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Antti - I ran into a similar problem - ISE would freeze when starting up. My solution was: a) delete the damaged.ise file and rebuild the project b) change the option in ISE to **NOT** load the previous file on startup by default. Make me do it manually. If Xilinx hadn't changed the .ise file to binary, this may have been easy to find and fix. XILINX - please change the .ise file back to text format! The binary version is a BAD idea for a bunch of reasons! John ProvidenzaArticle: 102926
ME TOO! PLEASE PLEASE! just the f**** up binary format - the cost for me was a perfectly wasted half a day. and I am not the only one - heavens sake a damaged file should not make an IDE to freeze !!! there is no reason for having the file in bin format - but if it is then it should be checked for correctness without causing system freezes AnttiArticle: 102927
ISE 8 already fucked me three projects, I had to rcecreate them. It is specially annoying, when each VHDL file is another directory. In ISE7 you could drag and drop files.Article: 102928
Bob, For IO timing, we specify the one standard, and use the following method: Simulate the IO standard we use as the standard with the pcb traces, package, and load in a SI program (liek Hyperlynx). The simulate the same IO with your specific standard. The difference in timing, will be the difference from the standard. Austin Bob wrote: > How does one, using the Virtex-4 datasheet, calculate IOB setup and hold > time requirements and global clock-to-out time for IO standards other than > LVCMOS25 fast 12mA? > > Thanks in advance, > Bob > >Article: 102929
"Telenochek" <interpasha@hotmail.com> wrote in message news:1148318946.683392.228470@j73g2000cwa.googlegroups.com... > > I am running into a problem: > Using my DMM, VCCAUX & VCCO seem to be shorted to GND. > At this point I am absolutely sure that they are shorted through the > Xilinx chip. It's probably nothing to worry about. Here are a couple of excerpts from a similar discussion on the SI mailing list: The reason is because of leakage current in transistors. As process technology progresses (180nm -> 130nm -> 90nm ...), the leakage current in a transistor gets bigger. That is, a transistor, even when it is "off", will have some current flowing through it. Also, you can pack more transistors onto a chip. Therefore, you end up with tens to hundreds of millions of leaky transistors, which leads to a low resistance when measured with an Ohm-meter. Because IC components are nonlinear, how much resistance you measure strongly depends on the ohmmeter's applied voltage. (Most ohmmeters don't apply a voltage, so don't expect a fixed value from your meter.) When measuring semiconductor junctions with an ohmmeter, the voltage developed (i.e., resistance) across a DUT will vary with the applied current, therefore, a different reading will be indicated depending on the scale (current source value) used. /MikhailArticle: 102930
Folks, After search the net for various eval boards, I haven't found the one that I need and afford... that is so oxymoronic... nevertheless, I figured I might try the community before making a decision. I am looking for an FPGA proto board that sits on a 64/66 PCI on a ATX motherboard. Since we are on a budget we would like to stick with low end devices such as Spartan 3 or Cyclone 2 with possibility to add more FPGA modules as we need them. I found one at http://www.4dsp.com/PCI.htm Unfortunately, it seems that it has a 32/33 pci interface. Any suggestions? Thank you. Best regards, -SanjayArticle: 102931
Hi Sanjay, I'm afraid I can't answer your question directly, but I can offer some food for thought. Be very careful treading into 64/66 PCI territory. The technology is new(ish), somewhat unproven, and mostly untested. I've had experience with board vendors that flat out lie about the 64/66 capability of the boards or at least they never bothered to test to see if it really worked. Be sure you REALLY need that extra throughput. Good luck MJArticle: 102932
Hi, I do not get exactly what it is you are looking for ? PCI TIM MotherBoard ? Rgds, John <fpgabuilder-groups@yahoo.com> a écrit dans le message de news:1148398325.753179.326230@38g2000cwa.googlegroups.com... > Folks, > > After search the net for various eval boards, I haven't found the one > that I need and afford... that is so oxymoronic... nevertheless, I > figured I might try the community before making a decision. > > I am looking for an FPGA proto board that sits on a 64/66 PCI on a ATX > motherboard. Since we are on a budget we would like to stick with low > end devices such as Spartan 3 or Cyclone 2 with possibility to add more > FPGA modules as we need them. > > I found one at http://www.4dsp.com/PCI.htm > > Unfortunately, it seems that it has a 32/33 pci interface. > > Any suggestions? > > Thank you. > Best regards, > -Sanjay >Article: 102933
Hi again, I have one of http://www.hunteng.co.uk/legacy_products/hepc4.htm plus a couple of TIM processing modules. If ever this is what you are looking for. Rgds, John <fpgabuilder-groups@yahoo.com> a écrit dans le message de news:1148398325.753179.326230@38g2000cwa.googlegroups.com... > Folks, > > After search the net for various eval boards, I haven't found the one > that I need and afford... that is so oxymoronic... nevertheless, I > figured I might try the community before making a decision. > > I am looking for an FPGA proto board that sits on a 64/66 PCI on a ATX > motherboard. Since we are on a budget we would like to stick with low > end devices such as Spartan 3 or Cyclone 2 with possibility to add more > FPGA modules as we need them. > > I found one at http://www.4dsp.com/PCI.htm > > Unfortunately, it seems that it has a 32/33 pci interface. > > Any suggestions? > > Thank you. > Best regards, > -Sanjay >Article: 102934
Falk Salewski wrote: > If I implement a function in an FPGA twice and do all these measures to make > sure that there are no functional interactions between theese two > implementations: What makes this implementation worse comparing to an > implementation based on two separate devices? The single power supply? If > this single piece of silizium is "faulty"? anything else? > > Regards > Falk S. > > Yes, both circuits share the same configuration circuitry. A fault in the configuration logic will render the whole device unprogrammable.Article: 102935
Hi, I am using Mediatronix picoBlaze to write assembly code for Xilinx picoBlaze and like to generate .hex or .svf file so that the code can be downloaded to the program rom via jtag port without re-synthesis. Could anyone advice me how to generate this type of file? Thank you in advance. S. C.Article: 102936
Just to follow up, we installed 8.1 and tried profiling again and it worked exactly as it should (the SDK gave us spinning, 3-D pie graphs and everything!). We followed the same steps as we had for 7.1, which didn't work for us. I think the moral is to use 8.1 if you are going to do any profiling.Article: 102937
johnp wrote: > Antti - > > I ran into a similar problem - ISE would freeze when starting up. My > solution was: > > a) delete the damaged.ise file and rebuild the project > b) change the option in ISE to **NOT** load the previous file on > startup by default. Make me do it manually. > > If Xilinx hadn't changed the .ise file to binary, this may have been > easy > to find and fix. > > XILINX - please change the .ise file back to text format! The binary > version is a BAD idea for a bunch of reasons! Perhaps now is a good time to ask Xilinx for a time-frame, when they WILL be making this fix ? IIRC there are other threads on the same time-sink flaw ? -jgArticle: 102938
I'm debugging a short delay generator with much higher resolution *right now* so I have some sensitivity for your issues. The biggest problem you may have with FPGA implementation of a delay generator is the jitter spec. The ECL outputs are not something you will find on standard eval boards. Expect to design your own board or have one designed for you to meet your specifications. The FPGA can do much of the hard work but interfacing to low-jitter ECL should involve some external registers times by a jitter-free clock to deliver the final ECL signals. ______ "amko" <sinebrate@yahoo.com> wrote in message news:1148383255.575687.208820@j33g2000cwa.googlegroups.com... Hello everybody, Currently I am designing very accurate delay generator, which will be based on FPGA . This delay generator should have similar technical requirements with DG535 http://www.thinksrs.com/products/DG535.htm. The major Delay Generator requirements are · 2 ns (1ns is desired, but 2ns will be also ok) time resolution on delayed channel (it means that time differences between any delayed channels can be set in 2 ns steps) · maximal 50 ps - 60ps (RMS) jitter on each output. · 14 delayed ECL channels · Two high speed (PECL) inputs (500 Mz ECL clock signal and ECL trigger) · Configurable via standard bus (Ethernet/USB/Serial bus) · Internal trigger with variable rate (DDS) · Internal clock oscillator · Clock master or slave Does anybody know for commercial available FPGA boards (preferred ISA (PC104) or PCI (PC104 plus) standards) that can be suitable for my requirements? Sutiable FPGA for my design is V5 or Stratix 2 GX. Thank you and Regrads, AmirArticle: 102939
On Tue, 23 May 2006 00:37:22 -0700, Eric Smith wrote:
> "alpha" <zhg.liu@gmail.com> writes:
>> [I am not trying to make binary compatiable with R3000. No delay slot.
> [...]
>> [I need think about it, thanks anyway. Of course, I do not want to get
>> any trouble]
>
> It appears that you've avoided the unaligned load/store instructions,
> which are patented.
I'm not familiar with the MIPS architecture, but the Motorola 68020 used
unaligned load/store (e.g., reading/writing a 32-bit word to an address
that was on an odd byte boundary) operations in the early/mid '80s. Do
you have a patent number at hand? I'm curious as to when this was
patented and what MIPS does that makes this patentable.
~Dave~
Article: 102940Well, I have a requirement for I2C or IIC communications to some video decoder chips on a new board I am designing. I would rather had not use this bus, but it seems that the Philips people have started a defacto standard in the video decoder world. So my questions are, what IO standard is best to use on a Virtex4, and what pullups should I use? The TI part I picked, the TVP5150AM1PBSR, has 3V3 volt digital connections. There are also two 1.8V requirements. And are there any free examples of VHDL that will drive slave devices. I have found an ap note Xapp172 Design of Video Capture but I can't find the source code downloads. I see on the Xilinx's Video Daughter Board (not V4) for the ML40x boards (are V4), that the SCL and SDA seem to be driven by a 3.3V bank7 and are pulled up with what I think are 4K. Weird BOM. Then I will have the issue of running multiple devices, more than are addressable by the hardwire addresing options. My first thought is to run multiple IOs from the V4. Is this the best solution? TMA Thanks Much in Advance, Brad Smallridge Ai Vision dot comArticle: 102941
Uncle Noah wrote: > Xilinx block RAM is synchronous read. Is this the source of your > problem? [YES, design was based on Altera Apex chip when it got started. This is why I need a newer altera board. Too expensive. Does anyone know if there is any chance to borrow one form Altera ? :) ]Article: 102942
Dave wrote: > On Tue, 23 May 2006 00:37:22 -0700, Eric Smith wrote: > > > "alpha" <zhg.liu@gmail.com> writes: > >> [I am not trying to make binary compatiable with R3000. No delay slot. > > [...] > >> [I need think about it, thanks anyway. Of course, I do not want to get > >> any trouble] > > > > It appears that you've avoided the unaligned load/store instructions, > > which are patented. > > I'm not familiar with the MIPS architecture, but the Motorola 68020 used > unaligned load/store (e.g., reading/writing a 32-bit word to an address > that was on an odd byte boundary) operations in the early/mid '80s. Do > you have a patent number at hand? I'm curious as to when this was > patented and what MIPS does that makes this patentable. > > > ~Dave~ This subject of load store word alignment has been pretty well done on c.a, google groups for John Mashey etc. He has several posts on it since he was there. There was a recent posting by an ex Lexra guy too who also went into the gory parts of it, Lexra was partly driven out of business by this licencing issue. I don't think MIPs did anything that wasn't already known about and hadn't been done countless times before probably all the way back to the earliest word machines. They almost admit as much, but the lawyers I guess forced it on them and they lucked out, nobody refuted it back then. I suspect it doesn't hurt anyone with a big enough patent portfolio since they usually have something more important on the other guy. I believe the particular patent expires soon, end of the year IIRC, not checking. I'd ignore it since the lawyers go after money and or companies with less patents, not experimenters. By the time they found out, they will be on the end of their rope. OTOH I can think of half a dozen instances of hardware software that I have done that are essentially the same thing done in different situations, boils down to mux demuxing of words and parts of. I wonder if eventually when all the CRTs are gone and the FPDs only have DVI Digital only ports, we won't be able to see anything on homebrew cpu without the DRM. Also we are starting to hear noise from political idiots about hitting on programmers whose tools can be used for hacking as well as good uses, that worries me more so. John Jakson transputer guyArticle: 102943
Hi,
I know this has been brought up many times in various groups but
here is my view on them and I would really appreciate some
clarification. I started working on FPGA design and stuff some 3 months
back or so. All the time I was switching back and forth between verilog
and VHDL for various projects. I personally feel that one can be very
productive as in time with Verilog? I only use VHDL if there is no
choice but I am not aganist VHDL or anything.
After some searching on google and various usenet groups I came
across many arguments regarding Verilog vs VHDL summarising either as
"use the right the tool for the right job" or "leading to language
wars". I am open-minded and I am biased to the former at the same time
a bit biased to verilog :) I just wanted to know some things.
-> Are there things that VHDL does better than verilog or vice-versa
-> What is the most widely used language in the industry i.e. FPGA and
ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
VHDL?
All kinds of thoughts, experiences and constructive criticisms will
be helpful.
cheers,
kishore.
Article: 102944-> Are there things that VHDL does better than verilog or vice-versa Enumerated data types. > What is the most widely used language in the industry i.e. FPGA and ASIC designs Probably 50-50. Cheers, JonArticle: 102945
On 23 May 2006 14:50:44 -0700, "Jon Beniston" <jon@beniston.com> wrote: >-> Are there things that VHDL does better than verilog or vice-versa > >Enumerated data types. > >> What is the most widely used language in the industry i.e. FPGA and ASIC designs > >Probably 50-50. Here is my very simple research: go to monster.com and search for verilog and vhdl keywords. Here are the results: verilog (%) vhdl (%) overall 387 (55) 320 (45) 100 miles around 104 (78) 30 (22) zipcode 94087 94087 is zipcode of Sunnyvale, CA.Article: 102946
It's usually said VHDL is more popular in Europe. Cheers, JonArticle: 102947
Brad Smallridge schrieb: > Well, I have a requirement for I2C or IIC communications to some video > decoder chips on a new board I am designing. I would rather had not use > this bus, but it seems that the Philips people have started a defacto > standard in the video decoder world. > > So my questions are, what IO standard is best to use on a Virtex4, and what > pullups should I use? The TI part I picked, the TVP5150AM1PBSR, has 3V3 volt 3.3 V LVCMOS or LVTTL is fine. Pull up of 4.7k to 10k is fine. > digital connections. There are also two 1.8V requirements. What kind of 1.8V requirements? For I2C communication? > And are there any free examples of VHDL that will drive slave devices. I There are some app notes that describe a I2C master/slave block, including VHDL source. I dont have the number handy. > I see on the Xilinx's Video Daughter Board (not V4) for the ML40x boards > (are V4), that the SCL and SDA seem to be driven by a 3.3V bank7 and are > pulled up with what I think are 4K. Weird BOM. Just fine. > Then I will have the issue of running multiple devices, more than are > addressable by the hardwire addresing options. My first thought is to run > multiple IOs from the V4. Is this the best solution? This is one solution. In similar situation were multiple devices with the same I2C address had to be connected to a I2C bus, we used I2C switches/MUXes. Philips offers them. Regards FalkArticle: 102948
YiQi wrote: > Dave, sorry for late reply. > ..... YiQi; In an earlier post you said: I got only only signal from the UART model saying that the transmit bus is empty(TBE) if 1 then empty. Here is what I do step by step: 1. until input arrive, then go to 1 2. read input if input = '1' then go to 3, else back to 1 3. put 'h' on the data bus, wait until TBE is 0 go to 4 4. wait until TBE = 1 then go to 5 5. put 'i' on the data bus, wait until TBE is 0 go to 6 6. wait until TBE = 1 then back to 1 it hang on step 5. wait for TBE to be 0 I would have said: 1) If the UART received a char (RDA = '1') then goto 2, else goto 1 2) Read the char from the UART. If the char is ASCII '1' (31h) then goto 3 else goto 1 ( rdSig <= '1'; if dbOutSig = x"31" then goto 3 ) 3) if the UART's Transmit Buffer is Empty (TBE = '1') then goto 4, else back to 3 4) write the 1st char into the UART (wrSig <= '1', dbInSig <= char in signal X) 5) if the UART's Transmit Buffer is Empty (TBE = '1') then goto 6, else back to 5 6) write the 2nd char into the UART ( wrSig <= '1', dbInSig <= char in signal Y ) DONE I doesn't look like your state-machine follows your step-by-step process. It's sending chars in X and Y and _then_ reading a char from the UART. It also looks like you're reading data from the UART and writing data to the UART at the same time (see state initSendX, where you set both rdSig and wrSig to '1'). I don't see the need for the process that writes into "send". This process is not related or synchronized to anything. HTH -Dave PollumArticle: 102949
Kishore wrote: > -> What is the most widely used language in the industry i.e. FPGA and > ASIC designs. I think VHDL is the dominant one as Xilinx totally uses > VHDL? Most Xilinx IP cores are delivered as VHDL for parameterization reasons, but we release a lot of Verilog code as well. Invariably when we release and application note with only one language we get an immediate request for the other. Personally I prefer Verilog (I find it quicker to code and debug in than VHDL), but I've written just about as much VHDL. Ed McGettigan -- Xilinx Inc.
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