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Messages from 10300

Article: 10300
Subject: Re: Xilinx Configuration Problem
From: z80@ds2.com (Peter)
Date: Sun, 10 May 1998 21:12:16 GMT
Links: << >>  << T >>  << A >>

Does a given bitstream file produce an identical result, in a
particular device?

Does a given bitstream file produce an identical result in several
devices?

This sort of behaviour can be easily achieved if you are e.g. gating
clocks, in which case you most likely won't be using the global clock
nets for clock distribution. This means that clocks will be routed
using normal interconnect (whose delays can vary), and if e.g. you
have a 16-bit counter, some of the stages will get clocked before
others. A counter (or a shift register) won't work unless the clock
skew is less than the clock-to-Q propagation delay - and C-Q prop
delays in present XC devices are extremely short, a lot shorter than
the typical interconnect delays.

The proper way to do FPGA design is to use the global clock nets for
all clocks, and use clock enables to decide which flipflop actually
gets clocked. But if you are trying to achieve low dynamic Icc, or
using an FPGA to prototype an ASIC (where clock gating is perfectly
OK, done properly) this global clock net business is a killer.


Peter.

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Article: 10301
Subject: Re: Xilinx Configuration Problem
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Mon, 11 May 1998 03:17:22 +0200
Links: << >>  << T >>  << A >>
Do you have pins that drive large cpacitors?

Are you _REALLY_ shure that _ALL_ your VCC/GND pins are connected?

Gerhard

-- 
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in the air:    D-8551
Article: 10302
Subject: Re: Xilinx Foundation and Linux
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Mon, 11 May 1998 03:29:32 +0200
Links: << >>  << T >>  << A >>
Nick Hartl wrote:
> 
> When you say Foundation though I tend to think not just of the place and
> route tools but the front end stuff (schematics, state machine editor,
> simulator and such).  I know nothing about Lunix ( outside of the usual

I think that Orcad IV STD works under Linux&DosEMU.
(ET4000W32 graphics card)

Gerhard
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Article: 10303
Subject: Re: Xilinx Foundation and Linux
From: Rickman <spamgoeshere1@yahoo.com>
Date: Mon, 11 May 1998 00:38:54 -0400
Links: << >>  << T >>  << A >>
Phil Ptkwt Kristin wrote:
> If the Xilinx tools alread run on various Unix platforms (I'm not too
> sure, but I think they at least run on Suns) then it won't be hard to port
> the GUI to Linux.  The only problem might be if they develop their GUI on
> Windows using MFC and then port to UNIX using some tool like Bristol or
> Mainsoft - neither of those tools support Linux yet, however, they could
> use the Willows TWIN API (which is free & under GPL, see: www.willows.com)
> to do the porting from Windows to Linux.  Either way, porting the GUI
> should be doable - of course the best thing is to do GUIs in Java, TCL/TK
> or some other portable GUI toolkit to avoid being locked into the Windows
> platform.
> 
> >
> >I am sure that if enough requests are heard for a Lunix place and route
> >tool the market will listen.
> 
> BTW: it's Linux not Lunix.
> 
> phil

-- 
I don't know for sure, but I have been told (quite a while back) that
most of the tool vendors (including the chip vendors) do all of their
developement work on Suns and port to PCs. I believe at the time this
was an explanation for the Unix versions coming out first. But maybe
things have changed over the years. I don't think the PC versions are
the last to be released anymore. 


Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10304
Subject: Re: Low power FPGA design
From: Rickman <spamgoeshere1@yahoo.com>
Date: Mon, 11 May 1998 00:55:25 -0400
Links: << >>  << T >>  << A >>
Nick Hartl wrote:
> Note often using the supplied clock enables on the a chip still clocks
> the register, it is just that the output is feed back when the clock is
> disabled.  So one must actually stop the from clock going to the
> register to save maximum power.
> 
> Have FUN!!
> Nick

-- 
I have always wondered just how much power would be saved by this. The
power is used when a node (any node, whether or not it is visible to the
user) is changed between a one and a zero. The amount of power used is
proportional to the capacitance of the node. 

If a FF is clocked with the output fed back to the input, the output
will not change state. The only nodes that change state are the clock
input itself and a small number of nodes internal to the FF. The FF
output consumes relatively more power to change state than the internal
nodes of a FF. I suspect that the clock input is also less power than
the FF output as well. So my guess is that there is not a lot of
difference between clocking a FF with the CE disabled and not clocking
it at all. 

Do you have any data on how much difference this makes? For example, if
you clock 100 FFs in a Xilinx part at 10 MHz with the outputs changing.
What percentage of this power is consumed when clocking at the same
speed, but with the CE held off. Then what percentage of the first
measurement is used when the FFs are not clocked at all (but with a 10
MHz clock into the chip)? Or maybe just make some number of ripple
counters and the same number of sync counters with a CE and compare the
three numbers; sync running, async running, sync stopped. 

If I had an easy way to measure the power of a chip, I would run this
myself. 



Rick Collins

rickman@XYwriteme.com

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Article: 10305
Subject: How to design frequency doubler ?
From: "chkcmc" <chkcmc@ms2.hinet.net>
Date: 11 May 1998 06:31:13 GMT
Links: << >>  << T >>  << A >>
Hello,

I want to design frequency doubler by using QuickLogic pASIC2 FPGA.
The input frequecy is 50MHz, and the internal signal need double to 100MHz,
the high and low duty is 1 : 1 closely.

how to make it ? 
give me a ideal, thanks very much


Chin-Horn Kuo
chkcmc@ms2.hinet.net
Article: 10306
Subject: Re: Low power FPGA design
From: botond@hotmail.com
Date: Mon, 11 May 1998 07:03:15 GMT
Links: << >>  << T >>  << A >>
In article <35518591.2F2FB2D4@diesel.eelab.usyd.edu.au>,
  Phil Cook <cook-pa@diesel.eelab.usyd.edu.au> wrote:
>
> I am beginning research on doing using a FPGA to implement a
> digital circuit for an implantable cardio defibrillator.  Due to the
> nature of the product, low power consumption is a primary concern.
> I was wondering if any one has any documentation or advice on
> doing a low power, low frequency design using an FPGA.  The chip
> will only need to be clocked at a few hundred hertz.
>
> Any help would be appreciated.
> TIA ,
>
> Phillip Cook.
>
>


  Hi Phil,
  I'm just curious whether you plan to use SRAM or antifuse based FPGAs.
Somewhere in this group I already read of Xilinx parts applied in aircraft
electronics, but I think SRAM based devices can't tolerate a direct
defibrillation shock. So what's your opinion ?

   Cheers,
   Botond

Botond Kardos - eMail: kardos@hu.matav.mail.NOJUNK
   To get my real address just put the domain
   name in reverse order and remove 'nojunk'.
   x@1.2.3.4 -> x@3.2.1

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Article: 10307
Subject: Neural Network implementation
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Mon, 11 May 1998 10:38:20 +0200
Links: << >>  << T >>  << A >>
Hello, I'm very interested in neural network implementation using
FPGA/CPLD.
Does somebody know a specific URL or site, available papers or thesis?
Thank you in advanced.

Sergio
--
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
email   : sergio@dtic.ua.es
===================================================================


Article: 10308
Subject: Re: Low power FPGA design
From: z80@ds2.com (Peter)
Date: Mon, 11 May 1998 08:40:11 GMT
Links: << >>  << T >>  << A >>

A very good question.

I have no hard data myself, but a while ago I did an ASIC prototype.
This made its way through a 3042, 3042A, 3064A, 3090A. Across all of
these I got a ratio of about 5x between static Icc (with the global
clocks gated OFF) and dynamic Icc (the whole thing clocked at 4MHz).

Due to various routing problems causing counters and shift registers
to sometimes not work (I describe these elsewhere in this NG) I
removed a lot of the (gated) local clocks and replaced them with
global clocks, and with CE gating. This worsened the dynamic Icc
"considerably".

I would guesstimate, from memory, that merely feeding a clock to a
non-CE-enabled D-type draws at least 1/2 of the power which it would
draw if you actually clocked it.

However I suspect that the *majority* of the dynamic Icc of an FPGA is
in the routing capacitance, not in the energy needed to flip the
D-types. Why, otherwise, would an FPGA draw 20mA (dynamic) when a
netlist-equivalent ASIC drew about 2mA? (These are the real figures
from my project.) I am sure that Xilinx can make D-types as good as
anyone else :)

As I keep saying here, and so far nobody has refuted it, in the recent
Xilinx parts the speed improvement of the D-types' C-to-Q delay is
better than the improvement in the interconnect delays. This is a
hypothesis of mine, based on the fact that in the old devices one
could freely use local interconnect, or long lines, to carry clocks to
things like counters - and gate these clocks off as required. This was
also recommended to me by Xilinx engineers at the time, as "OK". With
the current devices this simply doesn't work - you can easily end up
with counters which don't count properly. So, the biggest single
method of reducing the *dynamic* Icc of an FPGA - gating clocks to
chunks of logic - is no longer an option. Fortunately this works fine
in an ASIC, but it makes FPGA prototyping of an ASIC (a popular use of
FPGAs :)) somewhat tricky.

>I have always wondered just how much power would be saved by this. The
>power is used when a node (any node, whether or not it is visible to the
>user) is changed between a one and a zero. The amount of power used is
>proportional to the capacitance of the node. 
>
>If a FF is clocked with the output fed back to the input, the output
>will not change state. The only nodes that change state are the clock
>input itself and a small number of nodes internal to the FF. The FF
>output consumes relatively more power to change state than the internal
>nodes of a FF. I suspect that the clock input is also less power than
>the FF output as well. So my guess is that there is not a lot of
>difference between clocking a FF with the CE disabled and not clocking
>it at all. 


Peter.

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Article: 10309
Subject: Re: speed and area
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Mon, 11 May 1998 11:05:28 +0200
Links: << >>  << T >>  << A >>


Sidharta escribió:

> Hi everyone, I have a some questions about CPLD vs FPGA
>
> 1. When would you use CPLD and when would you use FPGA?
> 2. What are the effects of the ARCHITECTURE (macrocells, logic cells,
> routing, etc.) of both the CPLD and FPGA on the SPEED and chip AREA of the
> circuits implemented in them?
> 3. Is it true that the extra routing in FPGA makes it slower than CPLD?
> 4. So, which is more advantageous?
>
> Oh, another question. I'm using Altera Maxplus2 CAD tool. When
> implementing state machines, is the automatically generated state
> assignment always the best one? What is the guideline in doing state
> assignment, if we're to do it manually?
>
> Thank you.
>
> ( o )===:::
>   Bobby

 I think you need a book, for example "VHDL for programmable logic" , Kevin
Skahill (Addison Wesley). Althought it is dedicated to VHDL synthesis, in the
first chapter you´ll find the answers for yours FPGA/CPLD questions.

About the last question:
for smalls designs or when you are not tightly constrained for space, it is
probably fine to let the synthesis tool encode the states for you. However
sometimes it is possible improve the synthesis results yourself using
appropiated coding styles, for example  "one-hot" encoding (one register
dedicated to each state) can results in tremendous savings in the
combinational logic required for next-state and output encoding.

Sergio

--
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
email   : sergio@dtic.ua.es
===================================================================


Article: 10310
Subject: Re: Cool Clock Enable Synthesis Fix with Synplify 3.0b
From: "Tom Meagher" <tomm@icshou.com>
Date: Mon, 11 May 1998 09:07:25 -0500
Links: << >>  << T >>  << A >>
An update:  The code workaround described here produces the desired results with Exemplar 4.2.2, but
Synplify 3.0b still uses the clock enable inputs willy nilly, and (apparently) generates incorrect logic.

Tom Meagher


Article: 10311
Subject: Re: Altera relative placement
From: hayhoe@nortel.ca (Brent A. Hayhoe)
Date: 11 May 1998 16:33:18 GMT
Links: << >>  << T >>  << A >>

In article <35527a8f.2043057@news.sprint.ca>, ivan@caseware.NOSPAM.com (Ivan) writes:
>	
>	Is it possible to assign a relitave placement for the logic
>using Maxplus2?

Yes,  'cliques'.

>	Also, my pipeline stages are identical. I was wondering if it
>is possible to help the fitter fit and route one chunk of logic and
>then replicate the logic wherever it's needed.

Not in anything up to v8.3.

>	If this is not possible, what would be the best options to
>help Maxplus2 do the job correctly and completely?

The problem is, too many cliques can cause long fitting times,  as can not
enough.

The best way I've found (prompted by Altera) is to identify blocks that will
fit into rows and clique the block.  If you do this incrementally within your
design hierarchy,  you should be able to achieve a fit.

The fitter tries to place cliques in the order logic_cell, LAB, and finally row.

Once you have a layout,  you can change the cliques to row assignments.  The
fitter has less options to choose from and generally completes faster.

>	Ivan Hamer.


-- 

Regards,

 	Brent Hayhoe.

Nortel plc.,                                          Tel: +44 (0)1279-402937
Harlow Laboratories,  London Road,                    Fax: +44 (0)1279-439636
Harlow, Essex,  CM17 9NA,  U.K.                       Email: hayhoe@nortel.co.uk
                                                         or: hayhoe@nortel.ca


Article: 10312
Subject: Re: available eda environments
From: rajesh@comit.com
Date: 11 May 1998 19:09:05 GMT
Links: << >>  << T >>  << A >>
On Sun, 10 May 1998 12:27:08 -0400, Neil Horman <nrhorman@eos.ncsu.edu> wrote:

> Hello there all!

>      I'm trying to get started in some hardware design.  I've done alot

> in school, and now that I'm graduating I'd like to continue doing some

> fpga design at home.  Can anyone suggest an affordable eda environment

> that would run under windows NT or Linux on a DEC Alpha based machine?

> Thanks!

> -Neil Horman

> 

I used Quicklogic tools which contains silos verilog simulator

Synplify synthesis tool and quicklogic place and route tool

budled together. I heard that whole package costs around

$3000 



	They have 30 evaluation kit. Visit

http://www.quicklogic.com/products/pctools/

to get more information. I guess other vendors might also 

be having simillar products. I heard Xilinx tools and book 

for $90 for students. I am not aware of exact functionality



Xilinx also has "Foundation express" tool with Synopsys FPGA Express

and place and route tool. You need to check pricing from 

their marketing guys.



Hope this helps.

Rajesh



--

Rajesh Bawankule             | Checkout http://www.comit.com/~rajesh/verilog/

Hardware Engineering Manager | for Verilog FAQ

Comit Systems Inc.           | 

3375, Scott Blvd, #330       | Phone  : (408)-988-2988

Santa Clara, CA 94054        | Fax    : (408)-988-2133

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Article: 10313
Subject: Re: Xilinx Configuration Problem
From: "William L. Bahn" <bahn@bfe.com>
Date: Mon, 11 May 1998 13:49:31 -0600
Links: << >>  << T >>  << A >>

Gerhard Hoffmann wrote in message <355651A2.2B708D26@berlin.snafu.de>...
>Do you have pins that drive large cpacitors?
>

No. Just the inputs to two serial CMOS SRAMS and a couple of octal latches.
At present I even have those removed so the ONLY loads are four 100k pullup
resistors on static lines. All of the outputs are slew rate limited and the
behavior is the same at clock speeds from a few kiloHertz up to 40MHz.

>Are you _REALLY_ shure that _ALL_ your VCC/GND pins are connected?
>

Yes - but check me. In this part (the PP132 package) I see eight VCC and
eight GND pins. And I have two 47uF tantalum SMD capacitors and two 0.01 uF
ceramic SMD caps located on the component side of the PCB within the cavity
of the PGA socket and all of my power and ground traces are 30 mil wide.

But thanks for the suggestions.



Article: 10314
Subject: Re: Xilinx Configuration Problem
From: "William L. Bahn" <bahn@bfe.com>
Date: Mon, 11 May 1998 13:53:40 -0600
Links: << >>  << T >>  << A >>

Keith Wootten wrote in message ...
>In article <6j37rs$73h$1@newman.pcisys.net>, William L. Bahn
><bahn@bfe.com> writes
>>I have been working with a XC3142-3PP132 FPGA. I am using Xilinx's
>>Foundation Basic (Schematic Capture design entry) design tools and am
>>configuring the Xilinx using an Atmel AT17C128 Serial EPROM in the Master
>>Serial Mode.
>>
>>My problem is that nearly everytime I burn a new program into the PROM I
get
>>different results. The Xilinx appears to configure just fine and parts of
my
>>design work fine. But if I make a change to one part of the schematic (or
no
>>changes at all) then something changes in a completely different part of
the
>>schematic that wasn't touched. All of the IPADs and OPADs are pin-locked
>>using the LOC attribute.
>>
>[snipped]
>
>Do different PROMS programmed from the same bitstream give identical
>results?

Yes.

>
>After no material change to the schematic or any settings, is the new
>bitstream identical to the old one? (DOS file compare)
>


I will try it. I haven't thought of that because I figured they probably
wouldn't be identical since the router could have routed signals differently
based on even just a minor difference in the order of items in the netlist?
But it won't take long to try.



Article: 10315
Subject: Re: Xilinx Configuration Problem
From: "William L. Bahn" <bahn@bfe.com>
Date: Mon, 11 May 1998 14:01:20 -0600
Links: << >>  << T >>  << A >>

Peter Alfke wrote in message <3555E982.8230B208@xilinx.com>...
>William L. Bahn wrote:
>
>> I have been working with a XC3142-3PP132 FPGA. I am using Xilinx's
>> Foundation Basic (Schematic Capture design entry) design tools and am
>> configuring the Xilinx using an Atmel AT17C128 Serial EPROM in the
>> Master
>> Serial Mode.
>>
>> My problem is that nearly everytime I burn a new program into the PROM
>> I get
>> different results. The Xilinx appears to configure just fine and parts
>> of my
>> design work fine. But if I make a change to one part of the schematic
>> (or no
>> changes at all) then something changes in a completely different part
>> of the
>> schematic that wasn't touched. All of the IPADs and OPADs are
>> pin-locked
>> using the LOC attribute.
>>
>> Some of the things that are happening are simply crazy. For instance:
>>
>> I have a 4-bit counter (CB4CE) with CE tied to VCC and CLR tied to
>> GND. The
>> first three bits work but I get no output from the 4th bit or from
>> CEO.
>>
>> I also have a quadrature clock generator using an FD and an FD_1 block
>>
>> clocked with the same signal. The output signal from the FD block is
>> at half
>> the frequency of the clock signal (as expected) but the output from
>> the FD_1
>> block is at the SAME frequency as the clock signal.
>>
>> Plus a number of other crazy and intermittant things. If I use a
>> different
>> Xilinx (I have three of these parts) I get identical results and
>> reconfiguring the Xilinx doesn't seem to make a difference. So it does
>>
>> appear to be something in the bitstream. It's as if the schematic
>> netlister
>> (or something else further down the line) is randomly choosing to
>> disconnect
>> and/or misconnect a few of the pins each time. It's driving me insane.
>>
>> If anyone has ever experienced this type of behavior before or has any
>>
>> suggestions I would greatly appreciate them.
>>
>> TIA
>
>  Bill, what you are experiencing is definitely not normal.
>
>Since DONE must go High, I assume that the configuration process itself
>works properly.

It certainly appears to complete the configuration process - although with
one PROM program it didn't and just kept running the CCLK forever.

>Do you have a synchronous design, using global clock(s)? Asynchronous
>designs can be very nasty.

It is synchronous after my clock generator circuit. This is how it works: I
take an external clock and clock a 4-bit counter with it and then use a 8:1
mux to select the original clock, one of the four divided down clocks or one
of three other external clock sources. This becomes my "master clock" which
drives a quadrature clock generator that yields a set of four clocks at half
the master clock frequency that are quadrature related. The first two of
these are fed to the GCLK and ACLK buffers. At the present level of
implementation, I am only using the GCLK output to clock the rest of the
logic - but some of the un-implemented stuff will use the ACLK or have
inverted clock inputs using either the GCLK or the ACLK. Do you see any
problem with generating by GCLK and ACLK in this fashion.

>You can analyze a specific item, e.g. the fourth counter bit not
>toggling, in XACT, the graphics editor. It shows every internal
>connection.

I will look into this. Can it do it using the HEX file used to program the
SPROM? That would be best.


Thanks.


Article: 10316
Subject: Chicken & egg problem in PCI/CardBus designs using FPGA
From: George Fang <gfang@pop.slkc.uswest.net>
Date: Mon, 11 May 1998 21:59:10 -0600
Links: << >>  << T >>  << A >>
Hi,
    PCI and CardBus devices are detected at system boot-up. This is
going to be a problem when a FPGA is used as the PCI/CardBus controller
during development.
    The FPGA configuration data downloading program can only be
available after the system is fully up, but without a configured FPGA
the device under development is not going to be detected.
    Does anyone have a good solution for this? Is there a way to
re-invoke the device detecting process after the FPGA is configured?
    Thanks in advance for any information in this regard.

George.

Article: 10317
Subject: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
From: Steve Casselman <sc@vcc.com>
Date: Mon, 11 May 1998 22:48:24 -0700
Links: << >>  << T >>  << A >>
George Fang wrote:

> Hi,
>     PCI and CardBus devices are detected at system boot-up. This is
> going to be a problem when a FPGA is used as the PCI/CardBus
> controller
> during development.
>     The FPGA configuration data downloading program can only be
> available after the system is fully up, but without a configured FPGA
> the device under development is not going to be detected.
>     Does anyone have a good solution for this? Is there a way to
> re-invoke the device detecting process after the FPGA is configured?
>     Thanks in advance for any information in this regard.
>
> George.

   First you have to get the system to boot up with a minimal pci
interface so the OS can probe you and load your driver.  Then
if you have everything setup right you can reload the FPGA and
shove the pci configuration data back into it.  Once you have
this setup --  PCI development becomes much much easier.



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 10318
Subject: Re: Xilinx Configuration Problem
From: Steve Casselman <sc@vcc.com>
Date: Mon, 11 May 1998 22:55:29 -0700
Links: << >>  << T >>  << A >>
William L. Bahn wrote:
(* paraphrase *)  everytime I change something
something I did'nt touch messes up....

You should use a guide file.  You should also
think about place some of the stuff in your design
(not just the pins).  Also there are lots of timing
attributes you can put in your design that will
settle it down.  But first try a guide file approach.


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 10319
Subject: availability of EPC1LI20
From: paul@caemrad.com.au (Paul Teagle)
Date: 12 May 1998 05:56:03 GMT
Links: << >>  << T >>  << A >>
Hi

Can anyone help me find a source of industrial rated Altera EPC1s, ie, the EPC1LI20, in quantities less than the MOQ of 196 pieces the local rep. wants me to buy ? I guess we would have to buy them from the US. We only need about 10 pieces for a concept demonstrator.

regards,

Paul Teagle
CAE MRad


Article: 10320
Subject: Re: Low power FPGA design
From: Achim Gratz <gratz@ite.inf.tu-dresden.de>
Date: 12 May 1998 09:34:10 +0200
Links: << >>  << T >>  << A >>
z80@ds2.com (Peter) writes:

> I have no hard data myself, but a while ago I did an ASIC prototype.
> This made its way through a 3042, 3042A, 3064A, 3090A. Across all of
> these I got a ratio of about 5x between static Icc (with the global
> clocks gated OFF) and dynamic Icc (the whole thing clocked at 4MHz).

This is probably not the same thing as CE'ing the FFs.  Did the clock
still get distributed through the clock tree or not?

I'd think these are the components to Icc in a clocked circuit:

- static (all clocks stopped)
- clock global distribution (clock tree, but not going anywhere else)
- clock local distribution (clock routed to the FF from gate or global buffer)
- output toggling

So CE'ing does only avoid the fourth part, while gated local clocks
might skip on the second, depending on exactly how the routing works
and whether you need the global clock for something else.

Last time I used Altera 3200 w/SRAM I was wondering if it might be
better to use two global clocks or only one and quadrant clocks (the
second clock was only used in a small section of the design).  Since
the pins were fixed rather early and the part made the power budget
just fine with two global clocks I never tried this, though.


Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 463 - 8325
Article: 10321
Subject: Re: Low power FPGA design
From: Harald Vefling <hv@vingmed.no>
Date: Tue, 12 May 1998 09:59:34 +0200
Links: << >>  << T >>  << A >>
Peter wrote:

> However I suspect that the *majority* of the dynamic Icc of an FPGA is
> in the routing capacitance, not in the energy needed to flip the
> D-types. 

I believe this too, 

I once had a 80% full xc4020E running at 20MHz (DSP stuff)
Without floorplanning it ran close to 5W,
after preplacing the larger blocks to let signals 
flow nicely trough the design power dropped to aproximatly 2.5W. 
Global buffering and others being the same suggested to me 
that the reduction came from reduced wireing capacitance.

Harald
Article: 10322
Subject: Altera 3.3V and 5V
From: "John Huang" <hungi@tpts4.seed.net.tw>
Date: 12 May 1998 08:52:47 GMT
Links: << >>  << T >>  << A >>
Hi:
      I 've a problem with my design , could anyone can tell me that
3.3V and 5V chip has any differents?
     My current design using altera 10K20-3, it's 5V I/O chip, but
its speed is too slow that does not suit my timing, I've contact the
sales of altera, he tell me the -3 is the fastest chip of 10K20, If
I want a faster chip, they have 10K70 for -1, but it is 3.3V, but
my board's I/Os are connect to 5V chip, I wonder if they can't
work fine, can I replace 10K20 for 5V to 10K70 for 3.3V directly
?

	John Huang
	


Article: 10323
Subject: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
From: ems@see_sig.com (ems)
Date: Tue, 12 May 1998 08:56:01 GMT
Links: << >>  << T >>  << A >>
On Mon, 11 May 1998 22:48:24 -0700, Steve Casselman <sc@vcc.com>
wrote:

>George Fang wrote:
>>     Does anyone have a good solution for this? Is there a way to
>> re-invoke the device detecting process after the FPGA is configured?
>
>   First you have to get the system to boot up with a minimal pci
>interface so the OS can probe you and load your driver.  Then
>if you have everything setup right you can reload the FPGA and
>shove the pci configuration data back into it.  Once you have
>this setup --  PCI development becomes much much easier.

i presume you're talking about win95 here. if your device is
responsible for responding to pci configuration cycles, and it hasn't
been programmed, then there's no way to come up with a minimal pci
interface, and so no way to load a bitstream to the device.

in short, the pci interface must have at least a minimal working
functionality before the boot process begins. i'm not familiar with
cardbus, but i'm pretty sure that you have exactly the same problem.

there is, in principle, one possible workaround, which was discussed
in comp.os.ms-windows.programmer.vxd a few months ago (look up "Help
Allocating Physical Memory with PNP PCI Board" in dejanews). this
involved adding some 'minimal' external circuitry which latches the
address of configuration writes. this has a number of potential
problems, and my own opinion was that you'd have to have a *very* good
reason to try it.

evan (ems@nospam.riverside-machines.com)

Article: 10324
Subject: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
From: "p1v1t1=p2v2t2" <pvt@aol.com>
Date: Tue, 12 May 1998 12:02:33 +0200
Links: << >>  << T >>  << A >>

Best bet is to include an EEPROM serial interface an program your
register space configuration from it, at boot time.

George Fang wrote in message <3557C90E.9CE0C249@pop.slkc.uswest.net>...
>Hi,
>    PCI and CardBus devices are detected at system boot-up. This is
>going to be a problem when a FPGA is used as the PCI/CardBus controller
>during development.
>    The FPGA configuration data downloading program can only be
>available after the system is fully up, but without a configured FPGA
>the device under development is not going to be detected.
>    Does anyone have a good solution for this? Is there a way to
>re-invoke the device detecting process after the FPGA is configured?
>    Thanks in advance for any information in this regard.
>
>George.
>




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