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I am writing a interface about the ata interface but I have a problem that the dma request signal is sometimes always high when power up,and the hardware reset didn't work.So I don't have idea that what is the problem.Also I try the samsung hard disk drivers,and the hardware reset can reset the dma request signal to '0'!Article: 103251
bjzhangwn wrote: > I am writing a interface about the ata interface but I have a problem > that the dma request signal is sometimes always high when power up,and > the hardware reset didn't work.So I don't have idea that what is the > problem.Also I try the samsung hard disk drivers,and the hardware reset > can reset the dma request signal to '0'! If by "hardware reset" you mean the reset signal on the ATA interace, don't expect too much of it. The name is misleading, it does nothing near what a power cycling reset will do - and it may vary between vendors, especially when it comes to DMA and ATAPI combined (fortunately, ATAPI provides fast transfer mechanisms in PIO mode...). Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 103252
On Mon, 29 May 2006 04:59:58 -0700, Ron <News5@spamex.com> wrote: >Ben Jones wrote: >> Plenty of people would pay good money to have their compile >> times dropped from 12 hours to 12 minutes if the technology were available. > >Wow, I wish I had computers as powerful as yours. I've had a design >synthesizing using Xilinx Foundation 5.1 for 178 CPU hours thus far on a >Pentium 4 with 1.5 GBs RAM, and it's showing no signs of completing >anytime soon. Looks like I need to upgrade to a dual Opteron with many >gigs of RAM or something. Unfortunately those are *not* cheap. > >Can anyone recommend a computer system configuration (h/w and s/w) >specifically targeted at FPGA design and synthesis for under $5,000 or >so? A Sun Sparc workstation used to be considered top of the line, but >I'm not sure that's true anymore. I'm not sure that faster hardware would solve your compile time issue. What part? What design flow? Do you have excessive numbers of constraints? Watch out for, among other things, constraints with wildcards. Automatically generated constraints from third party synthesis tools can sometimes generate a huge number of constraints. Look for the <design_name>.ncf file. To debug this, try running the design with just a period constraint on every clock. If this completes in reasonable time, add constraints until it no longer runs in reasonable time, and then look carefully at the constraint(s) that breaks it. Before upgrading the hardware, have you considered upgrading the software? While the older software does some things better, run time and memory footprint have both gotten smaller. And it is fairly easy to have multiple versions on the same computer. Is the design paging? If the computer is paging, CPU utilization will be small, under 10%, and the disks will be running all the time. If so, then adding 0.5 G of memory might do the trick. That is about the limit with standard Windows. Standard WinXP has a 2 GB limit (3 GB with some hacking), and WinXP 64 isn't supported. As far as I know, all but the biggest parts should run with 2 GB or less. If you have to buy new higher end hardware, I'd suggest thinking about an Athlon dual core system with 4 GB RAM and RedHat 64. Yes, it is only about twice what you currently have, but it should be 1/3 the price of a 8GB Opteron system. -- Phil Hays (Xilinx, but speaking for himself)Article: 103253
Thanx Zara ..... this thing worked !! the peripheral is now connected to two opb buses now.... though along with the mpd file corresponding ports for the 2nd bus have to be added in the vhdl modules too ......Article: 103254
Note that somebody seems to have made up that far in the future "sometime in 2007". I know better... Peter AlfkeArticle: 103255
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1148929854.747791.35190@i40g2000cwc.googlegroups.com... > Note that somebody seems to have made up that far in the future > "sometime in 2007". > I know better... > Peter Alfke > well all the public info on V5xxT parts lists them available 2007 or is there some new update on the actual dates? sure the parts will come earlier internally but Xilinx had no forecast to deliver V5xxT parts this year. so we are all eyes and ears if there is an update on actual dates. I would of course also welcome if an PPC V5 part would be released 2006 even if no rocket io on it. V4FX12 is a nice part, smallest V5FX would be even better AnttiArticle: 103256
Antti Lukats wrote: > "Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag > news:1148929854.747791.35190@i40g2000cwc.googlegroups.com... > >>Note that somebody seems to have made up that far in the future >>"sometime in 2007". >>I know better... >>Peter Alfke >> > > well all the public info on V5xxT parts lists them available 2007 > or is there some new update on the actual dates? > > sure the parts will come earlier internally but Xilinx had no > forecast to deliver V5xxT parts this year. > > so we are all eyes and ears if there is an update on actual dates. > > I would of course also welcome if an PPC V5 part would > be released 2006 even if no rocket io on it. > > V4FX12 is a nice part, smallest V5FX would be even better > > Antti Antti, Xilinx (naturally) will be very cautious this time around. Things like fast serial IO do not take much silicon, but they do take large amounts of testing, and may need a tuning pass. Probably, they also want some field hours clocked up as well. All that, can easily add 6 months to a release time line. ES would be a different story, and it sounds like you and Peter should simply have a quiet word off-line ? :) -jgArticle: 103257
I am currently happy with the public information too AnttiArticle: 103258
Ron wrote > Wow, I wish I had computers as powerful as yours. I've had a design > synthesizing using Xilinx Foundation 5.1 for 178 CPU hours thus far on a > Pentium 4 with 1.5 GBs RAM, and it's showing no signs of completing > anytime soon. Looks like I need to upgrade to a dual Opteron with many > gigs of RAM or something. Unfortunately those are *not* cheap. 178 hours sounds wrong. A few suggestions for exploration: Relax the timing constraints and/or when target the design at a larger device. Partition or parameterise the design and check that there isn't something nasty going on. Beg or borrow a copy of Synplicity and see what that tool makes of the design.Article: 103259
Hi,
I am trying to use System Generator but it always shows the
following error no matter what type of blocks are used. Even demos are
showing the same error.
Error: "gcc.exe: installation problem, cannot exec `cc1': No such file
or directory" I don't know what does that mean. EDK is also showing the
same problem.
Configuraiton:
Windows XP SP2
Xilinx ISE 8.1i SP3
EDK 8.1i SP1
System Generator 8.1
Matlab R14 SP3
I checked and cc1 seems to be preprocessor or something also EDK
complains about cpp0. I checked the installation directory and found
cc1 and cpp0 at C:\Xilinx\gnu\MinGW\2.0.0-3\nt\lib\gcc-lib\mingw32\3.2
and tried setting the PATH variable to it but it only gave more errors.
What could be the problem here
thank you,
kishore.
Article: 103260What if I configure some IOB tu use a standard of 1.8v but vcco 3.8v? Will the FPGA be burned? Thanks in advace for answer MehdiArticle: 103261
GaLaKtIkUs=99 wrote: > What if I configure some IOB tu use a standard of 1.8v but vcco 3.8v? > Will the FPGA be burned? >=20 > Thanks in advace for answer > Mehdi oups 3.3v and not 3.8v!Article: 103262
Hi all, Is there a method for personalization of ISE?
One of the personalizations:
- For avoiding students to make errors in IOB proprties in UCF
files (the student's projects are for S3-Starter kit): is it possible
to add some step in the translate phase? I saw a perl interpreter
installed with ISE.
Cheers
Article: 103263"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1148964453.918613.319150@j33g2000cwa.googlegroups.com... > What if I configure some IOB tu use a standard of 1.8v but vcco 3.8v? > Will the FPGA be burned? no > > Thanks in advace for answer > Mehdi >Article: 103264
Antti Lukats wrote: > "GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag > news:1148964453.918613.319150@j33g2000cwa.googlegroups.com... > > What if I configure some IOB tu use a standard of 1.8v but vcco 3.8v? > > Will the FPGA be burned? > no > > > > > Thanks in advace for answer > > Mehdi > > ok. but will the design work normally? are the io vcco information stored in the bitstream and how does it affect the correct functionning of the fpga?Article: 103265
On 29 May 2006 09:56:32 -0700, "savs" <vidyutg@gmail.com> wrote: >Thanx Zara ..... this thing worked !! the peripheral is now connected >to two opb buses now.... though along with the mpd file corresponding >ports for the 2nd bus have to be added in the vhdl modules too ...... Ah, yes! Of course! I should rememeber to make answers less succint, more detailed. Sometimes I feel I express like Tarzan ;-) I'll try to improve my communication abilities. Best regards, zaraArticle: 103266
Hi Joel, Goto Project->Project Options->Generation in Coregen. There is a "Design Entry" option in which you can choose between Verilog and VHDL code generation. Regards, Srini.Article: 103267
Could somebody give me the format of type 1 and type 2 configuration headers.Article: 103268
Iam currently working on carbus project.I am really concerned with power delay factor in FPGA's especially Xilinx FPGA's .Will that create a problem for cardbus.Could somebody explain on, what all factors will affect the power up delay in SRAM based FPGA's.Article: 103269
this is described in the PCI specificationArticle: 103270
you can create a script to check the pad report (from par) to make sure pin locations and IO standards are correct for your particular demo design Aurash GaLaKtIkUs™ wrote: > Hi all, Is there a method for personalization of ISE? > One of the personalizations: > - For avoiding students to make errors in IOB proprties in UCF > files (the student's projects are for S3-Starter kit): is it possible > to add some step in the translate phase? I saw a perl interpreter > installed with ISE. > > Cheers >Article: 103271
Do you have any pdfs or documents on PCI system architecture?Article: 103272
you have to purchase the specification from PCISIGArticle: 103273
Hello, I am trying to program an RC-100 demo board, which contains a Spartan-II chip. The board is supposed to send three logic outputs to external devices through I/O pins provided on an expansion header. I am pretty sure I've coded the program correctly (only to the extent that it works as intended in simulation), but when I probe the I/O pins with a scope all I'm getting is what I assume is mains pick-up (50 Hz ~5Vpk-pk). My probes have been calibrated; the probe and scope have adequate bandwidth (greater than 5x the signal bandwidth), and I get the same result whether I use the 'Auto-scale' function or manually set the 'Volts' and 'Time' division scales to the capture the expected waveforms. In the event that the source of the problem isn't my code, does anyone have any suggestions as to what I might be doing wrong? Thanks, meesArticle: 103274
jpvarkey@gmail.com wrote: > Do you have any pdfs or documents on PCI system architecture? > Google for pci local bus specification revision 2.2 You might find the PDF :-) Alan
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