Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Mixing rising and falling-edge triggering is sometimes used to avoid hold-time problems when there is significant clock skew. Obviously, it reduces the max operating clock rate by more than half. A more conventional (and better and faster) approach uses low-skew global clock distribution, and then clocks all flip-flops on the rising edge. Peter Alfke, Xilinx ============ Marco wrote: > Hi, > I'm working with Spartan3 and ISE 7.1, simulating a small VHDL test > program I noted that signal updates within a process are done on clock > rising edges, while cuncurrent assignments, out of the process, are > done along falling edges. > Is it all correct? > Thanks, > MarcoArticle: 103426
Jim wrote: > I am using Xilinx ISE 8.1i on Linux. > > I have a bunch of Verilog and project files that I need to check in to > our version control system (Perforce) so others can work on them as > well. > > How do file paths in the project files are handled? For example, when I > work on the project the files are under /home/myname/... but when > somebody else opens the project he sees the files under > /home/othername/... > > Can I have relative references from the project file to the source > files? Yet another pain in the butt with the new and better binary project files. Back when the project files were text, you could open them up in any text editor and change all the paths to relative paths. The Xilinx tools all have handled relative paths perfectly for every version of the software I have ever used, but now there seems to be no way to use them.Article: 103427
Falk Brunner wrote: > Peter Alfke schrieb: > >> The faster the circuitry, the smaller your "no-man's land" of >> uncertainty, and the faster the resolutio. I would, therefore, go with >> the fastest LUT-based FPGA. You can imagine which one I have in mind. > > > 22V10 ?? > > SCNR ;-) When Peter wrote that, my imagination jumped to the new (claimed ) 2GHz Async FPGAs , still comming... ;) -jgArticle: 103428
Adam Megacz wrote > > I've been having a really hard time coming up with a design for a > robust clockless arbiter in an FPGA, and was wondering if anybody here > can provide input. By robust, I mean that it works correctly with > probability=1 and its output never glitches, but may take an unbounded > amount of time to resolve. Googling for "self-timed arbiter fpga" throws up several hits. At a very quick glance, this paper http://www.cl.cam.ac.uk/~swm11/research/papers/iccd1998.pdf seems relevant. In essence it's externally self-timed, but generates an internal clock when needed. Here is a quote from the paper, supporting other remarks in this thread: "Designing an arbiter on an FPGA is even more dificult. In order to minimise metastability effects the built in flip-flops must be used. typically D-latches. since they will have the highest gain and lowest feedback times."Article: 103429
Falk Brunner (Falk.Brunner@gmx.de) wrote: : Alexander Werger schrieb: : > Hi, : > in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 : > device the maximum frequency is about 110 MHz (55MIPS). : > In the Picoblaze product brief : > (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf) : > the performance is 102 MIPS -> 204MHz. : > Anybody has an idea how to increase the maximum frequency on our Picoblaze : > test implementation? Is there any reference implementation for the V4 FX12 : Register the IO-bus. If you dont need access to BRAM via the IO bus, : this will increase clock speed significantly. I remember Picoblaze : reacing ~ 80 MHz in Spartan-3. I'd second that - the Picoblaze reads IO on the second clock of the instruction so you get one register for free (timingwise). One design I have needs two levels of registers to meet timing and I can afford to compensate for this in the software. (So actually the second level of registers are only there to placate the timing analysis...) I don't think the scratchpad is in the critical path, but if it is and you're not using it you could try cutting it out. Looking at page 14 of ug129 the mux between the ALU/INPORT and the register file may be critical, so again if you don't need the scratchpad perhaps using that for IO with direct addressing and removing the INPORT and the downstream mux could speed things up. An interesting project might be to automate the examination of the assembly file for a design and remval of unused ports / ALU functions etc. and see how much difference it makes. cheers cdsArticle: 103430
Since signals A and B are each driven through interconnects with unavoidable delay differences, any attempt to find out which of the two signals arrived first has an unavoidable error. That error is much larger than the width of the metastability capture window, which is only fractional femtoseconds in a modern FPGA flip-flop. The stated problem is not only unsolvable, but inherently meaningless. How many angels can dance on the tip of a pin? Peter Alfke, Xilinx ================== Adam Megacz wrote: > I've been having a really hard time coming up with a design for a > robust clockless arbiter in an FPGA, and was wondering if anybody here > can provide input. By robust, I mean that it works correctly with > probability=1 and its output never glitches, but may take an unbounded > amount of time to resolve. > > Charles Seitz describes a solution in custom VLSI on page 260 of Mead > and Conway's _Introduction to VLSI Systems_, but this assumes you have > control over gate threshholds and can make some of them substantially > higher than others. > > The basic component that causes problems is the "interlock", a module > with two inputs A,B and two outputs X,Y. > > +---------------+ > A -----> | | -----> X > | Interlock | > B -----> | | -----> Y > +---------------+ > > All signals start low. If A+ (A rises) before B+, then X+. If B+ > before A+, then Y+. Once one of the outputs rises, the other one will > not rise until the device is reset (assume some sort of reset signal). > The important part here is that the interlock can take as long as it > likes to raise one of the outputs, but it must raise exactly one of > them, and cannot lower it once raised (ie no glitching). > > I'm working with Atmel FPGAs, but advice based on other devices would > be just as helpful. I thought of using the "internal feedback line" > to feed one of the 3-LUT's outputs back into one of its inputs as half > of an interlock -- the state of the feedback line being used to > determine if signal A+ has already arrived. But the problem is that > you might have A+ arrive, which causes the output of the 3-LUT to > transition, but then B+ might arrive *before* the LUT's output > transition arrives back at the third input to the LUT. > > Any pointers? I've come across a rather depressing paper concluding > that this isn't possible on the (extremely old) XC4000, but I'm sort > of hoping against hope that things may have changed: > > http://www.iccd-conference.org/proceedings/1998/90990360.pdf > > This paper claims to have a solution, but doesn't go into detail, so I > suspect that they may be overlooking something. > > http://citeseer.ist.psu.edu/maheswaran94hazardfree.html > > Thanks for any pointers... > > - a > > -- > PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 103431
Peter Alfke wrote: >Since signals A and B are each driven through interconnects with >unavoidable delay differences, any attempt to find out which of the two >signals arrived first has an unavoidable error. That error is much >larger than the width of the metastability capture window, which is >only fractional femtoseconds in a modern FPGA flip-flop. > > I think in the case where the two inputs rise almost simultaneously, then it may be more important that the arbiter resolves one and only one output, than it correctly identify which one was first. JonArticle: 103432
Un bel giorno Adam Megacz digitò: > By robust, I mean that it works correctly with > probability=1 I think Heisenberg would have something to argue about this. -- asdArticle: 103433
Jon Elson wrote: > > I think in the case where the two inputs rise almost simultaneously, then > it may be more important that the arbiter resolves one and only one output, > than it correctly identify which one was first. > > Jon That's what I addressd in my first response: "If you reduce your requirements to an unambiguous output, even if it is the "wrong" one (whatever wrong means when things happen essentially simultaneously) then the problem reminds me of metastability resolution, which will usually occur in a short time (although theoretically -but only theoretically- unbounded)." Given any specific test condition, every additional nanosecond of tolerable output delay increases the MTBF by ten decimal orders of magnitude (every extra 100 ps increases the MTBF a factor of ten). This was taken from XAPP094, which describes metastable recovery, essentially the same problem... And Heisenberg is in agreement, I checked with him ;-) Peter Alfke, XilinxArticle: 103434
Many thanks, Austin, for your reply. --- Jim "Austin Lesea" <austin@xilinx.com> wrote in message news:e5ki8v$8a712@xco-news.xilinx.com... > Jim, > > The CPLD you note is a 3.3V part, with a 5V input tolerance. Any > outputs will swing from 0 to 3.3V, not 0 to 5V. > > Other than that, inverting, or not inverting a signal is no problem > (selection of a 2:1 mux with the inverted and non-inverted signal as > inputs, output driving a pin). > > The jitter added is on the order of 20-50 ps p-p (a simple 74HC04 > inverter adds as much, and the delay will be something that you can get > as a report from the design tools). > > Austin > > Jim wrote: >> Hi, >> >> Apologies upfront if this is a really basic question, as I am rather new >> to >> CPLDs. >> >> We have a 0-5V squarewave (approx 1MHz, approx 50% duty) that we wish to >> use >> as the clock to a Xilinx CPLD (XC9572XL). We need to select at runtime >> whether to clock on its rising edge or its falling edge. To achieve this, >> my >> current thinking is to run this signal into a spare pin on the Xilinx. A >> control line into the Xilinx will tell it to either invert the signal or >> output it unchanged. This inverted/uninverted clock signal will then >> connect >> to the Xilinx pin assigned as its clock source. >> >> Just wondering, does that sound seinsble, and is there anything I should >> be >> wary of doing it this way? As I say, I am new to CPLDs so please don't >> rule >> out something you believe to be too obvious to mention, thanks! The only >> thing I can think of currently is the amount of delay added by the extra >> routing of the clock, plus increased jitter. However, they should both be >> within our requirements. >> >> Many thanks in advance. >> >> --- >> Jim >> >> >>Article: 103435
Hi All, Not sure if this is the right forum ... please point me if otherwise. I am a hobbyist and making my first foray into building custom hardware. I am interested in building my own VoIP device say using a Broadcom chip http://www.broadcom.com/products/Enterprise-Small-Office/IP-Phone-Products/BCM1112 As a total novice in this area, I would appreciate it if one could tell me how to to go about building a device (step-by-step)? 1) Raw material required - PCBs, components, etc. 2) How to combine them correctly? 3) Expertise - although I am a novice, I am always willing to read up, or is it that an expert is definitely required Basically, I am unhappy about the current state of hardware, where I have to pay for separate devices for every small feature I need. Thanks.Article: 103436
Guys/Gals, I am primarily an Altera developer at work, so I have a lot more experience with Quartus than ISE. (our site develops with both Altera and Xilinx designs, but most of my projects have involved Altera devices) However, as the proud recipient of a Spartan 3E sample pack board, I decided to give it a go. I am using the tool chain at work, because our site has the 7.1 EDK and ChipScope tools installed. (EDK may be overkill on a xc3s100e, but ChipScope seems like a useful tool) We haven't licensed the 8.1i tool chain yet, so I don't have access to it at work - though I can try it at home. The problem is that the tool seems to have LOC's and BANK's confused. I created a shell VHDL file that has all the I/O on the board defined, and assigned each signal a static level just to get the project going. I then started a new ISE project, told it to add my top-level VHD file, and assigned the part. This all works fine, and the correct part number is listed (xc3s100e-tq144). Next, I run the "Assign Package Pins" to set the pinout. ISE creates a blank .ucf file, and presents me with the PACE editor. This is where the rub is. When I click on fields under LOC, I get bank numbers - not pin locations. If I try to enter the pin location, the entry is deleted. So, I try to get fancy, and create my own .ucf file: Net Clock_50 LOC = "122" | IOSTANDARD = LVCMOS33 ; Net FL_Status LOC = "66" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<0> LOC = "98" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<1> LOC = "97" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<2> LOC = "96" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<3> LOC = "94" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<4> LOC = "93" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<5> LOC = "92" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<6> LOC = "91" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<7> LOC = "88" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<8> LOC = "87" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<9> LOC = "86" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<10> LOC = "85" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<11> LOC = "82" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<12> LOC = "81" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<13> LOC = "77" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<14> LOC = "76" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<15> LOC = "75" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<16> LOC = "74" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<17> LOC = "70" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<18> LOC = "68" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<19> LOC = "67" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<20> LOC = "44" | IOSTANDARD = LVCMOS33 ; Net FL_Addr<21> LOC = "83" | IOSTANDARD = LVCMOS33 ; Net FL_Data<0> LOC = "63" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<1> LOC = "89" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<2> LOC = "58" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<3> LOC = "54" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<4> LOC = "53" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<5> LOC = "52" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<6> LOC = "51" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<7> LOC = "50" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<8> LOC = "78" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<9> LOC = "84" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<10> LOC = "89" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<11> LOC = "95" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<12> LOC = "101" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<13> LOC = "107" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<14> LOC = "111" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_Data<15> LOC = "114" | IOSTANDARD = LVCMOS33 | PULLUP ; Net FL_WE_n LOC = "103" | IOSTANDARD = LVCMOS33 ; Net FL_CE0_n LOC = "104" | IOSTANDARD = LVCMOS33 ; Net FL_OE_n LOC = "105" | IOSTANDARD = LVCMOS33 ; Net FL_Byte_n LOC = "106" | IOSTANDARD = LVCMOS33 ; Net PortA<0> LOC = "14" | IOSTANDARD = LVCMOS33 ; Net PortA<1> LOC = "15" | IOSTANDARD = LVCMOS33 ; Net PortA<2> LOC = "16" | IOSTANDARD = LVCMOS33 ; Net PortA<3> LOC = "17" | IOSTANDARD = LVCMOS33 ; Net PortB<0> LOC = "20" | IOSTANDARD = LVCMOS33 ; Net PortB<1> LOC = "21" | IOSTANDARD = LVCMOS33 ; Net PortB<2> LOC = "22" | IOSTANDARD = LVCMOS33 ; Net PortB<3> LOC = "23" | IOSTANDARD = LVCMOS33 ; Net PortC<0> LOC = "25" | IOSTANDARD = LVCMOS33 ; Net PortC<1> LOC = "26" | IOSTANDARD = LVCMOS33 ; Net PortC<2> LOC = "29" | IOSTANDARD = LVCMOS33 ; Net PortC<3> LOC = "32" | IOSTANDARD = LVCMOS33 ; Net PortD<0> LOC = "33" | IOSTANDARD = LVCMOS33 ; Net PortD<1> LOC = "34" | IOSTANDARD = LVCMOS33 ; Net PortD<2> LOC = "35" | IOSTANDARD = LVCMOS33 ; Net PortD<3> LOC = "40" | IOSTANDARD = LVCMOS33 ; Net P1 LOC = "6" | IOSTANDARD = LVCMOS33 ; NET P2 LOC = "10" | IOSTANDARD = LVCMOS33 ; NET P3 LOC = "8" | IOSTANDARD = LVCMOS33 ; NET P4 LOC = "12" | IOSTANDARD = LVCMOS33 ; NET LED<1> LOC = "142" | IOSTANDARD = LVCMOS33 ; NET LED<2> LOC = "43" | IOSTANDARD = LVCMOS33 ; NET LED<3> LOC = "2" | IOSTANDARD = LVCMOS33 ; NET LED<4> LOC = "3" | IOSTANDARD = LVCMOS33 ; NET LED<5> LOC = "4" | IOSTANDARD = LVCMOS33 ; NET LED<6> LOC = "5" | IOSTANDARD = LVCMOS33 ; NET LED<7> LOC = "7" | IOSTANDARD = LVCMOS33 ; NET Button LOC = "18" | IOSTANDARD = LVCMOS33 ; NET WE_A LOC = "140" | IOSTANDARD = LVCMOS33 ; NET OE_A LOC = "139" | IOSTANDARD = LVCMOS33 ; NET CSA LOC = "135" | IOSTANDARD = LVCMOS33 ; NET LSBCLK LOC = "134" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<0> LOC = "132" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<1> LOC = "131" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<2> LOC = "130" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<3> LOC = "129" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<4> LOC = "128" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<5> LOC = "126" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<6> LOC = "125" | IOSTANDARD = LVCMOS33 ; NET MA1_DB<7> LOC = "124" | IOSTANDARD = LVCMOS33 ; NET MA1_AStb LOC = "123" | IOSTANDARD = LVCMOS33 ; NET MA1_DStb LOC = "113" | IOSTANDARD = LVCMOS33 ; NET MA1_Write LOC = "117" | IOSTANDARD = LVCMOS33 ; NET MA1_Wait LOC = "116" | IOSTANDARD = LVCMOS33 ; NET MA1_Reset LOC = "56" | IOSTANDARD = LVCMOS33 ; NET MA1_Int LOC = "112" | IOSTANDARD = LVCMOS33 ; NET GPIO_CCLK LOC = "71" | IOSTANDARD = LVCMOS33 ; NET GPIN_0 LOC = "136" | IOSTANDARD = LVCMOS33 ; NET GPIN_1 LOC = "141" | IOSTANDARD = LVCMOS33 ; NET GPIN_p LOC = "119" | IOSTANDARD = LVCMOS33 ; NET GPIN_n LOC = "120" | IOSTANDARD = LVCMOS33 ; (Note, I had a technician at work route some unused I/O to the connector) This seems to work, until I get to the mapping phase, where EVERY SINGLE LOCATION is invalid. I get a string of warning messages like the following: ERROR:MapLib:30 - LOC constraint 122 on Clock_50 is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. BTW - for owners of this board, Clock_50 is the 50MHz clock on GCLK4. So, did I do something wrong, or is my install of ISE 7.1i fouled up? I did a clean install of ISE 7.1i to a "virgin" machine (no other version of ISE has ever been installed on this system) and applied SP4. I then installed the EDK, and ChipScope. Note, when I go into PACE, the pin data shows up in the correct column, but if I try to change it, the field is erased as before. Thanks! -SethArticle: 103437
be.geek@gmail.com wrote: >Hi All, >Not sure if this is the right forum ... please point me if otherwise. >I am a hobbyist and making my first foray into building custom >hardware. I am interested in building my own VoIP device say using a >Broadcom chip >http://www.broadcom.com/products/Enterprise-Small-Office/IP-Phone-Products/BCM1112 Make sure you get the datasheet with all register/timeing details etc. Before even considering the chip. Broadcom have required NDA previously. You should make sure you are aware of it's implications. This caused some trouble writeing drivers for oss systems. The chip is BGA (http://en.wikipedia.org/wiki/BGA) which is not novice friendly package at all. You will need to heat it to ca 180 °C and then heat it to 230 °C (?) for like 20s. This is done with IR heat asfair. Converted kitchen ovens are reported to be useful too ;) >As a total novice in this area, I would appreciate it if one could tell >me how to to go about building a device (step-by-step)? >1) Raw material required - PCBs, components, etc. Get a electric cad program. If you want it free use gschem/pcb. To have the pcb made you need to have the gerber files (.gbr). >2) How to combine them correctly? Read said datasheets and consider what you want into your "box". Pay attention to grounding, decoupling, impedance, termination, power circuitry. They will cause trouble anytime you forget them ;) >3) Expertise - although I am a novice, I am always willing to read up, >or is it that an expert is definitely required >Basically, I am unhappy about the current state of hardware, where I >have to pay for separate devices for every small feature I need. It will happen as long as people won't do like you maybe will ;)Article: 103438
Hi, For a SP3 TQ144 package I use UCF statements like: NET "cpuData<0>" LOC = P141 | IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=8; Also make sure you are actually driving or reading the pin with your design, otherwise the tools will strip it out and fail to attach the LOC constraint. But in that case I think it gives a different error message than the one you are getting... Regards Andrew radarman wrote: > Guys/Gals, > ....Article: 103439
Why system generator block accepts delay block with zero latency. I always thought latency is actually the delay if that's right delay block should have minimum of 1 latency. Is my understanding is wrong if not than can some buddy tell me what is the difference between latency and delay and why delay block can have zero latency ThanksArticle: 103440
Thanks a lot for the reply. I am learning already ... :) Will start out modest as suggested to get a hang of things. -- pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > be.geek@gmail.com wrote: > >Hi All, > > >Not sure if this is the right forum ... please point me if otherwise. > > >I am a hobbyist and making my first foray into building custom > >hardware. I am interested in building my own VoIP device say using a > >Broadcom chip > >http://www.broadcom.com/products/Enterprise-Small-Office/IP-Phone-Produc= ts/BCM1112 > > Make sure you get the datasheet with all register/timeing details etc. Be= fore > even considering the chip. Broadcom have required NDA previously. > You should make sure you are aware of it's implications. This caused some > trouble writeing drivers for oss systems. > > The chip is BGA (http://en.wikipedia.org/wiki/BGA) which is not novice > friendly package at all. You will need to heat it to ca 180 =B0C and then > heat it to 230 =B0C (?) for like 20s. This is done with IR heat asfair. > Converted kitchen ovens are reported to be useful too ;) > > >As a total novice in this area, I would appreciate it if one could tell > >me how to to go about building a device (step-by-step)? > >1) Raw material required - PCBs, components, etc. > > Get a electric cad program. If you want it free use gschem/pcb. > To have the pcb made you need to have the gerber files (.gbr). > > >2) How to combine them correctly? > > Read said datasheets and consider what you want into your "box". > Pay attention to grounding, decoupling, impedance, termination, power > circuitry. They will cause trouble anytime you forget them ;) > > >3) Expertise - although I am a novice, I am always willing to read up, > >or is it that an expert is definitely required > > >Basically, I am unhappy about the current state of hardware, where I > >have to pay for separate devices for every small feature I need. >=20 > It will happen as long as people won't do like you maybe will ;)Article: 103441
Are there any starter kits out there to begin with? I do do SW, but hope that I can run Linux on it with little or no modifications. -- Dave wrote: > On Thu, 01 Jun 2006 17:55:53 -0700, be.geek wrote: > > > Hi All, > > > > Not sure if this is the right forum ... please point me if otherwise. > > > > I am a hobbyist and making my first foray into building custom > > hardware. I am interested in building my own VoIP device say using a > > Broadcom chip > > http://www.broadcom.com/products/Enterprise-Small-Office/IP-Phone-Products/BCM1112 > > > > As a total novice in this area, I would appreciate it if one could tell > > me how to to go about building a device (step-by-step)? > > 1) Raw material required - PCBs, components, etc. > > 2) How to combine them correctly? > > 3) Expertise - although I am a novice, I am always willing to read up, > > or is it that an expert is definitely required > > > > Basically, I am unhappy about the current state of hardware, where I > > have to pay for separate devices for every small feature I need. > > You might want to set your sights a little lower, initially. Start with > some simple schematics you draw and then breadboard and debug. Work to > more complexity and then begin to fab some simple PCBs. Learn soldering > with simple components first before you try expensive parts--it is not as > simple as it seems, especially for small closely spaced leads. BGAs are a > whole different story as far as soldering. > > Do you program? SW will be a major component of your finished design. > > > ~Dave~Article: 103442
On Thu, 01 Jun 2006 17:55:53 -0700, be.geek wrote:
> Hi All,
>
> Not sure if this is the right forum ... please point me if otherwise.
>
> I am a hobbyist and making my first foray into building custom
> hardware. I am interested in building my own VoIP device say using a
> Broadcom chip
> http://www.broadcom.com/products/Enterprise-Small-Office/IP-Phone-Products/BCM1112
>
> As a total novice in this area, I would appreciate it if one could tell
> me how to to go about building a device (step-by-step)?
> 1) Raw material required - PCBs, components, etc.
> 2) How to combine them correctly?
> 3) Expertise - although I am a novice, I am always willing to read up,
> or is it that an expert is definitely required
>
> Basically, I am unhappy about the current state of hardware, where I
> have to pay for separate devices for every small feature I need.
You might want to set your sights a little lower, initially. Start with
some simple schematics you draw and then breadboard and debug. Work to
more complexity and then begin to fab some simple PCBs. Learn soldering
with simple components first before you try expensive parts--it is not as
simple as it seems, especially for small closely spaced leads. BGAs are a
whole different story as far as soldering.
Do you program? SW will be a major component of your finished design.
~Dave~
Article: 103443Andrew FPGA wrote: > Hi, > ... Thanks! That worked great. Apparently the 'P' is important. However, I still don't know why I couldn't enter the information using PACE. The drop-down boxes showed bank numbers, not pin numbers - and the column for BANK was grayed out. Still, typing the info directly into the .ucf is much quicker, so I'm not that disturbed by that. (yet) As an aside, I discovered that Digilent did some strange things when they built this board. Half of the flash-bus is input-only. 2 of the 8 signals in MA1_DB are input-only. I would have dropped some of the other signals to make all of the databus read-write - but hey, it was free! -SethArticle: 103444
I think we have a working workaround. Let's say the project root at /home/myname/myproject. Make a directory called 'stable_root' (or any other name you like) under /usr/local. Then run the command 'mount --bind /home/myname/myproject /usr/local/stable_root'. This will map your project root to /usr/local/stable_root. Now, use in your ISE project only file pathes that start with /usr/local/stable_root. When other users need to work on the project, they should do the same mapping and the paths in the project will work for them. Notes: 1. Setting up /usr/local/stable_root as a symbolic link to /home/myname/myproject does not work. 2. In Windows this can be done using the 'subst' command. Simply define a stable driver letter 'y:' to the root of your project. Hope this helps. Jim Jim wrote: > I am using Xilinx ISE 8.1i on Linux. > > I have a bunch of Verilog and project files that I need to check in to > our version control system (Perforce) so others can work on them as > well. > > How do file paths in the project files are handled? For example, when I > work on the project the files are under /home/myname/... but when > somebody else opens the project he sees the files under > /home/othername/... > > Can I have relative references from the project file to the source > files? > > Any other suggestion? > > Thanks, > > JoeArticle: 103445
"Fizzy" <fpgalearner@gmail.com> wrote in message news:1149211987.152172.169510@g10g2000cwb.googlegroups.com... > Why system generator block accepts delay block with zero latency. I > always thought latency is actually the delay if that's right delay > block should have minimum of 1 latency. Is my understanding is wrong if > not than can some buddy tell me what is the difference between latency > and delay and why delay block can have zero latency > > Thanks > I'm getting dizzy. BobArticle: 103446
Hi Peter, I wanted to know few things from your explaination. 1) Did you mean that you can use both Debugger (xmd) and Chip scope at the same time? 2) You mentioned a nice point saying " stop the processor on a Chipscopre trigger event or trigger ChipScope on a software breakpoint" How do you do this ? I am verymuch curious to know more about this. If you can send me some links, then it will be really nice. Regards, saumyajit Peter Ryser wrote: > XMD and ChipScope DO coexist on the same JTAG chain. You can even > cross-trigger, i.e. stop the processor on a Chipscopre trigger event or > trigger ChipScope on a software breakpoint to get a complete picture of > your hardware/software system at the time of the event. > > - Peter > > Ben Jones wrote: > > Hi Joel, > > > > "Joel" <jceven@gmail.com> wrote in message > > news:1149173927.595412.96800@h76g2000cwa.googlegroups.com... > > > >>Xilinx gurus, > > > > > >>I want to use a ChipScope ILA or 2 in an EDK design. > >>... > >>What say you Xilinx gurus out there? > > > > > > What version of EDK are you using? > > > > To the best of my knowledge, the chipscope ILA, IBAs and VIO modules are > > available in the EDK IP catalog (under "Debug"). You can drop these in just > > like any other IP block (you need to add a chipscope "ICON" block and wire > > that up too). > > > > Not sure whether the debugger and chipscope will co-exist on the same JTAG > > chain (I'm fairly sure they won't). I believe you can get round this by > > means of a debugger connection over RS232, using an XMD "stub" - but don't > > quote me on that; I never did it! > > > > Cheers, > > > > -Ben- > > > >Article: 103447
Hello all,
I am trying to simulate a post par simulation model of a design
which contains block RAMs. The source code is simulated using the
simulation block RAM model. And the internal memory is accessed using
'.' operator. This suceessfully simulated. But when i tried to imulte
the post par model an error occured. I have used the X_ library files
for simulation.
Initially i simulted and only accessed the output signals. This
version simulated successfully. But when i tried to access the internal
memory using . operator. At the time of loading the design an error
occured. It reported no load error for a mux which is not part of the
RAM. Found no reation between the error reported mux and the RAM. Why
this condition. I just tried to access the RAM in the simulation. What
could be the problem.
regards
Sumesh
Article: 103448
On Thu, 01 Jun 2006 19:23:11 -0700, be.geek wrote:
>> > Not sure if this is the right forum ... please point me if otherwise.
>> >
>> > I am a hobbyist and making my first foray into building custom
>> > hardware. I am interested in building my own VoIP device say using a
>> > Broadcom chip
This is the wrong group for this discussion. But I'm not sure which is
the right group--anyone? comp.arch.embedded perhaps.
~Dave~
Article: 103449On 2 Jun 2006 00:27:13 -0700, "vssumesh" <vssumesh_asic@yahoo.com> wrote: >Hello all, > I am trying to simulate a post par simulation model of a design >which contains block RAMs. The source code is simulated using the >simulation block RAM model. And the internal memory is accessed using >'.' operator. This suceessfully simulated. But when i tried to imulte >the post par model an error occured. I have used the X_ library files >for simulation. > Initially i simulted and only accessed the output signals. This >version simulated successfully. But when i tried to access the internal >memory using . operator. At the time of loading the design an error >occured. It reported no load error for a mux which is not part of the >RAM. Found no reation between the error reported mux and the RAM. Why >this condition. I just tried to access the RAM in the simulation. What >could be the problem. >regards >Sumesh accessing the internal memory with '.' (verilog's hierarchical access operator i am assuming) will not work after p&r. you have to use the memory as a memory ie give an address at its ports and get the data from the data ports. as you say "block ram model" is just a model.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z