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Hi guys!!! am working on a VIRETX-II FPGA and i am downloading the bit file by using the RBT File. i am now trying to decode a RBT file, i am so confused abt how the data are stored in those frames. i am not sure how the address of each frame and the column are written in the RBT. Any help will be appreciated. thanks in advance.Article: 105051
Hi Jonathan, Could you please give the paper address so that I am able to have a look at the algorithm? Thank you. WengArticle: 105052
http://direct.xilinx.com/bvdocs/appnotes/xapp228.pdf ftp://ftp.xilinx.com/pub/applications/xapp/xapp228.zipArticle: 105053
superman321 schrieb: > Hi guys!!! > > am working on a VIRETX-II FPGA and i am downloading the bit file by using the RBT File. i am now trying to decode a RBT file, i am so confused abt how the data are stored in those frames. i am not sure how the address of each frame and the column are written in the RBT. > > Any help will be appreciated. > > thanks in advance. Hi Superman, you need need to read the documents from Xilinx. I did. All the information you need is there. It really is. AnttiArticle: 105054
Jim Wu wrote: > This will be flagged as an error in ADEPT. The tool is freely available > at > > http://home.comcast.net/~jimwu88/tools/adept/ Yes, actually I stumbled upon this issue only by accident because I read the ADEPT release notes today, not by reading the Xilinx documentation. Unfortunately it's too late now, I didn't know about ADEPT when I was doing the schematics. I'll probably have to solder 0402 100R-resistors directly to the balls. BTW: thanks for this great tool, really useful. I should've know about it a few months ago. cu, SeanArticle: 105055
On 12 Jul 2006 10:05:52 -0700, Weng Tianxiang <wtxwtx@gmail.com> wrote: >Could you please give the paper address so that I am able to have a >look at the algorithm? This is where I found it... http://www.nist.gov/dads/HTML/bitonicSort.html and it references the same Knuth book that I used to find out about Batcher sort. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 105056
Hi Jonathan, Thank you very much. WengArticle: 105057
"Sean Durkin" <smd@despammed.com> wrote in message news:4hkqn9F2pidU1@individual.net... > > Unfortunately it's too late now, I didn't know about ADEPT when I was > doing the schematics. I'll probably have to solder 0402 100R-resistors > directly to the balls. > > cu, > Sean Hi Sean, I wonder, have you tried simulating your design? You might find that it performs OK even with resistors that are wildly different from 100R. As I'm sure you know, it depends on speed, trace length blah, blah, blah, but if your design can already cope with the ~10pF Cpin of the FPGA, you've got a fair chance of getting away with it! Another idea: if you're AC coupling the signal near its source, you could attempt to bodge on some source termination. Brian Davis published some stuff a while back here on CAF which featured attenutators that might also be of interest. Surely, almost anything is better than soldering directly to your balls. Good luck, Syms.Article: 105058
As far I know not related. As to longevity I expect the boards you see on our website now will probably be available to buy still in 5 years time. OEM adoption and use of a number of these boards has virtually guaranteed small batches still being made in that timeframe. I don't expect they will be quite as popular by then having been replaced in the main by I dare say Virtex-5/6/7 and Spartan-4/5/6 replacements. Jan Hansen wrote: > Hello John ! Are you related to the famous "Red Adair" ? He put out an > oilwell fire here i Norway some 20 years ago or so. Anyway, I wish you luck > with the new dev. board, I only hope is has a better life ecpentancy than > the SP305, wich i purchased, only to realise that the board went out of > production after a few weeks, and no support from Xilinx... > > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in > message news:1152620387.58731.0@iris.uk.clara.net... > > Following our recent Swinyard1 (Virtex-4) release we are now looking at > the > > Swinyard2 module concept which will be based on a middle end Virtex-5 > > (initial XC5VLX50 and others) that will be supported by our Broaddown > series > > of main development boards. Bearing in mind this a small module what > > features would you like us to put on this module? > > > > and what did you all think of the general Swinyard concept? > > > > This is you chance to influence what we deliver to the marketplace so do > let > > us know. > > > > John Adair > > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > > Board. > > http://www.enterpoint.co.uk > > > >Article: 105059
Hi all, You don't need to add any library to the ISE project and you MUSTN'T include the vhdl file generated by coregen in you ISE project (is for simulation only is not synthetizable). Coregen generates edn file (eventually ngc file), that ise use during translate process. You must specify where are these files if you choose a special directory. Regards.Article: 105060
Alain wrote: > Hi all, > > You don't need to add any library to the ISE project and you MUSTN'T > include the vhdl file generated by coregen in you ISE project (is for > simulation only is not synthetizable). Coregen generates edn file > (eventually ngc file), that ise use during translate process. You must > specify where are these files if you choose a special directory. Umm... perhaps you need to reread the original post, and my response. He specifically asked about using xilinxcorelib files without a Coregen generated edn file. And notice that my comment says "...(but in general you should not be doing this).Article: 105061
Hi Antti, Thanx a lot for the reply, I got a lot of information from the xilinx webpage, though there still remains 1 ques, which i do not understand. after the FDRI is loaded with no. of the words that has to be written, the frames are being loaded with data right????...... like for eg: On a virtex - II xc2v40. 30004000 --write 0 word to frame data input reg.; type 1. 50002922 --type 2,data words,0x2922 = 10530(decimal) = (404 frames + 1)*(26 words per frame) then are 10530 line of bits....and here i do not understand how there data are arranged in frames..they do not match with description as said by xilinx. Am i rite or i am decoding something wrong?????? if possible through some lite on this plz. thanx 1 again.Article: 105062
All, Does anyone know if there is an easy way to reprogram xilinx xcf08 serial proms outside of tying the jtag lines to the chip and emulating the whole jtag protocol? Has anyone used jtag successfully to reprogram these proms from the FPGA that they load? Thanks, ClarkArticle: 105063
Superman321 schrieb: > Hi Antti, > > Thanx a lot for the reply, I got a lot of information from the xilinx webpage, though there still remains 1 ques, which i do not understand. > > after the FDRI is loaded with no. of the words that has to be written, the frames are being loaded with data right????...... > > like for eg: > > On a virtex - II xc2v40. 30004000 --write 0 word to frame data input reg.; type 1. 50002922 --type 2,data words,0x2922 = 10530(decimal) = (404 frames + 1)*(26 words per frame) > > then are 10530 line of bits....and here i do not understand how there data are arranged in frames..they do not match with description as said by xilinx. > > Am i rite or i am decoding something wrong?????? > > if possible through some lite on this plz. > > thanx 1 again. I could say the same thing I said before: read the docu. if multiply frames are loaded the the frame addr sub-fields autoincrement. The best thing is to generate a 'debug' bitstream' then each record contains each frame and you can see the frame addresses for each frame in sequence but, why do you need to understand that stuff ? AnttiArticle: 105064
Hey, thanx for the reply, i am using it for partial reconfiguration. if i send the partially decoded file, with comments would you be able to help me a little bit more, though i have read those docs, i am kinda confused. i understand that multiple frames or the whole FPGA is being loaded. Well thanx 1 again for all those reply.Article: 105065
Jim, Have you looked into the MPD file for your peripheral? I am guessing, but the relevant options are probably as follows: OPTION HDL = MIX OPTION STYLE = HDL OPTION RUN_NGCBUILD = TRUE /Mikhail <jhouse@btmd.com> wrote in message news:1152719230.706099.6480@i42g2000cwa.googlegroups.com... > Hello - > > I am trying to write a custom peripheral using Verilog and version 8.1 > of the Xilinx tool kits (ISE and XPS). It is my understanding that > only the user_logic component of the peripheral can be developed in > Verilog, not sure if that is correct or not. Anyway, I used the XPS > create custom peripheral tool to create the skeleton of the peripheral. > I was careful to select the option to generate the user_logic stub in > Verilog rather than VHDL. At which point I received a dialog box > warning that the Verilog stub will be limited capabilities, I went > ahead with the Verilog stub. Then, using the ISE, I added the > required ports etc to the top level VHDL code and added my Verilog code > to the user_logic component. > > Once I confirmed all of the syntax was correct, I went back to XPS and > attempted to import the existing peripheral back into the project. I > selected the standard options. I also selectd the 'MIXED' option > for the question asking which HDL languages were used to implement the > peripheral. > > I also realized that for some reason the create custom peripherial > wizard did not seem to include my user_logic module in the PAO file. > So I manually edited the file and added the following line: > > lib opb_DVIReceiver_v1_00_a user_logic Verilog > > I was a bit surprised that I had to do this, because in the past, > I've created customer peripherals in VHDL and found that the > user_logic entry was automatically placed into the PAO file. Anyway, I > completed the import custom peripheral wizard and then added the IP to > my XPS project. I specified the addresses, and tied in the required > ports etc. All SEEMED well. However when I tried to generate the > bitstream, I received the following error: > > ERROR:NgdBuild:604 - logical block > 'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type > 'user_logic' > could not be resolved. A pin name misspelling can cause this, a > missing edif > or ngc file, or the misspelling of a type name. Symbol 'user_logic' > is not > supported in target 'virtex2p'. > > I have searched the net for information regarding this error message > and found several mentions of it, however none of which seemed to help. > > There MUST be some information somewhere that explains how to import > custome peripherals that make use of a user_logic component written in > Verilog, but I have yet to be able to find anything. I would GREATLY > appreciate it if someone out there could point me in the right > direction. > > Thanks in advance, > > Jim >Article: 105066
Symon wrote: > Hi Sean, > I wonder, have you tried simulating your design? You might find that it > performs OK even with resistors that are wildly different from 100R. As I'm > sure you know, it depends on speed, trace length blah, blah, blah, but if > your design can already cope with the ~10pF Cpin of the FPGA, you've got a > fair chance of getting away with it! Well, I did the same thing in a Virtex-II Pro, and it seems to be the same there (i.e. you're not supposed to use the differential termination when VCCO=3.3V), even though it's not that explicitely stated in the documentation. On that board it works perfectly, even though the termination must be off there as well. Back then I did measurements with a scope (at the balls) and didn't notice any obvious reflections or weird behaviour because of impedance mismatch. On some IOs I had external resistors and did comparisions between external and internal termination, didn't make much of a difference. The only thing different now is the FPGA. So, it might work there as well. > Another idea: if you're AC coupling the signal near its source, you could > attempt to bodge on some source termination. Brian Davis published some > stuff a while back here on CAF which featured attenutators that might also > be of interest. Yes, I read that thread, very interesting, and did some simulations with HyperLynx afterwards and concluded that I should be able to get away without attenuators and AC-coupling, but always under the assumption that I have decent 100R-termination inside the FPGA. The effect that the resistance varies when you have a different VCCO is not included in the simulation models, so what I simulated is not the "real world case". I'll do some more sims with different resistor values to see how that really affects it. > Surely, almost anything is better than soldering directly to your balls. Yes, especially since I'm not exactly RoHS-compliant. :) But seriously: There will be a small redesign of that board for other reasons anyway, so should the need arise I can add pads for the resistors then. cu, SeanArticle: 105067
>The VHDL file is autogenerated, and I feel that editing it with >specifics about the precise target board is a hack. To me this should >reside in a separate file or be programmable via the GUI. If it's auto-generated, it can be auto-hacked. Just write a script in your favorite language to do whatever needs doing and toss that into your Makefile. (That's not to discourage easier solutions. I'm just trying to say that you shouldn't avoid hacking the "source" code because you don't think of it as source code. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 105068
Hi Brannon, As NIST website quoted, bitonic sorting takes O((log n)2/2) stages (or steps) with n/2 comparators at each stage. Can you release your design running frequency for 64*64 bitonic sorting and what type of Xilinx chip or larger is to be used? Thank you. WengArticle: 105069
Hi guys, I'm trying to do post place and route simulation and generate vcd file to estimate the power with XPower. I tried behavioral simulation and the system was working fine. However as for PPP simulation at the very first in ISE it generated "system_stub_timesim.vhd" and some other files in "netgen" directory in my design. However in the .vhd file the value of all my BRAMs were zero. I added "executable.elf" file to my project in ISE and it seems that there are something in the BRAMs. However I know no better way to populate my BRAMs with data. Anyway the major problem now is that when the modelsim is simulating the design, I'm trying to verify the simulation by monitoring ilmb_lmb_abus and ilmb_lmb_readdbus signals. As for behavioral simulation the flow matched with the assembly file of my software. However in PPP simulation the flow of address generation on ilmb, address bus is insane. It starts fetching from 20000000 instead of 00000000, as well between the rising edge and falling edge of the clock in the same cycle there are so many glitches on address bus which is strange. By the way the ilmb_lmb_abus is 29 bits, so I just assume that it can address the whole memory space needed by 29 bits. Anyone has an idea about the problems that I've faced? Thanks alot beforehand, Amir PS. By the way I'm using ISE 8.1.03i and EDK 8.1.01iArticle: 105070
Mikhail - Thanks for the suggestions, they seem to have worked. My question now is how was I supposed to know to add these options to the MPD file? I created the shell of the peripheral using the EDK Create Peripheral wizard, added a bit of Verilog code using the ISE and then re-imported the modified peripheral using import peripheral EDK wizard. All of that resulted in the following options being placed in the MPD file: ################################################################### ## ## Name : opb_DVIReceiver ## Desc : Microprocessor Peripheral Description ## : Automatically generated by PsfUtility ## ################################################################### BEGIN opb_DVIReceiver ## Peripheral Options OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION HDL = MIXED OPTION CORE_STATE = ACTIVE OPTION IP_GROUP = MICROBLAZE:PPC:USER Which resulted in the error mentioned in my original post. Per your suggestion, I manually edited the MPD file and added two of the options you suggested (the option HDL MIXED was already there) resulting in the following: OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION HDL = MIXED OPTION CORE_STATE = ACTIVE OPTION IP_GROUP = MICROBLAZE:PPC:USER OPTION STYLE = HDL OPTION RUN_NGCBUILD = TRUE Which, as I said, seems to be working. I really feel that Xilinx needs to document all of the little tricks that have to be done in order to use a Verilog based custom peripheral. Thanks for the help, Jim MM wrote: > Jim, > > Have you looked into the MPD file for your peripheral? I am guessing, but > the relevant options are probably as follows: > > OPTION HDL = MIX > OPTION STYLE = HDL > OPTION RUN_NGCBUILD = TRUE > > /Mikhail > > > <jhouse@btmd.com> wrote in message > news:1152719230.706099.6480@i42g2000cwa.googlegroups.com... > > Hello - > > > > I am trying to write a custom peripheral using Verilog and version 8.1 > > of the Xilinx tool kits (ISE and XPS). It is my understanding that > > only the user_logic component of the peripheral can be developed in > > Verilog, not sure if that is correct or not. Anyway, I used the XPS > > create custom peripheral tool to create the skeleton of the peripheral. > > I was careful to select the option to generate the user_logic stub in > > Verilog rather than VHDL. At which point I received a dialog box > > warning that the Verilog stub will be limited capabilities, I went > > ahead with the Verilog stub. Then, using the ISE, I added the > > required ports etc to the top level VHDL code and added my Verilog code > > to the user_logic component. > > > > Once I confirmed all of the syntax was correct, I went back to XPS and > > attempted to import the existing peripheral back into the project. I > > selected the standard options. I also selectd the 'MIXED' option > > for the question asking which HDL languages were used to implement the > > peripheral. > > > > I also realized that for some reason the create custom peripherial > > wizard did not seem to include my user_logic module in the PAO file. > > So I manually edited the file and added the following line: > > > > lib opb_DVIReceiver_v1_00_a user_logic Verilog > > > > I was a bit surprised that I had to do this, because in the past, > > I've created customer peripherals in VHDL and found that the > > user_logic entry was automatically placed into the PAO file. Anyway, I > > completed the import custom peripheral wizard and then added the IP to > > my XPS project. I specified the addresses, and tied in the required > > ports etc. All SEEMED well. However when I tried to generate the > > bitstream, I received the following error: > > > > ERROR:NgdBuild:604 - logical block > > 'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type > > 'user_logic' > > could not be resolved. A pin name misspelling can cause this, a > > missing edif > > or ngc file, or the misspelling of a type name. Symbol 'user_logic' > > is not > > supported in target 'virtex2p'. > > > > I have searched the net for information regarding this error message > > and found several mentions of it, however none of which seemed to help. > > > > There MUST be some information somewhere that explains how to import > > custome peripherals that make use of a user_logic component written in > > Verilog, but I have yet to be able to find anything. I would GREATLY > > appreciate it if someone out there could point me in the right > > direction. > > > > Thanks in advance, > > > > Jim > >Article: 105071
Anonymous schrieb: > All, > > Does anyone know if there is an easy way to reprogram xilinx xcf08 serial > proms outside of tying the jtag lines to the chip and emulating the whole > jtag protocol? Has anyone used jtag successfully to reprogram these proms > from the FPGA that they load? > > Thanks, > Clark 1) XCFxx is ONLY programmble using JTAG 2) Yes I have success programming XCF over PCI-JTAG bridge in the same FPGA using full custom programming software that programs the XCF08P from .BIT file Antti http://antti-brain.comArticle: 105072
Duane Clark schrieb: > Alain wrote: >> Hi all, >> >> You don't need to add any library to the ISE project and you MUSTN'T >> include the vhdl file generated by coregen in you ISE project (is for >> simulation only is not synthetizable). Coregen generates edn file >> (eventually ngc file), that ise use during translate process. You must >> specify where are these files if you choose a special directory. > > Umm... perhaps you need to reread the original post, and my response. He > specifically asked about using xilinxcorelib files without a Coregen > generated edn file. And notice that my comment says "...(but in general > you should not be doing this). > Umm.. perhaps you need to reread the original post. Vassili is talking about synthesis. Xilinxcorelib is only for simulation purposes. He just did it wrong. Alain's answer is mostly correct! (The netlist format is edif, found in the *edn file) You correctly explained the flow for adding synthesis libraries to ISE projects. But never ever do that with Xilinxcorelib. To Vassili: In the ISE 7In-Depth Tutorial vou find a chapter about using Coregen (p. 33). The example there uses the binary counter as well. The generated VHDL and verilog files are wrappers for the corelib instance and must only be added to a simulation project. In ISE 8.1 you can switch the sources window to different flows. In the synthesis flow view testbenches will not be displayed. In the simulation flows xco files will not be displayed, but the vhdl og verilog file of the core appear. For VHDL: a *.vho is generated which gives you an instantiation template for the generated core. The informations in this file have to be copyed correctly to the source where you want to instantiate the core (e.g. your toplevel design). If you have generated the core in a separate folder you either have to copy the files to your ISE project folder or set the constraint for the macro paths correctly (for both, synthesis and implementation tools). After generating the core you find a *_flist.txt file in your project directory like this for the example given in the ise7 tutorial: # Output products list for <tenths> tenths.edn tenths.vho tenths.vhd tenths.asy tenths.xco tenths.xcp tenths.sym tenths.edn is the netlist file that will be used during implementation. tenths.vho contains the imstantiation template. tenths .vhd is the wrapper for simulation. tenths.asy and tenth.sym are symbols for schematic flows tenths.xco is the core information used by the project navigator. tenths.xcp ??? don't know, have to read the documentation. About these license files: Vivek probably used a more complex core for which a license has to be bought separately. A lot of the simpler ones are for free and need no extra license. Anyway, Vassili, better chage to ise8.1. The coregen is there integrated in the flow and works just fine. With *.xco files and everything. have a nice synthesis EilertArticle: 105073
Thankyou all for nice comments and pointer. Each writer (processor), accessed its own address space, point-to-point connection might be better. I need another comment and pointer. Problem now I have is "how to connect each distributed memory to I/O". Since the input/output data is "streamed" (or serial) in the application I consider, I do not have idea how to "transfer" block of input streamed data to processor-private memory and vice versa. I 've thought of these things, but not yet there --:. ThankyouArticle: 105074
Thankyou all for nice comments and pointer. Each writer (processor), accesses its own address space, so point-to-point (p2p) connection might be better. I need another comment and pointer. Problem now I have is "how to connect each distributed memory to I/O". Since the input/output data is "streamed" (or serial) in the application I consider, that is, Input data stream ----> multiple processors and p2p-connected memories ---> Output data stream I do not have idea how each memory takes data from and to I/O. I 've thought of these things, but not yet there --:. Thankyou for your comment again.
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