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Hi Andy, "Ok - you're asking about decoding, not encoding." No, It is encoding! WengArticle: 105926
Thank you Symon & Jonathan. Your information are very useful.Article: 105927
John_H wrote: > Greetings, > > I want to parameterize a module in a way that makes some inputs used or not > used. If I have the input defined but don't use it in the module > instantiation, I end up with a synthesis warning about tying an unused input > to 0. If I use a generate, I'll be trying to add a generate item of the > form "input clk," where the comma looks like it won't be a legal generate > item. > > Anyone have a clean way to remove the input from the module definition list > without a `define? > > I can imagine specifying a Verilog-1995 style I/O list where only the names > are listed initially then outside the module port definition use an if/else > to define my value as input or output; if I don't use the output, I get no > warning and if I hook something up to the signal I want unused I should have > a synthesis warning for too many drivers. But I'd like to keep my > Verilog-2001 style of I/O definitions embedded in the portdefs. > > - John_H > > How often I have wished for this feature, and how often I have wondered why the IEEE committee didn't add it to the spec. But there is no way to make the port list varible. You can only vary the sizes of the ports. The only workaround is to use `defines. -KevinArticle: 105928
Hi guys, I have a problem with how EDK utilizes BRAMs for data and instruction LMB memories. I have 64KB instruction and data space and I have 32 BRAMs on my chip. So basically I should have 32 * 18KB memory on my board. However when EDK wants to map the data and instruction memories on the BRAMs it really under-utilizes the BRAMs. It assigns 2KB (every bit of the word) of instruction and data on the either port of each BRAM. I've tried with different memory sizes and still it uses just 2KB on each port for data and instruction. I should be able to virually use 512KB of on chip memory but practically I can't use more than 128KB of my on-chip memory space. Do you know any way to change the way that EDK assigns words to the BRAMs? Thanks beforehand,Article: 105929
We could drop leo but have a lot of process docs. defined with this tool. We have been considering a swicth to XST so we can stop Leo maintenance. For now it may be better to edit the script and run Leo standalone although it's nice to use PN to generate the script - for this one needs leonardo as part of the flow. Script edits get overwritten by PN flow. I don't understand why stuff that used to work now doesn't. In 7.1 all one needed was .edf and .xco files in the project to compile with coregen models, now 8.2 want's the .vhd files for these too?Article: 105930
Goran Bilski, The values are reversed. If you reverse the addresses then you get the correct values. MicroBlaze uses 0:31 but I think that you are watching the values in the other order 31:0 G=F6ran -----Original Message----- From: Xesium [mailto:amirhossein.gholamipour@gmail.com] Sent: Wednesday, July 19, 2006 15:47 To: Goran Bilski Subject: Re: Post Place and Route simulation for Microblaze... Dear Goran, I double checked everything again about Post Translate and Post Place and Route simulation. If the contents of my BRAMs are all 0 I have a sequence of fetched addresses in Post Translate which is exactly the same as Post Place and Route (when the address gets stable on address bus) if the contents of my BRAMs are 0 in system_stub_timesim.vhd. On the other hand if my BRAMs are populated with data and opcodes I have the same sequence for Post Translate and Post Place and Route however the sequence is different from the case that the contents are 0. After all the both sequence of addresses are insane and not reasonable. This is the sequence of the fetched addresses when the content of my BRAMs are 0: 00000000 -> 20000000 -> 10000000 -> 30000000 -> 08000000 -> 28000000 -> 18000000 -> 38000000 -> 04000000 ... and this is the sequence when my BRAMs are populated with data: 00000000 -> 20000000 -> 10000000 -> 0A000000 -> 2A000000 -> 1A000000 -> 3A000000 -> 06000000 ... considering my address space which is 00000000 - 0000FFFF these addresses are not reasonable. Looking forward to your advice, Thanks alot, Amir G=F6ran Bilski wrote: > Hi, > > There is too little information for me to give you an answer of your > problem. > > Can you explain a little what you mean with "irregular patterns"? > Are you running simulation with the timing information file (.sdf) ? > > G=F6ran Bilski > > Xesium wrote: > > Hi guys, > > I posted my problem a few days ago but I think I didn't make my points > > clear so I've decided to post it again. > > I have a very simple Microblaze based system which just has the > > processor and LMB BRAMs for instruction and data. I'm running my code > > on this system and I basically want to measure the power consumption of > > the system. I've generated a .vcd file by behavioral simulation of my > > design and estimated the power with that. But it seems that it is far > > unrealistic. As well by behavioral simulation I could verify my system > > behavior. I was monitoring my ilmb_lmb_abus which was the address bus > > of the instruction port of the microblaze and on the other hand I had > > the assembly code of my software so I could see what's going on in the > > system. However now to get a better estimation of power consumption of > > my system I want to do Post Place and Route simulation and generate the > > .vcd by doing so. I've made sure that there is data in BRAMs in > > system_stub_timesim.vhd file generated by ISE. But when modelsim > > simulates my design I observe irregular fetches on my address bus. Even > > the contents of the addresses which should be the opcodes of the > > instructions doesn't match with the assembly file that I have. I'm also > > monitoring Program Counter value but that one too has irregular > > patterns in addresses though different from address bus. I'm trying to > > verify my simulation to make sure that the .vcd file that is generated > > is what it should be however I'm stuck here because I don't know what > > the problem is. > > I am wondering if any of you have any idea what is going on and what > > can I do about it, > > > > I really appreciate your response and thanks alot beforehand, > > > > Amir > > > > PS. By the way I'm using ISE 8.1.03i and EDK 8.1.01i and Modelsim SE 6.0 > >Article: 105931
Kevin Neilson wrote: > John_H wrote: >> Greetings, >> >> I want to parameterize a module in a way that makes some inputs used >> or not used. If I have the input defined but don't use it in the >> module instantiation, I end up with a synthesis warning about tying an >> unused input to 0. If I use a generate, I'll be trying to add a >> generate item of the form "input clk," where the comma looks like it >> won't be a legal generate item. >> >> Anyone have a clean way to remove the input from the module definition >> list without a `define? >> >> I can imagine specifying a Verilog-1995 style I/O list where only the >> names are listed initially then outside the module port definition use >> an if/else to define my value as input or output; if I don't use the >> output, I get no warning and if I hook something up to the signal I >> want unused I should have a synthesis warning for too many drivers. >> But I'd like to keep my Verilog-2001 style of I/O definitions embedded >> in the portdefs. >> >> - John_H >> > How often I have wished for this feature, and how often I have wondered > why the IEEE committee didn't add it to the spec. But there is no way > to make the port list varible. You can only vary the sizes of the > ports. The only workaround is to use `defines. > -Kevin A half work around, at least for SynplifyPro: declare the ports as inout. There aren't warnings for unconnected inputs (yay!) but there aren't warnings for incorrect inputs that are only driven by the module (boo!).Article: 105932
Xesium wrote: > Hi guys, > I have a problem with how EDK utilizes BRAMs for data and instruction > LMB memories. I have 64KB instruction and data space and I have 32 > BRAMs on my chip. So basically I should have 32 * 18KB memory on my > board. However when EDK wants to map the data and instruction memories > on the BRAMs it really under-utilizes the BRAMs. It assigns 2KB (every > bit of the word) of instruction and data on the either port of each > BRAM. I've tried with different memory sizes and still it uses just 2KB > on each port for data and instruction. I should be able to virually use > 512KB of on chip memory but practically I can't use more than 128KB of > my on-chip memory space. Do you know any way to change the way that EDK > assigns words to the BRAMs? > > Thanks beforehand, Do you have bytes or do you have bits? The BlockRAMs are 18 kbit (double for Virtex-5, 1/4 for Virtex/-E, Spartan-2/E).Article: 105933
Hi Antti
> > Unfortunatelly I am not satisfied with couple of IO pins for BSCAN. I
> > need 16 bit pipe transfers. I will just connect my Avnet S3E board
>
> The BSCAN is pretty much documented and fun to use.
Do you know of a way of accessing the Xilinx platform USB cable
from an user application ?
The only way I know is the xtclsh stuff but I found it pretty slow ...
I designed a small module connected to a BSCAN where basically
I just need to continuously read the User DR and it takes ages to read
a few megabytes ...
And I know it could be faster because if I could drive the jtag pins
manually at 24 Mhz, it would just take a few seconds to do such a
transfer ...
Sylvain
>
> > (with FX2 on it) to Xilinx S3E starter kit and use the cripled S3E100
> > (on Avnet board) as a route-through.
> > I wonder if Hydra modules come up with a decent driver (PC and EDK
> > module) for on-board USB2.0 (with a source code of course).
> >
> > Thanks,
> >
> > Guru
>
> hydraxc modules do come with some USB code of course
> what is currently available is
>
> 1) working standalone application demo for USB Mass Storage class
> device. eg you plug the USB cable to PC and then the miniSD is visible
> has removable disk from the PC host.
>
> 2) minimal HOST standalone demo, enumerates internal HUB, set hib port
> on, and reads Device descriptor from external device
>
> 3) from Philips is optainable
>
> http://www.semiconductors.philips.com/products/connectivity/usb/products/download/
>
> source code for the uclinux host driver, this is however not fully
> suitable for microblaze-uclinux :(
>
> well from this driver here is some terminal log from hydraxc-uclinux:
>
> # mount -t usbfs none /proc/bus/usb
> # cd proc
> # cd bus
> # cd usb
> # cat devices
> T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 1
> B: Alloc= 0/800 us ( 0%), #Int= 0, #Iso= 0
> D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=01 MxPS= 8 #Cfgs= 1
> P: Vendor=0000 ProdID=0000 Rev= 2.04
> S: Product=USB PHCI Root Hub
> S: SerialNumber=802f7c00
> C:* #Ifs= 1 Cfg#= 1 Atr=40 MxPwr= 0mA
> I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub
> E: Ad=81(I) Atr=03(Int.) MxPS= 2 Ivl=256ms
>
> we do not have this driver fully working (but hopefully will have
> soon).
>
> As of open-source linux driver we are looking for solution (the Philips
> driver is not available as open-source unfortunatly)
>
> As of hardware side the ISP1761 can be connected to EDK system using
> OPB_EMC and is visible as memory mapped peripheral. The host drivers,
> well it depends what class you implement for CDC or mass storage there
> are no PC drivers needed
>
> Antti
Article: 105934On 2 Aug 2006 12:21:47 -0700, burn.sir@gmail.com wrote: >hello everybody, > > >are there any _simple_ ways of generating a sine waveform, maybe from a >reference pulse/saw/triangle signal? > >(Thanks to Ray :) I know that there are more complicated ways of doing >this, but for now i am interested in the simplest possible way for >getting something that looks like a sine. > >actually, i am also interested on algorithms for generating any type of >periodic signals (both low and high on harmonics) that works well in >FPGAs. Jitter and variations are ok (in fact, they are welcome up to >some degree). > > >(for the record, it will be used for sound synthesis) > > >regards, -Burns Try a google search for "Magic Sinewaves"Article: 105935
John, Thanks for your advice and for sharing your experience. We had a bad experience with the development board (in other respects) so I didn't want to "borrow" any parts of their design without checking other people's experiences. Thanks Peter John Adair wrote: > We use the ICS8442 and it has a very good jitter specification which is good > for applications like RocketIO. When you are looking at this kind of > specification there are not many devices as good as the ICS8442 especially > if you want to use LVDS. The device is fairly layout sensative so do take > care in that area of it but that's not unusual in this type of device. > > "Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> wrote in > message news:eaq928$5j8$1@dux.dundee.ac.uk... >> <snip> >> a ICS8442 low jitter LVDS frequency synthesizer. Does anyone have >> any suggestions or advice? Can/Should I use the same device? Is this a >> wild goose chase?Article: 105936
Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > Hi Antti > > > > Unfortunatelly I am not satisfied with couple of IO pins for BSCAN. I > > > need 16 bit pipe transfers. I will just connect my Avnet S3E board > > > > The BSCAN is pretty much documented and fun to use. > > Do you know of a way of accessing the Xilinx platform USB cable > from an user application ? > > The only way I know is the xtclsh stuff but I found it pretty slow ... > I designed a small module connected to a BSCAN where basically > I just need to continuously read the User DR and it takes ages to read > a few megabytes ... > > And I know it could be faster because if I could drive the jtag pins > manually at 24 Mhz, it would just take a few seconds to do such a > transfer ... > > the easiest way is possible hacking the impact-server tcp protocol, its rather simple. just start impact server (with debug logging), then impact that is connected to it and look in etherreal and debug log this way you can talk to any xilinx cable be it USB or not. I have partial protocol infos available, but not full :( should be doable in a few days work. sure the protocol may change every impact release :( or potentially you could also use the xilinx jtag dll's but they are also allmost not documented :( hm, the best solution would be to write open-source replacement firmware for the platform USB cable! AnttiArticle: 105937
What did you mean "it doesn't work"? I do not see a problem in your options. -Felix Nitesh wrote: > I have an IP core made up of verilog files as well as vhdl files. How > do I set my mpd file for the bitstream generation in XPS? > I tried putting > OPTION HDL =MIXED > OPTION STLYE = HDL > but it doesnt work . > Anyone done this before. > Thanks, > NiteshArticle: 105938
Hi Eric, Thank you for your response. I have read an article about median filter implementation: "New bit-level algorithm for general purpose median filtering" by Khaled Benkrid and Danny Crookes. Its FPGA speed is 27frame/s. Let your students try to increase its implementation speed. If they can, they know how to beef up performance. Thank you. WengArticle: 105939
Weng Tianxiang wrote: > Your method is interesting, but is far from what I am looking for. > It is too slow. > I found that almost all Huffman encoding applications are static as in > FAX, electronic books, ZIP files, JPEG, MPEG and so on. You are wrong there. ZIP files and most EBooks use some variant of LZ encoding using a suffix tree (which might be feasible in hardware), followed by Huffman coding - static *or* dynamic - on the resultant symbols. Zip in particular uses the deflate algorithm, which can emit either static or dynamically-generated Huffman data on each block. But AFAIK, the Huffman table is *not* updated with each symbol. There was a kid on sci.crypt a while back banging on about a per-symbol dynamic Huffman technique he'd invented, perhaps look there. JPEG and MPEG use a DCT (and optionally in MPEG, motion compensation) before applying further compression. The DCT is *not* huffman by another name, its a discrete cosine transform. Also, look for information on Suffix Trees (used in Lempel-Zif encoding), and you might find it can be done in a limited way in hardware. The tree is built incrementally, and looks kinda like Logan's trie, except that the first symbol of a sequence is at the leaf, with the last symbol at the root. Kinda... In general, though Huffman coding was thought to be "optimal" two decades ago, newer techniques have been shown to be better. For example, arithmetic coding (needs two passes over the data though), and the Burrows-Wheeler transform (used in bzip). There should be enough terms for you to go googling and perhaps find a more suitable algorithm than Huffman. Don't forget - compression is simply the process of removing whatever is predictable from a data stream. The better you understand your data, the better an algorithm can predict it, and the better your compressor can be. Good luck! Clifford Heath.Article: 105940
My simulator constantly give me this warning, the reason being that I am unable to predictable the word length of my test vectors, so I defined a 10K array, which is larger than any of the test vector files. I need to remove this warning so as to make my testing environment look better. How can I suppress this warning ALONE? I have other warnings which I would like not to be suppressed by global NCVerilog settings. $readmem warning: words in file "./tv/MSG_INPUT_0021_0200_p315.DAT" less than that given by address bounds Thanks for your idea.Article: 105941
john wrote: > Hello, > National instruments has introduced new module in their labview 8 for > programming the xilinx FPGA chips. It converts the labview programs > into VHDL . It can borrow image processing libraries from the labview > too. I was wondering that if somebody has used this module form labview > > can give me details about it. > Thanks > Regards > John I was at the Embedded Systems Conference in SanJose this year and I sat in on a 2 hour lecture on this. I initially thought the class was some kind of joke, but yes, they were actually using LabView to generate code for an FPGA. After sitting and watching a guy make a shift register I left the class with my inital impression of the class, its a joke. I can look at a schematic and tell a circuit is a shift register, I can look at VHDL/Verilog code and see a shift register, but that mess of LabView crud they hade on the screen looked NOTHING like a shift register. I know this is pretty much version 1 of their FPGA software, but it will take much more work before it is ever usefull as a design tool. I can't see how this will ever catch on for LabView...Article: 105942
hi In EDK, I am having problem with managing user functions in user IP component. The error message is that ------------------------------------------------------------------------------------------- XST synthesis ERROR:Xst:813 - C:/.../pcores/plb2_UserDesign/hdl/vhdl/Design/PE.vhd line 81: Body of function CON_INT not found. ERROR:MDT - HDL synthesis failed! ------------------------------------------------------------------------------------------- One simple user function, "CON_INT" is used ONLY in one component(PE.vhd) which is a sub-module of user peripheral pcore. It seems that I need to compile the user package and put the compiled user library in IP-wrapper. I need some comment from experienced people. User component "PE.vhd" looks like ---------------------------------------------------------------------------------------------- ---- "PE.vhd" library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.packet.all; -- function declare and function body entity PE is .... --------------------------------------------------------------------------------------------- And "packet.vhd" looks like --------------------------------------------------------------------------------------------- ------ "packet.vhd" library IEEE; use IEEE.std_logic_1164.all; package packet is .... subtype reg4 is std_logic_vector(3 downto 0); function CON_INT( vec: reg4 ) return integer; end packet; package body packet is function CON_INT( vec: reg4 ) return integer; is variable bin: integer range 0 to 255; begin ... return bin; end CON_INT; end packet; -----------------------------------------------------------------------Article: 105943
Hi all, I am using the FFT coregen block with pipelined streaming option in my design implementation on a Virtex-4 FPGA. I am having a lot of issues with the implementation and have shortlisted them below: 1. First of all, the HDL generated file for FFT core 3.2 is not synthesizable. Is there any way to synthesize this block. I am using Xilinx ISE 7.1.4i and latest IP update. 2. I went back and instantiated the FFT core 3.1 and tried to use that in my design. My PNR report states that the FFT logic is trimmed off. I am not able to understand the problem. 3. Also, how do I compile the wrapper file?? Please let me know if you have come across this problem. Thanks, VivekArticle: 105944
Also the synthesis report shows the following: Reading core <fft_testv4_r22_flow_ctrl_1.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_2.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_3.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_4.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_5.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_6.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_7.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_8.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_9.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_10.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_11.ngc>. Reading core <fft_testv4_r22_cnt_ctrl_12.ngc>. Reading core <fft_testv4_cmpy_3_dsp48_13.ngc>. Reading core <fft_testv4_cmpy_3_dsp48_14.ngc>. Reading core <fft_testv4_cmpy_3_dsp48_15.ngc>. Reading core <fft_testv4_cmpy_3_dsp48_16.ngc>. Reading core <fft_testv4_cmpy_3_dsp48_17.ngc>. Reading module "fifo_memory.ngo" ( "fifo_memory.ngo" unchanged since last run )... Reading core <fifo_memory_fifo_generator_v2_0_as_1.ngc>. Loading core <upload_bus_mux> for timing and area information for instance <upload_bus_mux>. Loading core <fft_testv4_r22_flow_ctrl_1> for timing and area information for instance <BU46>. I think this implies that my core is only being read and not loaded. If it's loaded for timing and area information, my core would work. Thanks in advance for your valuable suggestions. Vivek Vivek Menon wrote: > Hi all, > I am using the FFT coregen block with pipelined streaming option in my > design implementation on a Virtex-4 FPGA. I am having a lot of issues > with the implementation and have shortlisted them below: > 1. First of all, the HDL generated file for FFT core 3.2 is not > synthesizable. Is there any way to synthesize this block. I am using > Xilinx ISE 7.1.4i and latest IP update. > 2. I went back and instantiated the FFT core 3.1 and tried to use that > in my design. My PNR report states that the FFT logic is trimmed off. I > am not able to understand the problem. > 3. Also, how do I compile the wrapper file?? > Please let me know if you have come across this problem. > Thanks, > VivekArticle: 105945
On 3 Aug 2006 05:50:00 -0700, "Pasacco" <pasacco@gmail.com> wrote: >hi > >In EDK, I am having problem with managing user functions in user IP >component. The error message is that >------------------------------------------------------------------------------------------- >XST synthesis >ERROR:Xst:813 - C:/.../pcores/plb2_UserDesign/hdl/vhdl/Design/PE.vhd >line 81: Body of function CON_INT not found. >ERROR:MDT - HDL synthesis failed! >------------------------------------------------------------------------------------------- > >One simple user function, "CON_INT" is used ONLY in one >component(PE.vhd) which is a sub-module of user peripheral pcore. > >It seems that I need to compile the user package and put the compiled >user library in IP-wrapper. <....> You must include the file that contains that function in the hdl sources list when using the import peripheral wizard. ZaraArticle: 105946
> 1. First of all, the HDL generated file for FFT core 3.2 is not > synthesizable. It's not supposed to be. You need to use the netlist that coregen produces. /MikhailArticle: 105947
Can you please elaborate? MM wrote: > > 1. First of all, the HDL generated file for FFT core 3.2 is not > > synthesizable. > > It's not supposed to be. You need to use the netlist that coregen produces. > > > /MikhailArticle: 105948
http://xilant.com/content/view/45/2/ soon... AnttiArticle: 105949
http://inisyn.org/src/xup/ its already done! I was kind of hoping someone does it, and voila, done... and as a good smile bonus, I really like that webpage, the author can really name thing with proper names. to understand that just place the cursor over "proprietary nightmare" - and you see the hyperlink - www.jungo.com !! :) nice way to say it: "The windriver stuff really is one major thing that f*** ups Xilinx Cable IV and USB Cable support". Antti http://antti-brain.com
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