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Messages from 10625

Article: 10625
Subject: Re: minimalist FPGA - C API for FPGA
From: Steve Casselman <sc@vcc.com>
Date: Sat, 06 Jun 1998 13:53:28 -0700
Links: << >>  << T >>  << A >>
Tim Tyler wrote:

> Lastly, another stab at cheap cards:
>
> http://www.xess.com/FPGA/ are as cheap as I have seen for a basic
> small
> experimental unit.  These aren't PCI, but run over the printer port
> (they
> have sockets for breadboarding them that would be out of place if the
> cards
> were orthodox PCI).  I can't comment on the cards as I've not used
> them.
> --
> __________
>  |im |yler The Mandala Centre http://www.mandala.co.uk tt@cryogen.com

  With all due respect to xess the only chip today that makes sense
for EH is the 6200 no other device has the micro interface and
for sure no other system has the depth of C API of the 6200
development system.

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 10626
Subject: Re: Is there tiling software?
From: simon@VOID.actrix.gen.nz (Simon Peacock)
Date: 6 Jun 98 22:14:37 GMT
Links: << >>  << T >>  << A >>
In message <357e345e.92911649@news.demon.co.uk> - brian@shapes.demon.co.uk
(Brian Drummond)Sat, 06 Jun 1998 12:40:26 GMT writes:
:>
:>On Fri, 05 Jun 1998 11:10:43 -0600, "Prof. Vitit Kantabutra"
:><kantviti@isu.edu> wrote:
:>
:>>I'm designing a fairly large circuit, but only have a letter-sized
:>>printer, and want to be able to tile my printouts on several pages.  Is
:>>there software anywhere that does that?  
:>
:>A cheap A3 printer (color inkjet) would be a help (B-size to you
:>Americans) like the Canon 4650. I saw the obsolescent 4550 for about
:>$200 recently, it would do fine.
:>
:>- Brian

I've had good experiences with an Epson Color stylus pro xl+.. its got a flat
paper tray unlike the canon (whch hold the paper vertically).

Remember Just remove the VOID

--
StarLite Design                Phone mobile: +64 25 40 2963 
Simon Peacock                          Home: +64 4 388 8964
simon@VOID.actrix.gen.nz                Fax: +64 4 388 8964
Address: P.O. Box 15-143 Miramar, Wellington, NEW ZEALAND


Article: 10627
Subject: Re: Evolutionary FPGAs
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Sat, 06 Jun 1998 15:22:31 -0700
Links: << >>  << T >>  << A >>



Let me explain and also apologize if it's ALREADY generally known:

The XC6200-type devices are the only FPGAs that can be used for
evolutionary configuration, because their interconnect structure is such
that any metal line can be driven from only one source. Thus they can
tolerate "garbage configuration", since there is no possibility for
internal contention by two opposite signals driving the same
interconnect.
No other commercially available FPGA has this feature, they use software
(design-rule checkers ) instead, to eliminate most possibilities of
internal contention.

Peter Alfke, Xilinx applications
------------------------------------------------------------------------

Steve Casselman wrote:

> We have lots of customers working on evolvable
> hardware. Many people are interested in the method
> and the 6200 is the only device that allows one to
> do this.
>
> > On the June issue of Discover Magazine, the cover story reports of
> two
> >
> > computer scientists, Inman Harvey and Adrian Thompson, applying
> > evolution
> > to program a Xilinx XC6216ES.
> >
> > One of the things they did was evolved the FGPA to distinguish a
> 1KHz
> > input from a 10KHz input. This was done with using only 100 CLBs of
> > the
> > XC6216, and no clock input. After two weeks and 5000 generations,
> the
> > chip
> > evolved to work great --with one drawback, it's not robust. If
> > programmed
> > to different chips or if input/output pins were reassigned, it
> > wouldn't
> > work. Also, slightly temperature variations have big effects.
> >
> > Is there anybody that applied Thompson's method of programming a
> FPGA?
> >
> > More information can be found at http://www.discover.com
>
> --
> Steve Casselman, President
> Virtual Computer Corporation
> http://www.vcc.com

  




Article: 10628
Subject: Over 900 semiconductor links!
From: "A. Tillmann" <a.tillmann@t-online.de>
Date: Sat, 06 Jun 1998 19:35:31 -0700
Links: << >>  << T >>  << A >>
Please check out MY SEMICONDUCTOR LINKPAGE at

http://home.t-online.de/home/a.tillmann

where you can find links to semiconductor-related websites in the 
following categories:

Companies
     Wafer Manufacturers(17)
     Equipment Vendors(409)
     Used Equipment(9)
     IC Manufacturers(254)
     Software/ Process and Device Simulation(37)
     Service/ Photomask Manufacturers/ Others(66)
Universities/ Institutes(45)
Journals(14)
Organisations/ Directories/ Linkpages
     U.S.A.(27)
     Japan(11)
     Europe(7)
News(5) (New Category!)
Usenet Groups(15)
Search Engines (english)(27)
Search Engines (french, german)(6)
Jobs/ Recruitment(7)

If you miss a link to YOUR company or organization feel free to send me 
the according URL and the name of the category, where the link should 
appear. This linkpage will be updated on a regular basis (every 3-5 
weeks). If you want to get information about updates or changes of
the linkpage please join our mailing list: Enter your email address on 
top of the linkpage, then click the 'Join List' button.

I want to thank all the individuals, who send me missing URLs and 
encouraging comments.

Best regards

****************************************************************
Andreas Tillmann
E-Mail: a.tillmann@t-online.de
Web:    http://home.t-online.de/home/a.tillmann
****************************************************************
Article: 10629
Subject: Re: Is there tiling software?
From: murray@pa.dec.com (Hal Murray)
Date: 7 Jun 1998 04:36:41 GMT
Links: << >>  << T >>  << A >>
If you can get postscript output there are probably tiling
packages available.  At worst, you can get a postscript
hacker to help you write your own.

I'm thinking of some postscript code that you put on the
front of the output before you feed it to the printer.
Such as:
xxx>  cat tile.ps design.ps | lpr


-- 
These are my opinions, not necessarily my employers.
Article: 10630
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: Gary Helbig <ghelbig@slip.net>
Date: Sun, 07 Jun 1998 18:20:49 -0700
Links: << >>  << T >>  << A >>
Marcus Lankenau wrote:
> 
> z80@ds1.com (Peter) wrote:
> 
> >
> >Assuming you can write software at all, you don't need a code example.
> >Have a look at the slave serial mode in the Xilinx data book, and
> >implement that. It is trivial.
> >
> >>Hello all,
> >>    I am trying to program the xilinx fpga  in a serial slave mode with
> >>an 8051. Anyone knows where I can get an example of the 8051 codes that
> >>read the Xilinx configuration data from the 8051's eprom and program the
> >>Xilinx fpga ?
> >
> >
> >Peter.
> >
> >Return address is invalid to help stop junk mail.
> >E-mail replies to zX80@digiYserve.com but
> >remove the X and the Y.
> 
> Where is the adventage in using the 8051 for the configuration of the
> fpga instead of using an eeprom?
> 
> Marcus

I did a system once where (one of) two different interfaces could be
configured.

The 8051 would determine what was out there, and load the Xilinx
accordingly.

Gary.
Article: 10631
Subject: FPGA Conversion
From: Kalyan Gokhale <kgokhale@execpc.com>
Date: Sun, 07 Jun 1998 22:10:08 -0500
Links: << >>  << T >>  << A >>
What are the names of the companies doing FPGA to gate array converions?

Kalyan Gokhale
MagneTek Drives and Systems
kgokhale@magnetek.com

Article: 10632
Subject: ViewDraw Info
From: mstrzalka@my-dejanews.com
Date: Mon, 08 Jun 1998 03:36:38 GMT
Links: << >>  << T >>  << A >>
Is there a low-cost read-only viewer for ViewDraw files?

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10633
Subject: Atmel serial EEPROMs
From: Rick Filipkewicz <rick@algor.co.uk>
Date: Mon, 08 Jun 1998 11:13:04 +0100
Links: << >>  << T >>  << A >>
I'm using the 256KBit Atmel part to store config data for a Xilinx
XC4005XL part. To program it I've got a link that disconnects the EEPROM
from the FPGA and connects its pins via a 16 way header & ribbon cable
to an 8 bit PIO port on another board. The s/w puts it into I2C mode,
programs and verifies it. It then changes the EEPROM mode to serial and 
checks the output bit stream again.

The problem is that the I2C verify works but the serial one sometimes
doesn't! It only ever fails for between 1 and 8 bits of the first byte.
For the XC4005XL these should all be 1's but are read as 0's. All the
rest of the bit stream verifies o.k. Since the output has a pull-up on
it I must be ouptu enabling the device correctly and its driving a real
low.

When it fails to verify as above it also fails when trying a real load
of the Xilinx part, with the same number of initial bits being seen as
0's. Power cycling the board several times makes the problem go away.

Anybody else had this sort of problem ?

-- 

_________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 10634
Subject: Re: ViewDraw Info
From: z80@ds2.com (Peter)
Date: Mon, 08 Jun 1998 11:10:43 GMT
Links: << >>  << T >>  << A >>
Viewdraw file version?

>Is there a low-cost read-only viewer for ViewDraw files?


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10635
Subject: Re: FPGA Conversion
From: "Matthew Morris" <mmorris@no_spam.carrieraccess.com>
Date: Mon, 8 Jun 1998 06:47:37 -0600
Links: << >>  << T >>  << A >>
AMI, Matra Harris, Orbit, California Asic, Siquest


Kalyan Gokhale wrote in message <6lfk2h$sf6@newsops.execpc.com>...
>What are the names of the companies doing FPGA to gate array converions?
>
>Kalyan Gokhale
>MagneTek Drives and Systems
>kgokhale@magnetek.com
>


Article: 10636
Subject: Re: ViewDraw Info
From: "Austin Franklin" <darkro9om@ix.netcom.com>
Date: 8 Jun 1998 14:21:14 GMT
Links: << >>  << T >>  << A >>
The other option is to print to a post script file and use GhostScript to
view the post script...  Works well for board level schematics that aren't
hierarchical....

Austin Franklin
darkroom@ix.netcom.com


mstrzalka@my-dejanews.com wrote in article
<6lfm86$pca$1@nnrp1.dejanews.com>...
> Is there a low-cost read-only viewer for ViewDraw files?
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/   Now offering spam-free web-based newsreading
> 
Article: 10637
Subject: Re: FPGA Conversion
From: Jerry English <jenglish@planetc.com>
Date: Mon, 08 Jun 1998 11:44:26 -0400
Links: << >>  << T >>  << A >>
chip express

Matthew Morris wrote:

> AMI, Matra Harris, Orbit, California Asic, Siquest
>
> Kalyan Gokhale wrote in message <6lfk2h$sf6@newsops.execpc.com>...
> >What are the names of the companies doing FPGA to gate array converions?
> >
> >Kalyan Gokhale
> >MagneTek Drives and Systems
> >kgokhale@magnetek.com
> >



Article: 10638
Subject: Re: FPGA Conversion
From: Jerry English <jenglish@planetc.com>
Date: Mon, 08 Jun 1998 11:45:58 -0400
Links: << >>  << T >>  << A >>
And Atmel

Matthew Morris wrote:

> AMI, Matra Harris, Orbit, California Asic, Siquest
>
> Kalyan Gokhale wrote in message <6lfk2h$sf6@newsops.execpc.com>...
> >What are the names of the companies doing FPGA to gate array converions?
> >
> >Kalyan Gokhale
> >MagneTek Drives and Systems
> >kgokhale@magnetek.com
> >



Article: 10639
Subject: Re: Non-periodic clock
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: 8 Jun 1998 15:48:13 GMT
Links: << >>  << T >>  << A >>
Hal Murray <murray@pa.dec.com> wrote in article
<6l9t7h$7sc@src-news.pa.dec.com>...
> 
> You are getting into clock skew so you are justified in being
suspicious.
> 
> Suppose you bring one of these outputs back into the system.  The
clock
> to out time doesn't start when the normal clock ticks.  It gets
delayed
> until the "clock" signal gets out of the first chip and over to
your
> 9500.  Some software may not be able to account for that
complication.

These signals are never routed back into the system.  They are driven
in one state until they are explicitly changed.  I see what you are
saying, if I were to have to bring the signals back into the system. 
Thanks!

-andy

-- 
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM


Article: 10640
Subject: Q: FPGA Place and Route Software
From: mlankenau@yahoo.com (Marcus Lankenau)
Date: Mon, 08 Jun 1998 16:30:44 GMT
Links: << >>  << T >>  << A >>
I want to start with FPGA's and have this question:

Is it possible to use the Xilinx Foundation Series 1.4 (FND-BAS) as
back-end and Orcad or FPGA-Express as front-end???




Marcus Lankenau
Article: 10641
Subject: XC4000: post routing "customization"
From: Thomas Sailer <sailer@ife.ee.ethz.ch>
Date: Mon, 08 Jun 1998 20:28:26 +0200
Links: << >>  << T >>  << A >>
I want to be able to "customize" a circuit just before downloading
the configuration into a Xilinx XC4000 device.

Since the configuration bit stream is not documented by Xilinx,
the only feasible option to do so (short of reverse engineering
the format :-)) seems to be using ROM (16X1) elements in the circuit
to encode the different "runtime options".

If one uses more than one such ROM16X1, the problem arises how to find
out which ROM got placed into which CLB function generator.
Another problem is that the routing tool permutes the ROM address
pins at its discretion, which means that the bit locations listed
in the .LL file must be shuffled accordingly.

The way I did this so far was attaching a BLKNM attribute to every ROM
symbol,
then using a fairly hairy perl script which reads the original XNF file,
the output produced by ncdread (to find out which ROM landed in which
CLB function generator) and the LL file and produces the location
of the configuration bits for every ROM.

The problem with this approach (besides its hairiness) is that the
BLKNM parameter forces every ROM in a different CLB (i.e. no two ROMs
might be put into the same CLB), which is bad for routability in my
current design (filter coeffs).

Is there a better (automatic) approach to do this?

Another issue: how do I recalculate the CRC after changing ROM bits?
I didn't quite understand the CRC circuitry from the XC4000 databook...

Thomas Sailer
Article: 10642
Subject: Re: XC4000: post routing "customization"
From: gah@u.washington.edu (G. Herrmannsfeldt)
Date: 8 Jun 1998 21:53:07 GMT
Links: << >>  << T >>  << A >>
Thomas Sailer <sailer@ife.ee.ethz.ch> writes:

>I want to be able to "customize" a circuit just before downloading
>the configuration into a Xilinx XC4000 device.

>Since the configuration bit stream is not documented by Xilinx,
>the only feasible option to do so (short of reverse engineering
>the format :-)) seems to be using ROM (16X1) elements in the circuit
>to encode the different "runtime options".

>If one uses more than one such ROM16X1, the problem arises how to find
>out which ROM got placed into which CLB function generator.
>Another problem is that the routing tool permutes the ROM address
>pins at its discretion, which means that the bit locations listed
>in the .LL file must be shuffled accordingly.

I think that when I was working on a project like this, and using 
Xilinx RPM's, that it didn't rearrange the pins.  But maybe it does now,
anyway.

>The way I did this so far was attaching a BLKNM attribute to every ROM
>symbol,
>then using a fairly hairy perl script which reads the original XNF file,
>the output produced by ncdread (to find out which ROM landed in which
>CLB function generator) and the LL file and produces the location
>of the configuration bits for every ROM.

If you use 16x2 or 32x1 ROM's then they will fit in one CLB, anyway.

>The problem with this approach (besides its hairiness) is that the
>BLKNM parameter forces every ROM in a different CLB (i.e. no two ROMs
>might be put into the same CLB), which is bad for routability in my
>current design (filter coeffs).

I am not sure what you can do from XNF and what from LCA.  I know some
people have programs that can parse LCA files.  At least I think I heard
of some here that did.

>Is there a better (automatic) approach to do this?

>Another issue: how do I recalculate the CRC after changing ROM bits?
>I didn't quite understand the CRC circuitry from the XC4000 databook...

You can set all the CRC bits to '1', but it shouldn't be too hard to get
the CRC algorithm right.  

>Thomas Sailer
Article: 10643
Subject: Re: XC4000: post routing "customization"
From: "John L. Smith" <jsmith@vis_spamaway_icom.com>
Date: Mon, 08 Jun 1998 19:05:51 -0400
Links: << >>  << T >>  << A >>
Don't mess with the bitstream, use RAM instead of ROM for your
LUTs, with a MUX on the datapath feeding the RAM address inputs.
Load the RAM serially, output of one ram to input of adjacent
RAM, which gives easy routability.

Benefits:
 1) Faster re-configuration (only the RAM's, not entire XC4000)
 2) Simpler S/W ( no worries about checksum, LUT address pinning )

Problems w/ this approach:
  1) Need serial interface to do RAM load 
      ( I2C has worked fine for me, choose something simple, or
       roll your own. Since you already have a serial configuration
      interface to reconfig the part, you can just tie CCLK and CDAT
      to some general I/O pins, not mess with PROG pin )
  2) The mux for the RAM address takes extra CLBs. This may or
    not be many. For an FIR type filter, only one mux
    at the input is necessary. IIR may require 2 muxes.
    However, your current approach is already using only
    1/2 CLB per 16x1 LUT.

I've tried bit-stream modification in the past, w/ XC3042,
and while it works, it is a big hassle for the reasons
you mentioned. I wouldn't do it again unless absolutely
necessary.

Regards,
John L. Smith

Thomas Sailer wrote:

> I want to be able to "customize" a circuit just before downloading
> the configuration into a Xilinx XC4000 device.

> Since the configuration bit stream is not documented by Xilinx,
> the only feasible option to do so (short of reverse engineering
> the format :-)) seems to be using ROM (16X1) elements in the circuit
> to encode the different "runtime options".

> If one uses more than one such ROM16X1, the problem arises how to find
> out which ROM got placed into which CLB function generator.
> Another problem is that the routing tool permutes the ROM address
> pins at its discretion, which means that the bit locations listed
> in the .LL file must be shuffled accordingly.

> The way I did this so far was attaching a BLKNM attribute to every ROM
> symbol,
> then using a fairly hairy perl script which reads the original XNF file,
> the output produced by ncdread (to find out which ROM landed in which
> CLB function generator) and the LL file and produces the location
> of the configuration bits for every ROM.

> The problem with this approach (besides its hairiness) is that the
> BLKNM parameter forces every ROM in a different CLB (i.e. no two ROMs
> might be put into the same CLB), which is bad for routability in my
> current design (filter coeffs).

> Is there a better (automatic) approach to do this?

> Another issue: how do I recalculate the CRC after changing ROM bits?
> I didn't quite understand the CRC circuitry from the XC4000 databook...

> Thomas Sailer
Article: 10644
Subject: Re: XC4000: post routing "customization"
From: "John L. Smith" <jsmith@vis_spamaway_icom.com>
Date: Mon, 08 Jun 1998 19:33:27 -0400
Links: << >>  << T >>  << A >>
Ooops, I made some assumptions:

A) I assumed XC4000EX type part, which has synchronous ram.
   With the old async ram of the 4000, serial loading requires
   playing games w/ the WE input, complicates circuit, adds 1 FF/LUT.

B) Assumed you use slave serial configuration mode. If using a parallel
   mode, then you probably already have the pins connected to implement
   the RAM load circuit.

Hope this helps,
John L. Smith
Article: 10645
Subject: Re: FPGA Conversion
From: Rickman <spamgoeshere2@yahoo.com>
Date: Mon, 08 Jun 1998 21:27:38 -0400
Links: << >>  << T >>  << A >>
Don't forget Xilinx. They have a "Hardwire" version of their FPGAs. I
enquired about them once. They trade off price and minimum quantities so
that you need a minimum order (spread over the first year) of about
$100K. 


Jerry English wrote:
> 
> And Atmel
> 
> Matthew Morris wrote:
> 
> > AMI, Matra Harris, Orbit, California Asic, Siquest
> >
> > Kalyan Gokhale wrote in message <6lfk2h$sf6@newsops.execpc.com>...
> > >What are the names of the companies doing FPGA to gate array converions?
> > >
> > >Kalyan Gokhale
> > >MagneTek Drives and Systems
> > >kgokhale@magnetek.com
> > >

-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10646
Subject: Re: Q: FPGA Place and Route Software
From: Rickman <spamgoeshere2@yahoo.com>
Date: Mon, 08 Jun 1998 21:40:12 -0400
Links: << >>  << T >>  << A >>
Marcus Lankenau wrote:
> 
> I want to start with FPGA's and have this question:
> 
> Is it possible to use the Xilinx Foundation Series 1.4 (FND-BAS) as
> back-end and Orcad or FPGA-Express as front-end???
> 
> Marcus Lankenau

-- 
Even if you can get Orcad to work with the Foundation backend tool, I
would not recommend it. I am using Orcad with the Aliance backend tool,
which I expect is not different from the Foundation tool, and I am
having a lot of trouble with it. I see very inconsistant behavior and
extremely poor documentation. The problems I have had, have cost me over
two weeks of lost time so far. 

As far as is this possible, the Orcad tool puts out EDIF to Xilinx. If
the Foundation tool uses EDIF as the input, then you should be able to
run this way (at your own risk, which will not be slight!)

Does anyone else has experience with running Orcad as a front end to
Xilinx back end tools??? Am I unique in having problems with Orcad?



Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10647
Subject: Multipliers on FPGA's
From: Yves Vandervennet TFE <yves@elmitel.ulb.ac.be>
Date: Tue, 09 Jun 1998 10:16:39 +0200
Links: << >>  << T >>  << A >>
Hi !

	I'm involved in the design of a circuit that must
multiply as fast as possible on 12 bits signed fixed point numbers.
Does anybody know where I can find some literature, some articles
and know-how about implementation of such multipliers ? 

	Thank you and best regards.


						Yves.
Article: 10648
Subject: Re: FPGA Conversion
From: z80@ds2.com (Peter)
Date: Tue, 09 Jun 1998 08:48:16 GMT
Links: << >>  << T >>  << A >>
Also Temic, they also do analog stuff on the same chip.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10649
Subject: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Tue, 09 Jun 1998 10:03:06 GMT
Links: << >>  << T >>  << A >>
Anybody over here with hands-on experience with the
Lattice ispLSI series? 

After many years of designing with simple PLD's,
I am considering to move to something better.
In-system programmability is an important factor,
so the Lattice stuff seems pretty interesting.

What is the best software package to use this
stuff? I have fooled around with the Lattice starters
kit for I while, but I am not impressed. What I would
like is a relatively inexpensive package that allows
mixed HDL and schematic entry.

How about the Lattice ispVHDL/Viewlogic package?
Or the Synario/ABEL software. Which is best and why?
(I have some hands-on experience with ABEL, but not
VHDL. How difficult is this to learn?).

What about the performance of the chips? The timing
model seems much simpler than FPGA's.
Do I need a timing simulator or will a simple calculation
by hand suffice?
What kind of system speed are we talking about? Most
companies talk about flipflop toggle rates only, but
what can be expected in real life?

Thanks.

Rene Kellenbach
The Netherlands



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