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Messages from 10675

Article: 10675
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Wed, 10 Jun 1998 14:31:54 GMT
Links: << >>  << T >>  << A >>
nick toop <nick@cortexco.demon.co.uk> wrote:

>I have used Lattice parts for years.  Originally I used their PDS
>system and thought I was was really good at getting high utilisation.
>However, I have been using Lattice-Synario for some time now and still
>get very good utilisation.  The free starter kit is fine but is limited
>to the smaller devices.  At present I use Synario 5.0 which handles the
>("8000 PLD gate") isp1048 sized parts and I am happy with it.

I have tried the Lattice/Synario starter kit - seems pretty easy to
use. The full version isn't very expensive, and I am tempted to buy
one. However, Viewlogic/VHDL seems a more generally accepted standard,
and I think learning VHDL is not a bad thing.

>I like the ability to mix algebra, truth tables, and schematics and also
>the hierarchical schematics.  I like to see the whole of a design spread
>out in 2D with algebraically defined logic sections displayed as block
>symbols. I like the way you can lock pins and set their characteristics.
>I only use the simulator to check logic function but find it very useful
>for this.

Don't know if Viewlogic/VHDL has these abilities. A local Lattice
representative will visit me tomorrow to demonstrate the Viewlogic
design flow, using the Lattice fitter.

>I am uneasy that using VHDL would lead to large, "slap it together",
>improperly understood, and unnecessarily large designs (like C++ dare I
>say?) . However, I grant the necessity of VHDL (and C++) for larger
>designs and will certainly use it when I have to design more complex
>processing elements.

Me too - I'd like to have the ability to squeeze most out of a chip.
Maybe VHDL is too far away from bare metal. 

>Is there anyone reading this who has made the transition from Synario to
>Viewlogic that still looks back fondly at Synario?  Any other comments?

I hope I can comment on this in a few days.

>Finally, the Synario system has some quirks. The schematic entry tool
>"keeps trying to do the last thing you specified" which is logical
>enough but sometimes seems a bit weird.

I guess this is just something you have to get used to. 

>NB: Vantis (AMD) are offering a very low cost Synario based starter kit
>which seems equivalent to the Lattice starter.

Does AMD offer ISP devices, too?

Thanks,



Article: 10676
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Wed, 10 Jun 1998 14:39:54 GMT
Links: << >>  << T >>  << A >>
nick toop <nick@cortexco.demon.co.uk> wrote:

>I have used Lattice parts for years.  Originally I used their PDS
>system and thought I was was really good at getting high utilisation.
>However, I have been using Lattice-Synario for some time now and still
>get very good utilisation.  The free starter kit is fine but is limited
>to the smaller devices.  At present I use Synario 5.0 which handles the
>("8000 PLD gate") isp1048 sized parts and I am happy with it.

I have tried the Lattice/Synario starter kit - seems pretty easy to
use. The full version isn't very expensive, and I am tempted to buy
one. However, Viewlogic/VHDL seems a more generally accepted standard,
and I think learning VHDL is not a bad thing.

>I like the ability to mix algebra, truth tables, and schematics and also
>the hierarchical schematics.  I like to see the whole of a design spread
>out in 2D with algebraically defined logic sections displayed as block
>symbols. I like the way you can lock pins and set their characteristics.
>I only use the simulator to check logic function but find it very useful
>for this.

Don't know if Viewlogic/VHDL has these abilities. A local Lattice
representative will visit me tomorrow to demonstrate the Viewlogic
design flow, using the Lattice fitter.

>I am uneasy that using VHDL would lead to large, "slap it together",
>improperly understood, and unnecessarily large designs (like C++ dare I
>say?) . However, I grant the necessity of VHDL (and C++) for larger
>designs and will certainly use it when I have to design more complex
>processing elements.

Me too - I'd like to have the ability to squeeze most out of a chip.
Maybe VHDL is too far away from bare metal. 

>Is there anyone reading this who has made the transition from Synario to
>Viewlogic that still looks back fondly at Synario?  Any other comments?

I hope I can comment on this in a few days.

>Finally, the Synario system has some quirks. The schematic entry tool
>"keeps trying to do the last thing you specified" which is logical
>enough but sometimes seems a bit weird.

I guess this is just something you have to get used to. 

>NB: Vantis (AMD) are offering a very low cost Synario based starter kit
>which seems equivalent to the Lattice starter.

Does AMD offer ISP devices, too?

Thanks, Nick.

Rene Kellenbach,
The Netherlands.


Article: 10677
Subject: Re: How about Lattice ispLSI?
From: nick toop <nick@cortexco.demon.co.uk>
Date: Wed, 10 Jun 1998 16:14:45 +0100
Links: << >>  << T >>  << A >>
In article <357e9aa3.4700010@news.multiweb.nl>, Rene Kellenbach
<r.kellenbach@NO_SPAM_multiweb.nl> writes

>   Big snip here   <
>
>Does AMD offer ISP devices, too?
>
>Thanks, Nick.
>
>Rene Kellenbach,
>The Netherlands.
>
>

Yes.  The Vantis parts are ISP using a JTAG interface.  This is what
drew my attention to them as I was wondering if I could use their cheap
hardware/software for general purpose JTAG testing.

-- 
nick toop
Article: 10678
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: Paul Freda <paulfr@ix.netcom.com>
Date: Wed, 10 Jun 1998 09:00:48 -0700
Links: << >>  << T >>  << A >>
> Where is the adventage in using the 8051 for the configuration of the
> fpga instead of using an eeprom?
>
> Marcus

To save a prom.  Not the expense, but manufacturing ease.

 If you have a uC on your board, you already have one e/ee/flash prom.
From the manufacturing point of view, why have another one ?  Put
the 8051 code and the Xilinx bitstream on the same prom.
--

Paul Freda
Sparkle Engineering
Emeryville, CA 94608




Article: 10679
Subject: Re: ViewDraw Info
From: Chris Rottner <crottner@fpga.demon.co.uk>
Date: Wed, 10 Jun 1998 18:26:34 +0100
Links: << >>  << T >>  << A >>
The tool that you are enquiring about is called Viewdraw View only. This
tool allows you to view schematics through your Web Browser. Viewdraw
View Only empowers you with the ability to view your schematic file with
more intelligence than viewing a bit map or another graphics file. For
example you can view attributes associated with components, probe
through levels of heirarchies, etc.

If you require any further information please contact your local
Viewlogic sales office or Value Added Reseller (VAR).

Regards
Chris Rottner 

In article <6lfm86$pca$1@nnrp1.dejanews.com>, mstrzalka@my-dejanews.com
writes
>Is there a low-cost read-only viewer for ViewDraw files?
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/   Now offering spam-free web-based newsreading

-- 
Chris Rottner                 <
 ------------------------  <  <  <  -------- Email: crottner@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >        Tel: +44 1280 700262          |
|                          <  <  <           Fax: +44 1280 700577          |
 ---------------------------  <  ------------------------------------------
Article: 10680
Subject: Re: How about Lattice ispLSI?
From: ems@see_sig.com (ems)
Date: Wed, 10 Jun 1998 17:30:18 GMT
Links: << >>  << T >>  << A >>
my 2 cents: if you're just moving up from plds, get the starter
kit, and stick with abel. i think you can get support for
everything up to the 1032 (1048?) with the starter kit. this gives
you the minimum-investment solution and the smallest learning curve.
you'll have working devices *much* faster than if you decide to go for
VHDL, and it'll cost you a *lot* less.

schematics:

why bother? not only do you have to learn an HDL, but
you also have to learn the schematic package, and how to
integrate the HDL with the schematics. You have to cope with bugs
from both environments and support from 2 vendors (except that
one of them isn't supporting you - you try going to viewlogic/
aldec/etc to tell them that your lattice/xilinx/etc package has
a bug). i personally never use schematics, but i've used synario and
viewlogic, and both are second-rate (but i've seen worse). you often
end up just putting HDL modules on a page with their inputs and
outputs labelled - you might as well just put in a top-level HDL
source instead.

Abel:

+  easy to learn, except that the manuals are useless
+  you can buy it separately - you don't need synario
+  functional simulation is very easy; much easier than
   using a gate-level simulator such as viewsim (also
   second-rate)
-  has it reached end-of-life? i think it probably has.
   this is not a good time to be paying thousands of
   dollars for it.
-  annual maintenance (what do you get for this? nothing,
   in my case)
-  buggy, but you quickly learn what not to do
-  very expensive. why buy it if you're only interested
   in one vendor, and they do a cheap vendor-locked
   version?

Synario:

if you're not convinced that you need schematics, then
forget it. it's much too expensive for what it does.

Lattice starter kit:

+  much cheaper than abel (i paid 2K UKP for abel; if i'd
   waited a couple of months i could have got all the
   devices i was using at that time for a couple of
   hundred dollars in the starter kit)
+  no maintenance
+  covers most of the devices you'd want to use (i reckon
   lattice isn't cost-effective at the 1048 or higher
   level, but i think the kit now includes the 1048
   anyway)

ispVHDL/Viewlogic:

haven't used it, but i have used viewlogic with vhdl and
abel for xilinx, and i guess it's much the same. i didn't
like it - see comments about multiple vendors, viewsim,
need for schematics, etc.

timing:

i'm not sure why, but i've never felt the need to use
anything other than a static timing analyser for
lattice devices (i've used 1016/24/32/48). the timing
is well-defined and the devices don't encourage you
to do things which you'll need a timing simulator to
verify. on the other hand, i always use a timing
simulator with xilinx.
and you get a static analyser with the starter kit
(it's buggy, if i remember correctly, but normally
adequate).

VHDL:

i personally use VHDL for almost everything, but i
would say that - for me - it's not an efficient solution
for devices as small as a 1016 or 1024.

-  *very* hard to learn. if you're faced with a choice
   of learning abel or vhdl, and it's important to get
   results quickly, then it's a no-brainer - go for
   abel.
   it's not just the language, which is bad enough,
   but the synthesis issues, the entire
   design flow, the differences between vendors,
   etc.
+  vendor-independent - loads of people do vhdl
   products. only data i/o (doesn't) support
   abel.
+  in principle, you end up with a design which
   is vendor and technology independent
+  the primary advantage - simulatability. you
   can do far more complex simulations than
   you could hope to do with abel or a gate-
   level simulator.
-  but - you have to buy a separate simulator.
   the "cheap" (!) vendor-locked packages include
   only a synthesiser, which supports only
   a subset of the language.
   this can be expensive - i use modelsim, at
   about 5K UKP.

you often hear people saying that they don't use
vhdl because it's too high-level, too far from the
hardware, etc. but you can use whatever subset of
the language you want - you could even write in
a completely structural style, and just wire up
modules in the same way that you would on a
schematic (or in abel, for that matter).
synthesis shouldn't be a problem - if you stick with the
simple stuff it'll synthesise well.

and forget the device utilisation arguments. if you're
a software engineer and you synthesise vhdl code,
then you may very well end up with lots of unnecessary
hardware; but, if you know what you want, then there's
no reason that you shouldn't get it. 

you can get away without buying a dedicated simulator
and writing testbenches if you're using vhdl, and use a
gate-level simulator (such as viewsim) instead. this
isn't ideal, but it's not really a problem. but, on the
other hand, you're then throwing away one of the
primary reasons for using the language in the first
place.

in short - you need a very good reason, and lots of time,
money, and patience, to start down the vhdl route, even
more so if you want to use schematics as well.

on the other hand, you could start with abel and the
starter kit for almost nothing, and have working
hardware quickly.

evan (ems@nospam.riverside-machines.com)

Article: 10681
Subject: Re: How about Lattice ispLSI?
From: aaj15@dial.pipex.com (Kim Carter)
Date: Wed, 10 Jun 1998 18:58:58 +0100
Links: << >>  << T >>  << A >>
In article <357e9aa3.4700010@news.multiweb.nl>,
	r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach) writes:
> nick toop <nick@cortexco.demon.co.uk> wrote:
> 
>>I have used Lattice parts for years.  Originally I used their PDS
>>system and thought I was was really good at getting high utilisation.
>>However, I have been using Lattice-Synario for some time now and still
>>get very good utilisation.  The free starter kit is fine but is limited
>>to the smaller devices.  At present I use Synario 5.0 which handles the
>>("8000 PLD gate") isp1048 sized parts and I am happy with it.
>

Bear in mind that once you have fixed your pins, getting an acceptable fit
gets increasingly difficult - If you go much over 70% on the 3256's you are
running at rapidly increasing risk of not being able to modify and still get 
a fit. If you are pushing for speed as well this is accentuated - If as you 
suggested in an earlier post you are planning in the field mods, leave a good
margin for it or you will come unstuck.

We were using the 3256 devices - considerably larger, along with a few 
1024s. There was a lot of interest in using the 6000 series - at the time
Synario could not handle these in a properly integrated fashion ie one could 
neither call the RAM/FIFO sections up as 'symbols' in the schematic editor
nor as macros within Abel, is this still the case? and how are these functions
dealt with in the Viewlogic system?

> I have tried the Lattice/Synario starter kit - seems pretty easy to
> use. The full version isn't very expensive, and I am tempted to buy
> one. However, Viewlogic/VHDL seems a more generally accepted standard,
> and I think learning VHDL is not a bad thing.

It rather depends on what else you are likely to do in future - if you are
likely to move on to FPGAs as opposed to other CPLDs, VHDL will handle this
whereas Abel will not. I know there is the ability to use VHDL in Synario - the
starter kit can do VHDL syntax highlighting even if nothing useful with the 
resulting code. However Viewlogic is probably more mainstream so getting
libraries etc. and indeed getting help in the newsgroups is probably easier.

> 
>>I like the ability to mix algebra, truth tables, and schematics and also
>>the hierarchical schematics.  I like to see the whole of a design spread
>>out in 2D with algebraically defined logic sections displayed as block
>>symbols. I like the way you can lock pins and set their characteristics.
>>I only use the simulator to check logic function but find it very useful
>>for this.
> 
> Don't know if Viewlogic/VHDL has these abilities. A local Lattice
> representative will visit me tomorrow to demonstrate the Viewlogic
> design flow, using the Lattice fitter.
> 

There is also the issue of what form the schematics take - Some schematic
editors are basically HDL code generators, so you end up with code which
is entirely in HDL and therefore (within limits) portable, others including
the Synario/Abel arrangement are entirely proprietry and therefore are non
portable. AFAIK the Synario schematic format cannot be exported as anything 
else so you can't eg document your PLD by just embedding the schematic in
a word document, only print it. 
You should also be aware that some systems enable you to take your fitted design
and feed it back into a schematic editor to give a gate level diagram.

No answers, just maybe questions you should be asking yourself and/or your
potential suppliers. 

>>I am uneasy that using VHDL would lead to large, "slap it together",
>>improperly understood, and unnecessarily large designs (like C++ dare I
>>say?) . However, I grant the necessity of VHDL (and C++) for larger
>>designs and will certainly use it when I have to design more complex
>>processing elements.
> 
> Me too - I'd like to have the ability to squeeze most out of a chip.
> Maybe VHDL is too far away from bare metal. 
> 

For designs up to 3256 level Abel can handle it. However, much larger and I
think a greater degree of abstraction is probably necessary.

Simulation - the setup we used involved the use of Test vector files (as with 
small PLDs for 1024s and the like), but a Verilog simulator for the larger 
devices. How we ended up with this arrangement I don't know, but it was a pain
in the butt - swapping between Abel and Verilog every 10 minutes is not
recommended. However I would not recommend raw test vectors either, the use 
of a test harness is much better. The use of VHDL or Verilog throughout (albeit 
with the synthesis using a subset of the language) has definite advantages.

The mix of techniques in Synario also used to have 'funnies' as I recall, which
resulted in the required format of buses crossing levels of hierarchy and or
between Abel and Schematics being inconsistent. This has almost certainly been
dealt with by now, I know we moaned at Synario a lot about it and they did give
the impression of actually listening :-).  

>>Is there anyone reading this who has made the transition from Synario to
>>Viewlogic that still looks back fondly at Synario?  Any other comments?
> 
> I hope I can comment on this in a few days.
> 
>>Finally, the Synario system has some quirks. The schematic entry tool
>>"keeps trying to do the last thing you specified" which is logical
>>enough but sometimes seems a bit weird.
> 

Strange behavior when moving blocks, it tries to redraw the nets in a
rectilinear fashion while you are moving things and won't let you move the
blocks where it can't work out how to route them - personally I prefer a rats
nest either with auto-route when you let the block go or with highlighting on
potential shorts and manual re-routing.
It also behaves to my mind oddly if you put a marquee round part of a net -
ie it selects everything inside the marquee whether a net crosses it of not

Sure one can get used to it but if one uses other tools as well which conform
to more normal windows standards, it can drive you crazy. 

> I guess this is just something you have to get used to. 
> 
>>NB: Vantis (AMD) are offering a very low cost Synario based starter kit
>>which seems equivalent to the Lattice starter.
> 
> Does AMD offer ISP devices, too?
> 

So rumour (mainly from Lattice) had it, the other manufacturers had problems
with data retention - fine if you want built in obsolescence but not much good
if it was expected to work for 10 years or so. Probably bs**t but if you do 
want to use Vantis, might be worth comparing with Lattice.

Cheers
Kim
Article: 10682
Subject: Re: How about Lattice ispLSI?
From: Leon Heller <leon@lfheller.demon.co.uk>
Date: Wed, 10 Jun 1998 20:25:09 +0100
Links: << >>  << T >>  << A >>
In article <2hhml6.mb.ln@ragnarok>, Kim Carter <aaj15@dial.pipex.com>
writes

[deleted]

>There is also the issue of what form the schematics take - Some schematic
>editors are basically HDL code generators, so you end up with code which
>is entirely in HDL and therefore (within limits) portable, others including
>the Synario/Abel arrangement are entirely proprietry and therefore are non
>portable. AFAIK the Synario schematic format cannot be exported as anything 
>else so you can't eg document your PLD by just embedding the schematic in
>a word document, only print it.

I've just experimented with Paint Shop Pro, and successfully captured a
Synario schematic, cropped it and pasted it into a WP document. It looks
a bit grotty, but is good enough for documentation purposes.

[deleted]

Leon
-- 
Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk
Amateur Radio Callsign G1HSM    Tel: +44 (0) 118 947 1424
See http://www.lfheller.demon.co.uk/dds.htm for details of a simple AD9850
DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system.
Article: 10683
Subject: Re: XILINX Foundation - how to minimize project archive?
From: "J.Simmons" <jef@odetics.com>
Date: Wed, 10 Jun 1998 13:21:32 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_000F_01BD9472.AF629CE0
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

The easiest way to reduce the archive size is to delete every VER and =
REV that you have impemented/placed and routed.  This will leave you w/ =
all design entry stuff.
( I do this all of the time)
By doing this you can reduce a 5 + meg file to ~ 1Meg, easy.=20

email me directly if you need additional info; I don't check this NG =
that often.

Jeff
    Alexander Sherstuk wrote in message =
<08210BF6F78BD111AAD80000F8009FD6BCE8CB@NS.amsd.com>...
    Hi ALL,=20

    The problem, which I am trying to solve - how to keep=20
    reasonable size of an archive for the LCA design created with=20
    XILINX Foundation M1.4.=20

    I revealed that Foundation creates a number of intermediate files,=20
    which need not be remembered for successful reconstruction of=20
    the project. An existing FOUNDATION "Archive" feature does=20
    not solve the problem - it just PKZIPs everything, without any=20
    attempt of minimization.=20

    My question is:=20

      Which file extensions must be remembered when archiving Foundation =
project?=20

    Thanks in advance for any Foundation experience,=20

      Alex Sherstuk=20
        sherstuk@amsd.com=20


------=_NextPart_000_000F_01BD9472.AF629CE0
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>

<META content=3Dtext/html;charset=3Diso-8859-1 =
http-equiv=3DContent-Type><TITLE>Q: XILINX Foundation - how to minimize =
project archive?</TITLE><!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML =
3.2//EN">
<META content=3D'"MSHTML 4.72.2106.6"' name=3DGENERATOR>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>The easiest way to reduce the archive size is to =
delete every=20
VER and REV that you have impemented/placed and routed.&nbsp; This will =
leave=20
you w/ all design entry stuff.</FONT></DIV>
<DIV><FONT size=3D2></FONT><FONT size=3D2></FONT><FONT color=3D#000000 =
size=3D2>( I do=20
this all of the time)</FONT></DIV>
<DIV><FONT size=3D2>By doing this you can reduce a 5 + meg file to ~ =
1Meg, easy.=20
</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>email me directly if you need additional info; I =
don't check=20
this NG that often.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>Jeff</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 solid 2px; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
    <DIV>Alexander Sherstuk<SHERSTUK@AMSD.COM> wrote in message &lt;<A=20
    =
href=3D"mailto:08210BF6F78BD111AAD80000F8009FD6BCE8CB@NS.amsd.com">08210B=
F6F78BD111AAD80000F8009FD6BCE8CB@NS.amsd.com</A>&gt;...</DIV>
    <P><FONT face=3D"Arial CYR" size=3D2>Hi ALL,</FONT> </P>
    <P><FONT face=3D"Arial CYR" size=3D2>The problem, which I am trying =
to solve -=20
    how to keep</FONT> <BR><FONT face=3D"Arial CYR" size=3D2>reasonable =
size of an=20
    archive for the LCA design created with</FONT> <BR><FONT =
face=3D"Arial CYR"=20
    size=3D2>XILINX Foundation M1.4.</FONT> </P>
    <P><FONT face=3D"Arial CYR" size=3D2>I revealed that Foundation =
creates a number=20
    of intermediate files, </FONT><BR><FONT face=3D"Arial CYR" =
size=3D2>which need=20
    not be remembered for successful reconstruction of </FONT><BR><FONT=20
    face=3D"Arial CYR" size=3D2>the project. An existing FOUNDATION=20
    &quot;Archive&quot; feature does </FONT><BR><FONT face=3D"Arial CYR" =

    size=3D2>not solve the problem - it just PKZIPs everything, without =
any</FONT>=20
    <BR><FONT face=3D"Arial CYR" size=3D2>attempt of =
minimization.</FONT> </P>
    <P><FONT face=3D"Arial CYR" size=3D2>My question is:</FONT> </P>
    <P><FONT face=3D"Arial CYR" size=3D2>&nbsp; Which file extensions =
must be=20
    remembered when archiving Foundation project?</FONT> </P>
    <P><FONT face=3D"Arial CYR" size=3D2>Thanks in advance for any =
Foundation=20
    experience,</FONT> </P>
    <P><FONT face=3D"Arial CYR" size=3D2>&nbsp; Alex Sherstuk</FONT> =
<BR><FONT=20
    face=3D"Arial CYR" size=3D2>&nbsp;&nbsp;&nbsp; =
sherstuk@amsd.com</FONT>=20
</P></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_000F_01BD9472.AF629CE0--

Article: 10684
Subject: Re: Atmel AT40K
From: "J.Simmons" <jef@odetics.com>
Date: Wed, 10 Jun 1998 13:25:47 -0700
Links: << >>  << T >>  << A >>
the atmel fpga looks like a hybrid of Altera10K and Xilinx4K stuff.

The arch. looks good.  Haven't eval'd the s/w.  I'll wait and see until
'others' are using it since I was beta for brand X once and I am not going
through that again!


Marcus Lankenau wrote in message <3577a520.4119014@news.nordkom.de>...
>
>
>
>How dows the new Atmel AT40K compare to Xilinx XC4000 in price and
>function?
>
>
>
>
>Marcus Lankenau


Article: 10685
Subject: Re: Xilinx Foundation
From: "J.Simmons" <jef@odetics.com>
Date: Wed, 10 Jun 1998 13:27:52 -0700
Links: << >>  << T >>  << A >>
Try calling the hotline, they might be able to help
1-800-255-7778


s.timm wrote in message <35748A7B.879D5656@fh-westkueste.de>...
>I have a problem with Foundation 1.4 from Xilinx.
>
>I cant start the program. Every time messages of errors ocour if I try
>to start the program. The messages are different; missing device;
>PCM.EXE not found; differnt types of DLL  have errors; ...
>My System is a Pentium 133; 64 MB RAM; HDD1 with 2GB and HDD2 with 12 GB
>(exlusive for the cad-system)
>The OS is WIN95B.
>
>I have insall the OS and the software more times and it dosent help.
>
>
>Has anyone a idea ?
>
>S. Timm
>


Article: 10686
Subject: Re: How about Lattice ispLSI?
From: r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach)
Date: Wed, 10 Jun 1998 21:46:29 GMT
Links: << >>  << T >>  << A >>
Ilpo Hamunen <ilpo@dna.fi> wrote:

>The current version of the downloadable Starter SW supports
>all the 1000-, 1000E-, 2000-, 2000V- and GAL-devices.

>Take a look at http://www.latticesemi.com/ftp/synario.html

I know, I already have the free Starter CD.

Thanks, IIpo.

Rene

Article: 10687
Subject: Re: BREAKTHROUGH ASIC PRODUCT---Beta customers needed
From: "kash johal" <kash@ix.netcom.com>
Date: 10 Jun 1998 22:52:43 GMT
Links: << >>  << T >>  << A >>
Peter,

I think you are mistaken about other vendors offering this
price/performance.

Our smallest device is approx 50K useable gates, so we can mux in several
customer codes in the 5K used gate range. Our technology is 0.35 micron
Drawn with 100 ps gate delays.

In a Pq44 package our volume prices would be:

1k	$5.00
5K	$3.50
10K	$2.75
50K	$2.30
100K 	$2.00
1M+	$1.50

Customers can get to the 50K price for exanple with 10 designs averaging 5K
pcs.

Also remember the devices do not require external memory configuration,
will run at 200-300Mhz, and are true ASIC gate counts.

Welcome your thoughts and comments,

Regards,

Kash

Peter <z80@ds1.com> wrote in article
<3581436f.39407184@news.netcomuk.co.uk>...
> Lots of people offer this. It is the unit cost that makes or breaks
> this. What would be the cost of a 5k gate device, in a QFP-44, 1k and
> 5k pieces? From a Xilinx XNF netlist, and with production test vectors
> supplied in a text format?
> 
> Peter.
> 
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.
> 
Article: 10688
Subject: Re: XC4000: post routing "customization"
From: Rickman <spamgoeshere2@yahoo.com>
Date: Wed, 10 Jun 1998 19:36:46 -0400
Links: << >>  << T >>  << A >>
Thomas Sailer wrote:
> 
> I want to be able to "customize" a circuit just before downloading
> the configuration into a Xilinx XC4000 device.
> 
> Since the configuration bit stream is not documented by Xilinx,
> the only feasible option to do so (short of reverse engineering
> the format :-)) seems to be using ROM (16X1) elements in the circuit
> to encode the different "runtime options".
> 
> If one uses more than one such ROM16X1, the problem arises how to find
> out which ROM got placed into which CLB function generator.
> Another problem is that the routing tool permutes the ROM address
> pins at its discretion, which means that the bit locations listed
> in the .LL file must be shuffled accordingly.
> 
> The way I did this so far was attaching a BLKNM attribute to every ROM
> symbol,
> then using a fairly hairy perl script which reads the original XNF file,
> the output produced by ncdread (to find out which ROM landed in which
> CLB function generator) and the LL file and produces the location
> of the configuration bits for every ROM.
> 
> The problem with this approach (besides its hairiness) is that the
> BLKNM parameter forces every ROM in a different CLB (i.e. no two ROMs
> might be put into the same CLB), which is bad for routability in my
> current design (filter coeffs).
> 
> Is there a better (automatic) approach to do this?
> 
> Another issue: how do I recalculate the CRC after changing ROM bits?
> I didn't quite understand the CRC circuitry from the XC4000 databook...
> 
> Thomas Sailer

Actually, this question has been posted here before. Many people think
that the bitstream is not documented. But in postings by Xilinx reps,
they say that if you ask, you can get info on the parts of the bitstream
you really need. 

Other people have pointed out that by using the graphical editor, you
can determine the bit stream mapping for the contents of a CLB. This
then would be part of a repetive pattern in the bit stream. Not too much
work, but there are other problems (as you point out, remapping of CLB
pins...) when you have to reroute your design. Yes, too much work!

Have you thought about using RAM for the coefficient storage? This
eliminates a lot of the problems. The coefficients could be downloaded
just after configuration by the same device that would be recomputing
the bitstream. They could even be stored in the same PROM with the
configuration bits as someone else suggested.

The Xilinx rep who reads this group and often responds to postings is
Peter Alfke. You might try contacting him by email, or you could try
calling the Xilinx hotline. You can get his email address off of one of
his many postings.

-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10689
Subject: Rough time with Orcad???
From: Rickman <spamgoeshere2@yahoo.com>
Date: Wed, 10 Jun 1998 20:14:12 -0400
Links: << >>  << T >>  << A >>
I am doing a Xilinx design using VHDL as well as schematic capture with
Orcad Express. I have been having many serious problems and have been
getting little results by contacting their technical support. 

Does anyone else have experience designing Xilinx FPGAs using Orcad
Express? How did it work for you? Did you use VHDL? Are there any
secrets to getting things to work without crashing the simulator and/or
compiler?  

-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10690
Subject: Re: How about Lattice ispLSI?
From: Ilpo Hamunen <ilpo@dna.fi>
Date: Wed, 10 Jun 1998 17:35:40 -0700
Links: << >>  << T >>  << A >>
Rene Kellenbach wrote:

-snip-

> aaj15@dial.pipex.com (Kim Carter) wrote:
> >The ISP Synario Starter Software is downloadable from the Lattice
> >website or was available as a free CD and reflects the the state
> >of the Synario/ABEL software when I last used it (some time ago)
> 
> I have this Starter CD - seems pretty straightforward, but it is
> limited in device selection and libraries. Don't know about the
> Real Thing.


The current version of the downloadable Starter SW supports
all the 1000-, 1000E-, 2000-, 2000V- and GAL-devices.

Take a look at http://www.latticesemi.com/ftp/synario.html

-snip-

> Best Regards,
> 
> Rene Kellenbach
> The Netherlands.
Article: 10691
Subject: Re: AHDL vs. VHDL vs. Verilog HDl
From: Gary Helbig <ghelbig@slip.net>
Date: Wed, 10 Jun 1998 17:39:44 -0700
Links: << >>  << T >>  << A >>
I won't get into the VHDL vs/ Verilog argument.  But, AHDL is good
for Altera-made chips only, which limits its usefulness.

AHDL also has poor documentation, and a few bugs.

In other words, Verilog, VHDL; pick one.  Or both.  AHDL, stay away.

My opinions only,
Gary.

Victor Levandovsky wrote:
> 
> Hi,
> 
> Which main differencies, anvantages, etc. between this HDL`s?
> Sincerelly,
>    Victor Levandovsky
>    PLD application instructor
>    Technological University of Podillia
>    Ukraine
> 
>    vic@NSalpha.podol.khmelnitskiy.ua
>    remove@NS.for.email.me
Article: 10692
Subject: Re: How about Lattice ispLSI?
From: Garry Allen <garrya@abc.gov.au>
Date: Thu, 11 Jun 1998 11:51:54 +1000
Links: << >>  << T >>  << A >>
Rene Kellenbach wrote:
> 
> aaj15@dial.pipex.com (Kim Carter) wrote:
> Hmm...sounds scary. Maybe the ispVHDL/Viewlogic combo
> is more consistent and not as quirky as Synario. It also seems
> far more complicated to learn - do you have any experience
> with this stuff?
> 
How can I slag the ispVHDL?Viewlogic combination enough. The lattice
fitter is a good tool. the Viewlogic VHDl tools OTOH were the worst I
have ever used. The tool was so poor it could not identify counters from
if rising_edge(clock)
  count <= count + '1';
endif;
The minimised code Viewsynthesis produced for one of my designs would
not fit into a 256 macrocell device with less than 5 levels of logic. I
expected around 190 with 2 levels. Using another tool (Synplicity) I got
the types of resiults I expected. Thsi suggests that the minimisation
from viewlogic is around 30-40% worse than a more optimal tool. FWIW
Lattice use Synplicity for their technical support and are happy to sell
it to you at a much reduced price. If you are serious about using the
lattice devices and VHDL, get the Synplicity tool.
Garry Allen
ABC Technology Research and Development
Article: 10693
Subject: Re: AHDL vs. VHDL vs. Verilog HDl
From: vic@alpha.podol.khmelnitskiy.ua (Victor Levandovsky)
Date: Thu, 11 Jun 1998 05:41:45 GMT
Links: << >>  << T >>  << A >>
On Wed, 10 Jun 1998 17:39:44 -0700, Gary Helbig <ghelbig@slip.net>
wrote:

>I won't get into the VHDL vs/ Verilog argument.  But, AHDL is good
>for Altera-made chips only, which limits its usefulness.
>
>AHDL also has poor documentation, and a few bugs.

What bug?

>
>In other words, Verilog, VHDL; pick one.  Or both.  AHDL, stay away.
>
>My opinions only,
>Gary.
>
>Victor Levandovsky wrote:
>> 
>> Hi,
>> 
>> Which main differencies, anvantages, etc. between this HDL`s?
>> Sincerelly,
>>    Victor Levandovsky
>>    PLD application instructor
>>    Technological University of Podillia
>>    Ukraine
>> 
>>    vic@NSalpha.podol.khmelnitskiy.ua
>>    remove@NS.for.email.me

Sincerelly,
   Victor Levandovsky
   PLD application instructor
   Technological University of Podillia
   Ukraine

   vic@NSalpha.podol.khmelnitskiy.ua
   remove@NS.for.email.me
Article: 10694
Subject: Are you looking for a good VHDL/Verilog Editor?
From: "John Maher" <jmaher@silicon-systems.com>
Date: Thu, 11 Jun 1998 16:49:21 +1000
Links: << >>  << T >>  << A >>
For all of you VHDL or Verilog users:

Silicon Systems Solutions produce a product called "ED for Windows - HDL"
(ED4W-HDL) which is a very sophisticated productivity editor, to FAST TRACK
your VHDL/Verilog code development.

The editor runs under Windows 3.1/95/98/NT

Features include:

+ Syntax Highlighting
+ Automatical Language Template insertion and expansion
+ Automatic TESTBENCH template generation
+ Dozens of common VHDL models for FPGA development
+ Advance Search/Replace across files etc
+ Syntax and Template Expansion support for 30+ other languages, including
C. C++, BASIC, PASCAL

and much more ...


A FREE evaluation copy is available, at
http://www.silicon-systems.com/prod01.htm

The evaluation version is restricted to 45 days use, from the time of
installation

Regards,

John




Article: 10695
Subject: Re: How about Lattice ispLSI?
From: aaj15@dial.pipex.com (Kim Carter)
Date: Thu, 11 Jun 1998 11:01:13 +0100
Links: << >>  << T >>  << A >>
In article <k+7hoAAV2tf1EwC1@lfheller.demon.co.uk>,
	Leon Heller <leon@lfheller.demon.co.uk> writes:
> In article <2hhml6.mb.ln@ragnarok>, Kim Carter <aaj15@dial.pipex.com>
> writes
> 
> [deleted]
> 
>>There is also the issue of what form the schematics take - Some schematic
>>editors are basically HDL code generators, so you end up with code which
>>is entirely in HDL and therefore (within limits) portable, others including
>>the Synario/Abel arrangement are entirely proprietry and therefore are non
>>portable. AFAIK the Synario schematic format cannot be exported as anything 
>>else so you can't eg document your PLD by just embedding the schematic in
>>a word document, only print it.
> 
> I've just experimented with Paint Shop Pro, and successfully captured a
> Synario schematic, cropped it and pasted it into a WP document. It looks
> a bit grotty, but is good enough for documentation purposes.

Is it? did you try resizing it and then passing it to someone with no idea of
what it is supposed to do and ask them to explain it? Sorry this is one of my
hobby horses :-) 

> 
> [deleted]
> 
> Leon

Sure you can do a screen capture to a bitmap format, but if one could export to
a vector file (eg .dxf) it would remain editable - If one is trying to document
something, it is often useful to add annotations, provide zoomed detail views
etc. 
It is also a sad fact of life that if you get it 'perfect' as a bitmap, the tech
pubs or standards people will want it resized (resulting in the text ending up 
unreadable). In addition with the move to non-paper based documentation (html) a
standard vector drawing format can commonly be handled by a browser plug in. 
I have seen to many circuit diagrams, put on web pages as gifs (and indeed 
diagrams in pdf files) which are unreadable to be in favour of the use of 
bitmaps. Given the choice I'd rather read HDL generated from a schematic than
read a 'grunged' bitmap. 

Cheers

Kim
Article: 10696
Subject: Xilinx 4000/Spartan: Maximum pin pullup
From: thiessen@iee.et.tu-dresden.de (Thilo Thiessenhusen)
Date: 11 Jun 1998 10:37:44 GMT
Links: << >>  << T >>  << A >>

Hello,

I have a configuration like this:

                 Vdd
                  |
                 ---
                 | |
                 | | R
                 ---
        _         |          _
  OBUFT _>--------o---------<_ IBUF


What is the maximum resistance that guarantees a valid input level
at any time? Would 100K be O.K.?

[The actual configuration is a bit more complicated since there is
a sensor between OBUFT and the dot, which can switch between
open and about 10-20K].

Thilo





-- 
Support the anti-Spam amendment - Join at http://www.cauce.org/


Article: 10697
Subject: Re: Are you looking for a good VHDL/Verilog Editor?
From: "jc" <jchuan@soft.net>
Date: 11 Jun 1998 11:08:08 GMT
Links: << >>  << T >>  << A >>
I'm interested in the VHDL editor, but I can't access
www.silicon-systems.com,  Would you please tell me how can logon.
Thanks 


Article: 10698
Subject: Re: Xilinx 4000/Spartan: Maximum pin pullup
From: Ed McCauley <edmccauley@bltinc.com>
Date: Thu, 11 Jun 1998 07:24:25 -0400
Links: << >>  << T >>  << A >>
Would turning on the internal pull-up resistor in the 'load' IOB solve
your problem?  I'm assuming you're trying to guard against the sensor
going open circuit.

-- 
Ed McCauley
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA, (908) 996-0817
FAX:   (908) 996-0817


Thilo Thiessenhusen wrote:
> 
> Hello,
> 
> I have a configuration like this:
> 
>                  Vdd
>                   |
>                  ---
>                  | |
>                  | | R
>                  ---
>         _         |          _
>   OBUFT _>--------o---------<_ IBUF
> 
> What is the maximum resistance that guarantees a valid input level
> at any time? Would 100K be O.K.?
> 
> [The actual configuration is a bit more complicated since there is
> a sensor between OBUFT and the dot, which can switch between
> open and about 10-20K].
> 
> Thilo
> 
> --
> Support the anti-Spam amendment - Join at http://www.cauce.org/
Article: 10699
Subject: Re: How about Lattice ispLSI?
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Thu, 11 Jun 1998 12:50:25 +0100
Links: << >>  << T >>  << A >>
Rene Kellenbach wrote:
> 
> Anybody over here with hands-on experience with the
> Lattice ispLSI series?
>...

Here's my offering:

I got the pDS starter kit several years ago, which was OK but very
limited.  Because I wanted to use the 1024, I had to buy "Full pDS", and
all I got extra over the starter kit was support for the full range of
devices.  Even after an upgrade, this software is AWFUL.  It isn't a
true Windows app, doesn't save configuration, etc.  I do all the
minimisation in another tool, generate Boolean and cut/paste that into
pDS (I tried macros, which would have been ideal for my application, but
they were just too badly implemented).  Since my application was, in
several respects, a trivial one, this wasn't any great hardship.  I've
heard several people say the starter Synario is pretty good for a
freebie, but haven't tried it myself.

As to the ICs, they are fine, and have delivered excellent performance. 
I've got reliable 9ns glitch recognition out of a 90MHz part, which I
think is good going.  The only reservation I have, which I pass on
whenever anyone asks about ispLSI, is WATCH YOUR 5V line.  With most
logic ICs, the data sheet says max Vcc (or Vdd) is 7V.  With 74-type
logic, and with many PLDs I've used, if there's a microsecond-order
supply transient which exceeds 7V, even one of over 10V, the ICs don't
die, and some just carry on working as is nothing had happened.  But
ispLSI chips fail short-circuit in an EXTREMELY short time if the rail
exceeds 7.0V.  The fix in my case was to use a 1N5908 across the power
pins relatively close to the IC.  I also used a tantalum bulk decoupler
to limit the rise rate of 5V transients.  If you can guarantee that your
board's power rails will NEVER glitch this way, then you are very
fortunate, and should ignore this problem.  I couldn't so protected the
devices explicitly.  The failure mode is related to the charge pump
involved in providing 5V-only isp, so is likely to be found in other isp
families.

Support, from distributors and from Lattice, has been patchy.  Sometimes
it's been excellent, sometimes poor.  No obvious reason for the
variation.

Final point.  When you want to buy some ICs, check all approved
distributors.  I encountered pricing ranges of more than 2:1, together
with widely differing stocking systems, delivery charges, minimum
orders, "we'll have to get those from the States and won't do that for
less than X devices and XXX dollars", etc.

Hope this helps.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions


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