Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Peter Korsgaard schrieb: > >>>>> "Antti" == Antti <Antti.Lukats@xilant.com> writes: > > Hi, > > Antti> My bet is NO. you are of course welcome to try! > > It definately won't work. > > Antti> but Xilinx has announced that www.lynuxworks.com is supposed to release > Antti> 2.6.x base linux distributions soon(ppc end of August, microblaze and > Antti> of 2006) , so I hope whatever there may be issues with 2.6.x are solved > Antti> by then. on montavista the ppc linux is given as version 2.4.18, but > Antti> there are also some comments about using the official ppc-linux tree > Antti> (2.6.x) for V4 without problems. > > Yes, V2P/V4 is nicely supported in the kernel (since Dec 2004). What > is not included is device drivers for all the Xilix IP cores. > > -- > Bye, Peter Korsgaard Peter, could you please please elaborate what does this 'nicely supported' mean? if there are no drivers then all the stuff is only of 'academic interest' - as it has no real world value. Or is there a way to actually use the kernel that has been available since Dec 2004 as you say in real world applications, in real V2Pro/V4 doing some real tasks? I am struggling with V4 ppc linux (kernel 2.4.x) where I see SIGSEGV when doing dlclose() - could it be that retrieving the sources from kernel.org ? that problem goes away? hm that problem is related to ppc implementation of the libc actually, but as libc is pretty much a must have part of linux then when its all 'nicely supported' then there should be no problems with libc? AnttiArticle: 108076
hi i'm on the final bit of the indi core, which is the sequencing unit. i have decided to go for a 4 clock bus cycle, and so a read takes 4 cycles etc. there are 4 bus cycle types read, write, fetch and bushalt. so this gives 16 "microcode lines". the question is a solution for minimum area would be best done as a 16 way decoder, or as a fourway 4 parallel decoder with a 4 way post mux?? any input on minimum area solutions?? cheersArticle: 108077
Torsten Alt schrieb: > Another thing is that i would try to avoid to compare values with > "greater " or "lower" than a value. This can increase your logic since > the synthesizer has to synthesize all this cases. In your case i would I disagree. Using '=' for counters may decrease your logic but may also increase your logic[1]. But it will always be a pitfall, if your counter value gets over (for inc-counter, else under)) the value your looking for, due to any reason. I just had to remove a bug from a co-designer basing on this pitfall. For a simple counter there are only external reasons like SEU that will lead to this pitfall, in complex designs, there might be a erroneous written if-then-else path leading to the situation were your counter waits forever. bye Thomas [1] A 8 bit '=' needs 15 XOR2. A 8 bit '> 127' is free in terms of gates.Article: 108078
I changed my design to (like Antti suggested): port1 <= port2 when (port1_output_enable = '1') else 'Z'; port2 <= port1 when (port2_output_enable = '1') else 'Z'; but this doesn't work in Altera Quartus Simulation :-((( the output at port1 and port2 shows "Z" when enabled and otherwise "Unknown" Is this just an malfunction of Quartus Simulation???? and will it work in real hardware (Altera MAX3000A)??? Manfred "Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag news:1157115749.090604.75380@m73g2000cwd.googlegroups.com... > Manfred Balik schrieb: > >> Thanks to KJ and Antti for your prompt answers!!! >> >> I see - I will need a enable signal for each direction, because I want a >> synthesizable code not a simulation (I thought this is easy, just a >> connection :-( ). >> >> the PCA9515 is a really nice bidirectional level converter, but I think >> he >> has a enable signal, too. Not a external direction signal, but internally >> generated out of weak low (the output of the PCA9515) and hard low (if >> the >> input is low). >> >> Manfred >> >> "KJ" <Kevin.Jennings@Unisys.com> schrieb im Newsbeitrag >> news:1157109054.812511.131460@b28g2000cwb.googlegroups.com... >> > >> > Antti wrote: >> >> > >> >> > What you probably need to add is the concept of an output enable for >> >> > both port1 and port2 and only drive the outputs when that output is >> >> > enabled... >> >> > >> >> > port1 <= port2 when (port1_output_enable = '1') else 'Z'; >> >> > >> >> > KJ >> >> >> >> KJ >> >> >> >> bidir connections between to io's are sometimes possible also when >> >> no enable signal exists, see NXP's I2C extender as one example >> >> >> >> http://www.nxp.com/pip/PCA9515DP.html >> > >> > Yes, and an even simpler example of a bi-directional connection between >> > two I/Os with no enable or direction signal is a resistor. >> > >> > Since I wasn't quite sure exactly what the original poster was trying >> > to do, I mentioned "What you probably need...." on the assumption that >> > he is trying to come up with synthesizable code targetting some >> > FPGA/CPLD or such (in which case I believe he will be needing the >> > enable). >> > >> > If instead the poster was interested in a non-synthesizable simulation >> > model that connects two things bi-directionally without a 'direction' >> > or 'enable' signal (i.e. like a resistor or the part you linked) than >> > he will be wanting a different code entirely. >> > >> > KJ >> > > > the PCA9515 was just an example reference. it is not generic bidir > buffer - such thing is not possible by definition. PCA9515 is somwehat > 'protocol aware' and can be used as if it would be transparent bidir > buffer for the constrained use of the I2C bus. > > sometimes similar bidirectional buffer is possible to be implemented in > PLD or FPGA or MCU also, but it always needs some 'protocol awareness' > and some timing reference to avoid self-lockup. > > Antti >Article: 108079
Hi Have you see this page: http://www.cs.york.ac.uk/rtslab/demos/amos/xupv2pro/ It helped me getting an 2.6.17.1. kernel running on an xilinx xup board. The network is doing dhcp but is somehow broken. I managed to install debian sarge on this board. STArticle: 108080
hi just wondering if grey code (1 bit change) addressed stack memory might be useful for cutting down carry chain logic for pre-post dec/inc addressing?? cheers From paulu@sx4all.nl Tue Sep 05 02:54:45 2006 Path: newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!border2.nntp.ams.giganews.com!nntp.giganews.com!transit.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <44fd4968$0$4422$e4fe514c@dreader32.news.xs4all.nl> From: Paul Uiterlinden <paulu@sx4all.nl> Subject: Re: bidirectional connection between two bidirectional ports Newsgroups: comp.arch.fpga,comp.lang.vhdl Date: Tue, 05 Sep 2006 11:54:45 +0200 References: <44f7ead6$0$11094$3b214f66@tunews.univie.ac.at> <1157105399.378243.82790@m73g2000cwd.googlegroups.com> <1157107617.801943.12170@b28g2000cwb.googlegroups.com> <1157109054.812511.131460@b28g2000cwb.googlegroups.com> <44f81b42$0$12126$3b214f66@tunews.univie.ac.at> <1157115749.090604.75380@m73g2000cwd.googlegroups.com> <44fd3402$0$11094$3b214f66@tunews.univie.ac.at> User-Agent: KNode/0.8.0 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 22 NNTP-Posting-Host: 213.84.176.29 X-Trace: 1157450088 dreader32.news.xs4all.nl 4422 213.84.176.29:10424 Xref: prodigy.net comp.arch.fpga:118965 comp.lang.vhdl:66215 Manfred Balik wrote: > I changed my design to (like Antti suggested): > port1 <= port2 when (port1_output_enable = '1') else 'Z'; > port2 <= port1 when (port2_output_enable = '1') else 'Z'; > but this doesn't work in Altera Quartus Simulation :-((( > the output at port1 and port2 shows "Z" when enabled and otherwise > "Unknown" Is this just an malfunction of Quartus Simulation???? and > will it work in real hardware (Altera MAX3000A)??? When setting for example port1_output_enable='1' and port2_output_enable/='1', something else should drive port2. Either your testbench or another part of the design. This driver should be tri-stated if port2_output_enable='1' and driven by some source if port2_output_enable/='1'. Just draw the diagram of these drivers with their enable signals, and see how you must control the enable signals to avoid contention (i.e. driving to strong values on a signal). -- Paul.Article: 108081
"Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message news:44fd3402$0$11094$3b214f66@tunews.univie.ac.at... >I changed my design to (like Antti suggested): > port1 <= port2 when (port1_output_enable = '1') else 'Z'; > port2 <= port1 when (port2_output_enable = '1') else 'Z'; > but this doesn't work in Altera Quartus Simulation :-((( > the output at port1 and port2 shows "Z" when enabled and otherwise > "Unknown" > Is this just an malfunction of Quartus Simulation???? and will it work in > real hardware (Altera MAX3000A)??? Depends completely on what your model for port1 and port2 are doing. Do you have some form of VHDL model for the external 'things' that are driving port1 and port2? Are you trying to 'force' them? If forcing, how? Since port1 and port2 are I/O pins on your design, then when things are just 'sitting there' (i.e. port1_output_enable and port2_output_enable are both '0') then port1 and port2 will be sitting there at 'Z'. When port1_output_enable goes to a '1', your design should start driving port1 (i.e. now it's an output) with whatever is on port2 (which is now an input). So, ask yourself, at that time, what is driving port2? The answer is that it is your simulation testbench, port2 needs to be driven, at that time, just like any other input to your design. Once you've got that understood, you'll need to answer the same questions about port1 when your signal 'port2_output_enable' is active. KJArticle: 108082
Tanks for your answers ... Now it works - it was just a handling error of the Quartus Simulator by me (embarrassing) Manfred "KJ" <kkjennings@sbcglobal.net> schrieb im Newsbeitrag news:O6cLg.15443$%j7.3213@newssvr29.news.prodigy.net... > > "Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message > news:44fd3402$0$11094$3b214f66@tunews.univie.ac.at... >>I changed my design to (like Antti suggested): >> port1 <= port2 when (port1_output_enable = '1') else 'Z'; >> port2 <= port1 when (port2_output_enable = '1') else 'Z'; >> but this doesn't work in Altera Quartus Simulation :-((( >> the output at port1 and port2 shows "Z" when enabled and otherwise >> "Unknown" >> Is this just an malfunction of Quartus Simulation???? and will it work in >> real hardware (Altera MAX3000A)??? > > Depends completely on what your model for port1 and port2 are doing. Do > you have some form of VHDL model for the external 'things' that are > driving port1 and port2? Are you trying to 'force' them? If forcing, > how? > > Since port1 and port2 are I/O pins on your design, then when things are > just 'sitting there' (i.e. port1_output_enable and port2_output_enable are > both '0') then port1 and port2 will be sitting there at 'Z'. When > port1_output_enable goes to a '1', your design should start driving port1 > (i.e. now it's an output) with whatever is on port2 (which is now an > input). So, ask yourself, at that time, what is driving port2? The answer > is that it is your simulation testbench, port2 needs to be driven, at that > time, just like any other input to your design. Once you've got that > understood, you'll need to answer the same questions about port1 when your > signal 'port2_output_enable' is active. > > KJ >Article: 108083
jacko wrote: > hi > > just wondering if grey code (1 bit change) addressed stack memory might > be useful for cutting down carry chain logic for pre-post dec/inc > addressing?? Not sure exactly what you are getting at here ? Gray code ctrs might only toggle one bit, but their creation is more complex than binary counters - often it is Binary ctrs + XOR's. - ie they are not likely to be faster counters. Johnson counters can avoid carry chains, but they have lower densities (do not cover all binary states) The best solution could vary with exact target device & mappings, and counter length, so I'd suggest create some of each candidate, and check the reported speeds. -jgArticle: 108084
jacko wrote: > just wondering if grey code (1 bit change) addressed stack memory might > be useful for cutting down carry chain logic for pre-post dec/inc > addressing?? I wouldn't expect it to. Do you have a good algorithm for incrementing grey code? If you have a good method it might be better.Article: 108085
J Thomas wrote: > jacko wrote: > > > just wondering if grey code (1 bit change) addressed stack memory might > > be useful for cutting down carry chain logic for pre-post dec/inc > > addressing?? > > I wouldn't expect it to. Do you have a good algorithm for incrementing > grey code? If you have a good method it might be better. PRBS sequences, maximal length!!! don't rotate the word, rotate the xor bit taps and insert location!!! ok cheers!Article: 108086
"Michael A. Terrell" wrote: > Steve at fivetrees wrote: >> "Michael A. Terrell" <mike.terrell@earthlink.net> wrote in message >>> Luhan wrote: >>>> >>>> The famous N.E.D. (noise emitting diode) - goes bang just one time! >>> >>> Install a 1N34 across a light switch with the power off an d the >>> switch is on. Turn the power back on and wait for someone to >>> shut it off. Then there is a loud bang, but the light still >>> works when they turn it back on. I used to have 5000 spares. ;-) >> >> My kinda guy ;). > > I got some people more than once. Anyway, what else would you use > unmarked germanium diodes for? You can only use so many in > prototypes. I used to install a roughly 68 ohm 1/2 watt carbon resistor across the AC mains (110 volt) after the power switch. This was usually done at lunch time, while someone else was preparing for his initial smoke test on a new instrument (back in the days of tubes). The result was a satisfactory grrr-bang and smoke. Modern resistors don't work as well, they just fizzle. -- "I'm the commander--see, I don't have to explain -- I don't need to explain why I say things. That's the interesting thing about being the President. Maybe somebody needs to explain to me why they say something, but I don't feel like I owe anybody an explanation." - George W. Bush, 2002-11-19Article: 108087
hi sorry, this is corrected /.s=q /.q.r ; get 1st pointer to q /.q.r /.q.r ; copied 3 16 bit words to r /=q.r /.s=q ; save address for write over and get other address /.q.s /.q.s ; get other 3 16 bit words to s /.q.s /=q.s ; and save q on s /.r=q /.s.r ; restore 1st address /.s.q /.s.q ; overwrite 3 16 bit words /.s.q /.r=q ; restore 2nd pointer in q (correction) /.r.q /.r.q ; overwrite 2nd set /.r.q /=p.p ; and a nop (possible faster pipeline) cheersArticle: 108088
In comp.lang.forth jacko <jackokring@gmail.com> wrote: > just wondering if grey code (1 bit change) addressed stack memory > might be useful for cutting down carry chain logic for pre-post > dec/inc addressing?? If it's just adders you want to avoud, I've seen linear feedback shift regsiters used for this: very small and cheap. Andrew.Article: 108089
Hi, I have tried to synthesize the synchronous fifo example "FIFO.vhd" from Ben Cohen's book "Real Chip Design and Verification Using Verilog and VHDL" on a Lattice EC15 (Synplicity compiler) For the FIFO registers declaration I add the following attribute : attribute syn_ramstyle : string; attribute syn_ramstyle OF FIFO_r : SIGNAL IS "block_ram"; And yet the synthesis results show that no Embedded RAM blocks are used. Is the used attribute not appropiate or is Synplify not able to implement the registers as EBR in that hardware description? Thank you for your opinion. Rgds Andr=E9Article: 108090
Hello all, Does anybody have a simple dma example that dma's from a custom peripheral to the SRAM or SDRAM on the ML403 board? I really only need the VHDL for the custom peripheral & the source code for the example. Thanks, HarryArticle: 108091
"CBFalconer" <cbfalconer@yahoo.com> wrote in message news:44FD685C.9311F3B1@yahoo.com... > "I'm the commander--see, I don't have to explain -- I don't need > to explain why I say things. That's the interesting thing about > being the President. Maybe somebody needs to explain to me why > they say something, but I don't feel like I owe anybody an > explanation." - George W. Bush, 2002-11-19 Just out of curiosity, what is the source of that quote? If I quote it, people are going to ask me how I know it's genuine.Article: 108092
"mc" <look@www.ai.uga.edu.for.address> wrote in message news:EmfLg.47233$e9.7114@bignews4.bellsouth.net... > "CBFalconer" <cbfalconer@yahoo.com> wrote in message > news:44FD685C.9311F3B1@yahoo.com... > >> "I'm the commander--see, I don't have to explain -- I don't need >> to explain why I say things. That's the interesting thing about >> being the President. Maybe somebody needs to explain to me why >> they say something, but I don't feel like I owe anybody an >> explanation." - George W. Bush, 2002-11-19 > > Just out of curiosity, what is the source of that quote? If I quote it, > people are going to ask me how I know it's genuine. Found it. CBS News, dated 2002/11/17: http://www.cbsnews.com/stories/2002/11/17/60minutes/main529657.shtmlArticle: 108093
rickman wrote: > Peter Alfke wrote: > >>Rickman, the SRL16 (or SRL32 in Virtex-5) really is a "physical" shift >>register that transfers all data bits to their respective neighbors. So >>it will probably consume more power than a pointer-addressed RAM. >>But you don't need the pointer, and it's also a neat way to load a LUT >>with its 16 bits. > > > I wasn't aware of that. Is this only true for the V5 parts, or has > this always been true for SRLs in Xilinx parts that have them? > Rickman, The SRLs do move the data, and always have. The shift register in pre-V5, as I understand it is latches rather than master-slave FFs. Maybe that is what caused the confusion. The SRL16's do move the data though. Think of the structure as a 16 bit shift register with a 16:1 mux on the outputs. The LUT address goes to the 16:1 mux select lines. The shift register is not shifted when used as a LUT, but is shifted when used as an SRL16.Article: 108094
CBFalconer wrote: > > I used to install a roughly 68 ohm 1/2 watt carbon resistor across > the AC mains (110 volt) after the power switch. This was usually > done at lunch time, while someone else was preparing for his > initial smoke test on a new instrument (back in the days of > tubes). The result was a satisfactory grrr-bang and smoke. Modern > resistors don't work as well, they just fizzle. And some people think Carbon Comp resistors are useless. ;-) -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 108095
Does anyone know where Xilinx has hidden a Programmers Guide to the Microblaze similar to Altera's Nios one? I've search all over Xilinx's website and all I can find the the MicroBlaze Processor Reference Guide. This is just a hardware look at the Softcore I'm trying to find info on some of the predone C function calls like: printf? GPIO_toggle? etc If you have a link that would help me out!!! Thanks, EricArticle: 108096
CBFalconer wrote: > I used to install a roughly 68 ohm 1/2 watt carbon resistor across > the AC mains (110 volt) after the power switch. This was usually > done at lunch time, while someone else was preparing for his > initial smoke test on a new instrument (back in the days of > tubes). The result was a satisfactory grrr-bang and smoke. Modern > resistors don't work as well, they just fizzle. > Reminds me of a tech that liked to insert a small loop of rosin-core solder into another tech's bench outlets. These gave a very satisfying BANG and smoke, but had the down side of ruining the outlet, so you couldn't play the trick too many times....Article: 108097
Eric schrieb: > Does anyone know where Xilinx has hidden a Programmers Guide to the > Microblaze similar to Altera's Nios one? > > I've search all over Xilinx's website and all I can find the the > MicroBlaze Processor Reference Guide. This is just a hardware look at > the Softcore > > I'm trying to find info on some of the predone C function calls like: > > printf? > GPIO_toggle? > etc > > If you have a link that would help me out!!! > > Thanks, > Eric Eric, I think for printf you are better reading some generic book about C programming? as a side note, the printf() for Microblaze costs you around 36KB of code - so it is recommended to use xil_printf if you need small applications. sure the xil_printf doesnt always work. things like GPIO_toggle have NOTHING todo with MicroBlaze so there is no need to talk about them in microblaze documents. You need to check the library function for the GPIO driver for the version you are using, the API have been changed between GPIO versions that are no in sync with MicroBlaze or EDK revisions. This is when you are using XPS standalone applications. if you are using some other environment like maybe uClinux or some other OS the the way you access the GPIO may be way different. GPIO toggle is basically read offset 0 togge bit write back the is can be done using different methods and drivers. if you need to have fast access then you should avoid xilinx high level APIs as they can make the bit-bang GPIO access maybe up to 10 slower ! AnttiArticle: 108098
On Tue, 5 Sep 2006 10:02:40 -0400, "mc"
<look@www.ai.uga.edu.for.address> wrote:
>"mc" <look@www.ai.uga.edu.for.address> wrote in message
>news:EmfLg.47233$e9.7114@bignews4.bellsouth.net...
>> "CBFalconer" <cbfalconer@yahoo.com> wrote in message
>> news:44FD685C.9311F3B1@yahoo.com...
>>
>>> "I'm the commander--see, I don't have to explain -- I don't need
>>> to explain why I say things. That's the interesting thing about
>>> being the President. Maybe somebody needs to explain to me why
>>> they say something, but I don't feel like I owe anybody an
>>> explanation." - George W. Bush, 2002-11-19
>>
>> Just out of curiosity, what is the source of that quote? If I quote it,
>> people are going to ask me how I know it's genuine.
>
>Found it. CBS News, dated 2002/11/17:
>http://www.cbsnews.com/stories/2002/11/17/60minutes/main529657.shtml
>
Yep. CBS/Wallace/Woodward... the kind of source that makes the
stomach turn.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 108099Thanks Antti, But were is a document that talks about xil_printf and other predone xilinx specific C routines. I know what printf does and I know how to toggle GPIO, but does xil_printf support %c, %d, %i.... etc. Altera did up a very nice Nios Programmers Reference Guide, I gues I assumed Xilinix did something similar, but I can find it on there website. Eric
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z