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Messages from 108725

Article: 108725
Subject: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
From: Kolja Sulimma <news@sulimma.de>
Date: Fri, 15 Sep 2006 18:58:02 +0200
Links: << >>  << T >>  << A >>
Austin Lesea schrieb:
> Joseph,
> 
> I was worried that FPGA_Editor was also not in webpack, but, the worry
> was unfounded.

This is great news. I was not there in earlier versions.
FPGA Editor was the only reason for our university to file donation
requests for foundation software.

It is good for teaching to show the students that there actually is
a circuit generated from their VHDL.

Kolja Sulimma

Article: 108726
Subject: Re: microblaze lwip
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: 15 Sep 2006 10:28:13 -0700
Links: << >>  << T >>  << A >>
as i posted bevore in the mms file config_sema=true is set. i rebuilt
the libraries and still the same.


Article: 108727
Subject: Re: Fusion
From: "Antti" <Antti.Lukats@xilant.com>
Date: 15 Sep 2006 10:29:06 -0700
Links: << >>  << T >>  << A >>
Eli Hughes schrieb:

> Antti wrote:
> > Eli Hughes schrieb:
> >
> >
> >>Does anyone know if ANY of the Actel fusion devices are available for
> >>purchase?
> >>
> >>-Eli
> >
> >
> > I received some PQ208 fusion chips over 6 weeks ago already.
> > so I assume the answer is yes.
> >
> > Antti
> >
>
>
> Where did you order? I just called avnet and they said 6-month lead
> time.   You want to sell any of yours??
>
> -Eli

please contact me in private.
I have an interesting project, and I may have some
funding in terms of FPGA silicon, eval boards.

Antti


Article: 108728
Subject: Re: upgrading firmware on stratix 2 without NIOS IDE
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Fri, 15 Sep 2006 11:26:03 -0700
Links: << >>  << T >>  << A >>
Jeff Johnson wrote:
> I am writing a firmware application that allows the verilog hardware on
> the stratix 2 board to communicate via rs232 to a C# application.  I
> would like to add the functionality into the C# app to upgrade the
> firmware on the board, as new functions become available.  I'd like to
> be able to send a flash file from PC to the board, store it to flash
> and have the new version load on reset.
> 
> 
> ANY INFORMATION is GOOD INFORMATION
> 
> Jeff
> 

Was there a question in there?

Here's some information that might be useful:
My shoe size is 12.:)

Your idea sounds perfectly reasonable.

-Dave

-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 108729
Subject: Re: USB programming cables
From: "Paul" <pauljbennett@gmail.com>
Date: 15 Sep 2006 11:37:46 -0700
Links: << >>  << T >>  << A >>
Digilent sells a USB JTAG cable.  The downside is it isnt compatible
with Xilinx drivers, so you have to download and use the digilent load
software.  This adds an extra step to the process, although ExPort (the
digilent software) will download the BIT file into the FPGA fine, you
have to take some additional steps to get an SVF file out of your MCS
file for the PROM, the load the PROM from the digilent software from
the SVF.


John_H wrote:
> I've been using the Xilinx Platform Cable USB for some time.  They now have
> a second generation out there with lower power *and* is lead free.  I only
> wish I could have multiple USBs connected at once since my Xilinx Spartan3E
> starter kit board has a "built-in" platform USB cable that just needs a
> standard USB cable to connect to my system.  So nice.
>
>
> "Simon" <news@gornall.net> wrote in message
> news:2006091508283364440-news@gornallnet...
> > So, having bought the V4FX-12 kit from NuHorizons, it arrived with a
> > parallel-port JTAG cable. Normally I'd be just *fine* with this, but today
> > my new quad-xeon Mac-pro arrives, and I bought that specifically to get
> > some oomph in P&R (running linux using "parallels", of course).
> >
> > The mac doesn't have a parallel port. Ahhh. Is there a USB programming
> > cable suitable for the FX-12 ? A fallback plan is to do most of the work
> > on the Mac, but have a mini-itx machine next to it just for programming -
> > the itx machine *does* have a // port, but it's woefully underpowered for
> > any serious work on it...
> >
> > Ideas gratefully received :-)
> >
> > Simon
> >


Article: 108730
Subject: Re: net skew
From: "Paul" <pauljbennett@gmail.com>
Date: 15 Sep 2006 11:41:09 -0700
Links: << >>  << T >>  << A >>
If you use the global clock buffers and global clock lines, then you
clocks should be *very* skew controlled, as that is their purpose.
Your P&R should infer this though if you dont explicitly specify it...
make sure it's using them and maybe check the datasheet to see what the
maximum skew is spec'ed at for them.  0.8ns seems high I think.

maxascent wrote:
> Hi
>
> I have a design that I am having trouble routing. When I look at the clock
> signals the net skew for one is about 0.8ns were the other are less than
> 0.1ns. Could this be my problem and if so does anyone have any
> surgestions.
> 
> Thanks
> 
> Jon


Article: 108731
Subject: Re: Critcal path in XILINX ISE (XST)
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 15 Sep 2006 11:44:41 -0700
Links: << >>  << T >>  << A >>
That should be in the "Timing Report" section of the XST report.
However, the timing report from synthesis tools are just an estimate
and sometimes they can be way off. I would run the Timing Analyzer on
the placed & routed design to get more accurate timing information.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/

Mak wrote:
> Hi,
> Can you please tell me where I can see the critical path in Xilinx ISE
> tool? I am using XST as synthesis tool.
> Regards


Article: 108732
Subject: shift register with clock divder and debounce.....HELP
From: "andrew browning" <ahb3@mac.com>
Date: 15 Sep 2006 11:49:06 -0700
Links: << >>  << T >>  << A >>
I am designing a four-bit shift register using four 4 - 1 MUXes and
four D Flip-Flops.  This is to be connected in a schematic to a
push-button debounce switch and a clock divider.

My shift register works when i test-bench the verilog, but when
coonected to the other components in the schematic, the shift register
doesn't select; The output is always the default value in the MUX's
case statement.  Can anyone help????  This was done in xilinx ise 6.3i.
 The code below is the flip flop, the mux, the structural verilog of
the shift reg, a switch debounce and a clock divider


module dFlipFlop(clk, reset, d, q);  //Port List
	input clk;
	input reset;
	input d;
	output q;
	reg q; //Redeclaration of output
always@(posedge clk or posedge reset)begin
	if(reset == 1'b1)begin
		q = 1'b0;
	end
	else begin
	q = d;
	end
end
endmodule



module fourToOneMux(i0, i1, i2, i3, sel, y);
	input i0, i1, i2, i3;
	input [1:0] sel;
	output y;
	reg y;
always@(i0 or i1 or i2 or i3 or sel)begin
	case({sel})
		2'b00: y = i0;
		2'b01: y = i1;
		2'b10: y = i2;
		2'b11: y = i3;
		default: y = 2'hx;//garbage
	endcase
end
endmodule




module shiftRegisterFourBit(clk,reset,si,m0, m1,d,q);
    	input clk, reset;
    	input si, m0, m1;
    	input [3:0] d;
    	output [3:0] q;
    	wire[3:0] q;
	wire w0, w1, w2, w3;

		fourToOneMux	mux0(q[1], si, d[0], q[0],{m1, m0}, w0);
		fourToOneMux	mux1(q[2], q[0], d[1], q[1],{m1, m0}, w1);
		fourToOneMux	mux2(q[3], q[1], d[2], q[2],{m1, m0}, w2);
		fourToOneMux	mux3(si, q[2], d[3], q[3], {m1, m0}, w3);

		dFlipFlop		dff0(clk, reset, w0, q[0]);
		dFlipFlop		dff1(clk, reset, w1, q[1]);
		dFlipFlop		dff2(clk, reset, w2, q[2]);
		dFlipFlop		dff3(clk, reset, w3, q[3]);


endmodule



module switchDebounce(clk, reset, din, dout);
input clk, reset, din;
output dout;
wire dout;
reg q3, q2, q1, q0;

always@(posedge clk or posedge reset)
	if(reset == 1'b1)
	{q3, q2, q1, q0} <= 4'b0;
	else begin
	q3 <= q2;
	q2 <= q1;
	q1 <= q0;
	q0 <= din;
	end
assign dout = !q3 & q2 & q1 & q0;
endmodule


module clkDivider(clk,reset,clk_out);
    input clk, reset;
    output clk_out;
    reg clk_out;
    integer count;
always@(posedge clk or posedge reset)
	if(reset == 1'b1)
		count = 0;

	else begin
		count = count + 1;
		if(count >= 25000)begin
		clk_out = ~clk_out;

		end
	end
endmodule


Article: 108733
Subject: Re: ispDesignExpert available for download anywhere ?
From: "Rajeev" <rrr@ieee.org>
Date: 15 Sep 2006 12:28:34 -0700
Links: << >>  << T >>  << A >>
Luc,

That's very helpful, I think you made the sale ;-)  And the MACH 4A5
looks good, I'm glad the quiescent current is lower than the 16V8 22V10
devices.  It took me a while to find them available in distribution,
mostly because they're called M4A5 not MACH 4A5.  I also wondered about
there being both a TQFP44 and TQFP48 package, but I get it now I see
the pad spacing is different.

Thanks much !

-rajeev-

lb.edc@telenet.be wrote:
> Hi Rajeev,
>
> ispLEVER starter version is also free of charge - so no problem there.
> As for the 5V tolerance, you can use the MACH4A5. This family starts
> from 32MC's up to 256MC's. Maybe an ispGAL22V10 can do the job for you
> as well. Gives you isp, so no need for a programmer!
> 
> Regards,
> 
> Luc

<...>


Article: 108734
Subject: Re: problems with IOSTANDARD
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 15 Sep 2006 14:29:40 -0500
Links: << >>  << T >>  << A >>


Martin Geisse wrote:

> Hi to all,
>
> I'm trying to set the output voltage level of a Virtex 2 pro using the
> IOSTANDARD constraint, but it doesn't work.
>
> More exactly, I'm using the XUP Virtex-II Pro Development System (an
> evaluation board) by Xilinx. For an application, I need the FPGA to
> output 3.3 V signals on the left low-speed expansion connector. I have
> tried to achieve this by placing the following lines in my UCF file
> (using one of the signals as an example):
>
> NET "camera_sio_d" LOC = "U3";
> NET "camera_sio_d" IOSTANDARD = LVTTL;
>
> However, the FPGA outputs 2.5 V for digital 1 (0 V for digital 0),
> measured with no load on the signal.

What is the power supply to the Vccext on that bank?  If it is 2.5 V,
you can play with the IO spec all you want, there's no way it can produce
3.3 V.  You may have to change a regulator, move jumpers, or whatever
to get 3.3 V to that bank's power supply.

Jon


Article: 108735
Subject: Re: Spartan3 driving mosfets
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 15 Sep 2006 14:33:23 -0500
Links: << >>  << T >>  << A >>


John Larkin wrote:

>I've got some DACs that I'd like to switch gain ranges on, and it
>turns out I can do it nicely using a single 2N7002 (sot23 n-channel
>mosfet) to switch a resistor to ground in each reference circuit. So
>I'd like to turn each 7002 on and off from a pin on an XC3S400. But
>3.3 volts is a marginal high for this fet... 4 volts looks safe.
>
>So, how about running Vccio a bit high, 3.5 maybe, and adding an
>external pullup resistor to +5. If I tristate the pin, I should
>forward-bias the upper esd diode and get 4.2 roughly, right? I'm
>thinking maybe a half milliampere or so pullup current. Doing this 8
>times only dumps 4 mA into the Vccio rail, no hazard there.
>
>  
>
You could also use a voltage divider circuit.  A series resistor between the
FPGA and the FET's gate, and a pull-up resistor to a higher voltage.
This would get you 4 or 5 V for the high, and 2.5 V or less for the low,
depending on the values selected.  As long as you don't need fast switching
the resistors can be fairly high values.

Jon


Article: 108736
Subject: Re: Fusion
From: "Brian" <brian.rasmussen80@gmail.com>
Date: 15 Sep 2006 12:38:35 -0700
Links: << >>  << T >>  << A >>
Hi

We are two students doing our bachelor project with an Actel Fusion
FPGA (AFS600 FG256). We have some problems concerning the A/D-converter
part of the FPGA. Does any of you have some tips to get started with
the A/D-converter in ViewDraw (the schematic tool)? We just got some
errors after making the modules with SmartGen.

Any help or hints would be appreciated.

Best regards

Kim Lyngaas and Brian Rasmussen

Antti wrote:
> Eli Hughes schrieb:
>
> > Antti wrote:
> > > Eli Hughes schrieb:
> > >
> > >
> > >>Does anyone know if ANY of the Actel fusion devices are available for
> > >>purchase?
> > >>
> > >>-Eli
> > >
> > >
> > > I received some PQ208 fusion chips over 6 weeks ago already.
> > > so I assume the answer is yes.
> > >
> > > Antti
> > >
> >
> >
> > Where did you order? I just called avnet and they said 6-month lead
> > time.   You want to sell any of yours??
> >
> > -Eli
>
> please contact me in private.
> I have an interesting project, and I may have some
> funding in terms of FPGA silicon, eval boards.
> 
> Antti


Article: 108737
Subject: Re: USB programming cables
From: google@gornall.net
Date: 15 Sep 2006 12:50:39 -0700
Links: << >>  << T >>  << A >>

Paul wrote:
> Digilent sells a USB JTAG cable.  The downside is it isnt compatible
> with Xilinx drivers, so you have to download and use the digilent load
> software.  This adds an extra step to the process, although ExPort (the
> digilent software) will download the BIT file into the FPGA fine, you
> have to take some additional steps to get an SVF file out of your MCS
> file for the PROM, the load the PROM from the digilent software from
> the SVF.
>
>
> John_H wrote:
> > I've been using the Xilinx Platform Cable USB for some time.  They now have
> > a second generation out there with lower power *and* is lead free.  I only
> > wish I could have multiple USBs connected at once since my Xilinx Spartan3E
> > starter kit board has a "built-in" platform USB cable that just needs a
> > standard USB cable to connect to my system.  So nice.

Cheers, both :-)

I've ordered one of the Xilinx USB ones. $150 for a cable seems ...
overkill ... but I guess it'll work with just about all the devices I
use from now on (still waiting for the Darnaw1 :-) Anything for a
simple life :-)

Simon.


Article: 108738
Subject: Parallel P&R
From: google@gornall.net
Date: 15 Sep 2006 12:58:10 -0700
Links: << >>  << T >>  << A >>
Anyone know if the P&R tools are multi-threaded ? And, if they're not,
whether there are any plans to make them so ? Even if it's just the
multi-pass tools running in parallel, it could be an advantage...

All the new Mac Pro's (which can also run Windows & Linux) are
quad-core, and the new chips due from Intel in December are
quad-core-on-a-die, making the machines 8-core... It sure would be nice
to harness all that power... You don't need a Mac, btw, Dell sell
just-as-capable computers, but the Mac is just cheaper :-)

Simon


Article: 108739
Subject: Re: Parallel P&R
From: "John_H" <newsgroup@johnhandwork.com>
Date: Fri, 15 Sep 2006 20:13:36 GMT
Links: << >>  << T >>  << A >>
On solaris (and probably linux) you can set up a node file - just a list of 
hosts - for multi-pass place & route that will run a separate P&R job on 
each host.  When I was working with this, I understood you couldn't specify 
multiple cores for one host without "fooling" the node selection by 
permutating upper and lower case for the same spelling to make it appear as 
different hosts.

As for Windows... ?


<google@gornall.net> wrote in message 
news:1158350290.111061.285470@m73g2000cwd.googlegroups.com...
> Anyone know if the P&R tools are multi-threaded ? And, if they're not,
> whether there are any plans to make them so ? Even if it's just the
> multi-pass tools running in parallel, it could be an advantage...
>
> All the new Mac Pro's (which can also run Windows & Linux) are
> quad-core, and the new chips due from Intel in December are
> quad-core-on-a-die, making the machines 8-core... It sure would be nice
> to harness all that power... You don't need a Mac, btw, Dell sell
> just-as-capable computers, but the Mac is just cheaper :-)
>
> Simon



Article: 108740
Subject: Re: microblaze lwip
From: "Alan Nishioka" <alan@nishioka.com>
Date: 15 Sep 2006 13:24:29 -0700
Links: << >>  << T >>  << A >>
u_stadler@yahoo.de wrote:
> as i posted bevore in the mms file config_sema=true is set. i rebuilt
> the libraries and still the same.

Oops, didn't re-read your original message.

You're missing config_time = true

See oslib_rm.pdf page 23 where the notes for the sem_timedwait()
function say you need to define this.

Alan Nishioka


Article: 108741
Subject: Re: upgrading firmware on stratix 2 without NIOS IDE
From: "Jeff Johnson" <jeffjohnsonce@gmail.com>
Date: 15 Sep 2006 14:14:50 -0700
Links: << >>  << T >>  << A >>

David Ashley wrote:
> Jeff Johnson wrote:
> > I am writing a firmware application that allows the verilog hardware on
> > the stratix 2 board to communicate via rs232 to a C# application.  I
> > would like to add the functionality into the C# app to upgrade the
> > firmware on the board, as new functions become available.  I'd like to
> > be able to send a flash file from PC to the board, store it to flash
> > and have the new version load on reset.
> >
> >
> > ANY INFORMATION is GOOD INFORMATION
> >
> > Jeff
> >
>
> Was there a question in there?
>
> Here's some information that might be useful:
> My shoe size is 12.:)
>
> Your idea sounds perfectly reasonable.
>
> -Dave
>
> --
> David Ashley                http://www.xdr.com/dash
> Embedded linux, device drivers, system architecture

so the question is........i think.......how do you reformat the output
of the NIOS IDE output files so they can be saved to flash and
successfuilly rebooted.


Jeff
size 11....DOH! got me again


Article: 108742
Subject: Re: microblaze lwip
From: "Vasanth Asokan" <nospam@xilinx.com>
Date: Fri, 15 Sep 2006 14:31:47 -0700
Links: << >>  << T >>  << A >>
You need to enable "time" features.

Turn config_time = true in the Xilkernel configuration.


<u_stadler@yahoo.de> wrote in message 
news:1158341293.912775.209800@d34g2000cwd.googlegroups.com...
> as i posted bevore in the mms file config_sema=true is set. i rebuilt
> the libraries and still the same.
> 



Article: 108743
Subject: Re: USB programming cables
From: "zcsizmadia@gmail.com" <zcsizmadia@gmail.com>
Date: 15 Sep 2006 15:50:16 -0700
Links: << >>  << T >>  << A >>
I have a open-source cableserver which works with Impact. Today I've
just finished to implement the Digilent JTAG-USB support in it. This
weekend I will upload the 0.2 version, which will have the digilent
support.

The digilent software doesn't support all the Xilinx devices and very
slow with Platform Flash.

www.sourceforge.com/projects/xilprg

Regards,

Zoltan

Paul wrote:
> Digilent sells a USB JTAG cable.  The downside is it isnt compatible
> with Xilinx drivers, so you have to download and use the digilent load
> software.  This adds an extra step to the process, although ExPort (the
> digilent software) will download the BIT file into the FPGA fine, you
> have to take some additional steps to get an SVF file out of your MCS
> file for the PROM, the load the PROM from the digilent software from
> the SVF.
>
>
> John_H wrote:
> > I've been using the Xilinx Platform Cable USB for some time.  They now have
> > a second generation out there with lower power *and* is lead free.  I only
> > wish I could have multiple USBs connected at once since my Xilinx Spartan3E
> > starter kit board has a "built-in" platform USB cable that just needs a
> > standard USB cable to connect to my system.  So nice.
> >
> >
> > "Simon" <news@gornall.net> wrote in message
> > news:2006091508283364440-news@gornallnet...
> > > So, having bought the V4FX-12 kit from NuHorizons, it arrived with a
> > > parallel-port JTAG cable. Normally I'd be just *fine* with this, but today
> > > my new quad-xeon Mac-pro arrives, and I bought that specifically to get
> > > some oomph in P&R (running linux using "parallels", of course).
> > >
> > > The mac doesn't have a parallel port. Ahhh. Is there a USB programming
> > > cable suitable for the FX-12 ? A fallback plan is to do most of the work
> > > on the Mac, but have a mini-itx machine next to it just for programming -
> > > the itx machine *does* have a // port, but it's woefully underpowered for
> > > any serious work on it...
> > >
> > > Ideas gratefully received :-)
> > >
> > > Simon
> > >


Article: 108744
Subject: Re: Spartan3 driving mosfets
From: "PeteS" <PeterSmith1954@googlemail.com>
Date: 15 Sep 2006 15:56:47 -0700
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> John Larkin wrote:
>
> >I've got some DACs that I'd like to switch gain ranges on, and it
> >turns out I can do it nicely using a single 2N7002 (sot23 n-channel
> >mosfet) to switch a resistor to ground in each reference circuit. So
> >I'd like to turn each 7002 on and off from a pin on an XC3S400. But
> >3.3 volts is a marginal high for this fet... 4 volts looks safe.
> >
> >So, how about running Vccio a bit high, 3.5 maybe, and adding an
> >external pullup resistor to +5. If I tristate the pin, I should
> >forward-bias the upper esd diode and get 4.2 roughly, right? I'm
> >thinking maybe a half milliampere or so pullup current. Doing this 8
> >times only dumps 4 mA into the Vccio rail, no hazard there.
> >
> >
> >
> You could also use a voltage divider circuit.  A series resistor between the
> FPGA and the FET's gate, and a pull-up resistor to a higher voltage.
> This would get you 4 or 5 V for the high, and 2.5 V or less for the low,
> depending on the values selected.  As long as you don't need fast switching
> the resistors can be fairly high values.
>
> Jon

But amongst all this John faces the standard hardware design issue:
cost. A 2N7002 is 3 cents and thus easy to drop in by the 10s of units
(layout costs aside). As to a voltage divider, I don't trust a FET to
be off unless it's pulled to ground (it's actually in a sub-threshold
region otherwise with a very undefined [generally] drain-source
resistance) so I would not personally countenance that.

Much depends on the cost sensitivity of John's product. In some cases,
one can justify a full solution, in others one can not (and some
vendors would do well to learn that lesson).

Amusingly, on the subject of vendors and cost, I was comparing a MAX
device against it's second source at TI today: MAX wants $3.11, TI
wants $0.74. Hmm.

Cheers

PeteS


Article: 108745
Subject: Re: upgrading firmware on stratix 2 without NIOS IDE
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Fri, 15 Sep 2006 16:01:31 -0700
Links: << >>  << T >>  << A >>
Jeff Johnson wrote:
> so the question is........i think.......how do you reformat the output
> of the NIOS IDE output files so they can be saved to flash and
> successfuilly rebooted.

Well I don't know Verilog, C# or NIOS IDE so I can't help.
But at least now someone else will know what you need. :)

-Dave

-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 108746
Subject: http://www.srisc.com ?
From: ziggy <ziggy@fakedaddress.com>
Date: Fri, 15 Sep 2006 19:42:24 -0400
Links: << >>  << T >>  << A >>
Ok, so a link to these people came across my mail box today. and its 
supposedly a Open Source 64bit sparc core.. 

Anyone that has seen this before want to comment?

Oh, and the little piece of hardware they show on their pages, anyone 
know what that is and where it came from?

Article: 108747
Subject: Re: Spartan3 driving mosfets
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 15 Sep 2006 16:52:24 -0700
Links: << >>  << T >>  << A >>
On 15 Sep 2006 15:56:47 -0700, "PeteS" <PeterSmith1954@googlemail.com>
wrote:

>Jon Elson wrote:
>> John Larkin wrote:
>>
>> >I've got some DACs that I'd like to switch gain ranges on, and it
>> >turns out I can do it nicely using a single 2N7002 (sot23 n-channel
>> >mosfet) to switch a resistor to ground in each reference circuit. So
>> >I'd like to turn each 7002 on and off from a pin on an XC3S400. But
>> >3.3 volts is a marginal high for this fet... 4 volts looks safe.
>> >
>> >So, how about running Vccio a bit high, 3.5 maybe, and adding an
>> >external pullup resistor to +5. If I tristate the pin, I should
>> >forward-bias the upper esd diode and get 4.2 roughly, right? I'm
>> >thinking maybe a half milliampere or so pullup current. Doing this 8
>> >times only dumps 4 mA into the Vccio rail, no hazard there.
>> >
>> >
>> >
>> You could also use a voltage divider circuit.  A series resistor between the
>> FPGA and the FET's gate, and a pull-up resistor to a higher voltage.
>> This would get you 4 or 5 V for the high, and 2.5 V or less for the low,
>> depending on the values selected.  As long as you don't need fast switching
>> the resistors can be fairly high values.
>>
>> Jon
>
>But amongst all this John faces the standard hardware design issue:
>cost. A 2N7002 is 3 cents and thus easy to drop in by the 10s of units
>(layout costs aside). As to a voltage divider, I don't trust a FET to
>be off unless it's pulled to ground (it's actually in a sub-threshold
>region otherwise with a very undefined [generally] drain-source
>resistance) so I would not personally countenance that.
>
>Much depends on the cost sensitivity of John's product. In some cases,
>one can justify a full solution, in others one can not (and some
>vendors would do well to learn that lesson).
>
>Amusingly, on the subject of vendors and cost, I was comparing a MAX
>device against it's second source at TI today: MAX wants $3.11, TI
>wants $0.74. Hmm.
>
>Cheers
>
>PeteS

Grumble, snarl, I guess I'll use an FDV301 like Larry suggests...
somebody else down the hall has just selected that same part for
another board. Damned things cost 9 cents!

Roger the Maxim parts; they're expensive, but the good news is that
you can't get them, so you save a lot of money.

John


Article: 108748
Subject: Re: XIlinx Spartan 2E stuck in configuration mode
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 15 Sep 2006 17:09:48 -0700
Links: << >>  << T >>  << A >>
On Fri, 15 Sep 2006 07:50:54 -0700, Austin Lesea <austin@xilinx.com>
wrote:

>False Rumor,
>
>We still require signal integrity to be correct, and have no plans to
>try to deal with bad engineering.
>

Whose side are you on? Do you *prefer* your FPGAs to not configure, as
some sort of punishment for crosstalk? 

CCLK is often bit-banged from a uP port and bussed to multiple
devices.  Lately it requires serious added drivers/buffers and
termination to be reliable with the faster FPGAs. Given a "slow" (say,
5 ns) risetime, the noise margin on Spartan3's is down in the
millivolts. Since you really can't clock these things above 20-25 MHz
in most situations, why use a gigahertz clock buffer on this pin?

John



Article: 108749
Subject: System Generator Bug
From: "Kuan Zhou" <kuan.zhou@unh.edu>
Date: Fri, 15 Sep 2006 20:17:02 -0400
Links: << >>  << T >>  << A >>
Hi,

    I found a bug inthe System Generator 8.2i. Every time when I click on 
the DSP block under Xilinx Reference Blockset in Simulink, i got a lot of 
warnings as follows:

Warning: When displaying: "xrbsDSP_r4/m-channel n-tap Transpose FIR Filter", 
the expression "ports_in(1)" could not be evaluated.  Check that the 
parameter entries and variables used in the Initialization command are valid 
MATLAB expressions.
> In load_system at 45
  In 
D:\MATLAB\R2006a\toolbox\xilinx\sysgen\bin\xlSetGUIXMLFromMaster.p>xlSetGUIXMLFromMaster 
at 4
  In 
D:\MATLAB\R2006a\toolbox\xilinx\sysgen\bin\xlBlockLoadCallback.p>xlBlockLoadCallback 
at 20
  In load_system at 45
  In 
D:\MATLAB\R2006a\toolbox\xilinx\sysgen\bin\xlProcBlockUpdate.p>xlProcBlockUpdate 
at 2
  In 
D:\MATLAB\R2006a\toolbox\xilinx\sysgen\bin\xlBlockLoadCallback.p>xlBlockLoadCallback 
at 71
  In load_system at 45
  In 
D:\MATLAB\R2006a\toolbox\xilinx\sysgen\bin\xlSetGUIXMLFromMaster.p>xlSetGUIXMLFromMaster 
at 4
  In 
D:\MATLAB\R2006a\toolbox\xilinx\sysgen\bin\xlBlockLoadCallback.p>xlBlockLoadCallback 
at 20
Warning: When displaying: "xrbsDSP_r4/m-channel n-tap Transpose FIR Filter", 
the expression "ports_in(2)" could not be evaluated.  Check that the 
parameter entries and variables used in the Initialization command are valid 
MATLAB expressions.


    I use Xilinx ISE 8.2i and did all the software update. I am using the 
MATLAB 7.2.0.232. And I also did all the update. The simulink version is 
6.4.1. The windows XP I am using is Version 5.1 with the Build of 2600 and 
SP2. Java version is 1.5.0 with Sun.

    Can anybody tell me how to remove these warning messages? I am sure this 
is a bug.

Kuan 





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