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Messages from 10900

Article: 10900
Subject: Advance Program.: 8th WS on Field-Programmable Logic FPL'98
From: abakus@informatik.uni-kl.de (Ulrich Nageldinger [Inf.])
Date: 29 Jun 1998 11:44:04 GMT
Links: << >>  << T >>  << A >>

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                          F P L  '98
 
      E I G H T H  I N T E R N A T I O N A L  W O R K S H O P
 
           FIELD PROGRAMMABLE LOGIC AND APPLICATIONS

     (http://xputers.informatik.uni-kl.de/FPL/index_fpl.html)


                        Advance Program
                        ===============
 
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
_|                                                                _|
_|       August 31 - September 3, 1998  (Monday - Thursday)       _|
_|                                                                _|
_|                      Tallinn, Estonia                          _|
_|                                                                _|
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Aim: From tinkertoy to parallel computing paradigm 
====
The methodology of reconfigurable circuits and systems is evolving 
from tinkertoy approach to an:
 Innovative Parallel Computing Paradigm
which combines computing in time with computing in space. The aim of
this workshop is to bring together workers from throughout the world
for a wide ranging discussion of all forms of field programmable 
logic, particularly field programmable gate arrays and complex 
programmable logic devices, and their applications. It is intended 
to discuss the increasing range of device types, industrial 
applications, advanced design tool development, research 
applications, novel system architectures and educational 
experiences. 
The workshop will include regular presentations, posters and 
discussion sessions, and it is expected that most of the delegates 
will wish to make some contribution to one or more of these. The 
workshop is the eighth in a series of workshops which were held in 
Oxford (1991, 1993 and 1995), Vienna (1992), Prague (1994), 
Darmstadt (1996) and London (1997). 


The following program is subject to change without notification.
====================================================================
Sunday, Aug. 30
====================================================================
--------------------------------------------------------------------
20.00 Informal Gathering and Registration at the Hotel Viru (lobby)
--------------------------------------------------------------------

====================================================================
Monday, Aug. 31
====================================================================
--------------------------------------------------------------------
8.00 - 9.00 Registration at Tallinn National Library
--------------------------------------------------------------------
9.00 - 9.20 Opening Session
--------------------------------------------------------------------
9.20 - 10.20 Keynote
--------------------------------------------------------------------
V.Milutinovic, University of Belgrade:
Key Issues in Reconfigurable Computing
--------------------------------------------------------------------
10.20 - 10.35 Coffee Break
--------------------------------------------------------------------
10.35 - 12.15 Session 1: Design Methods
--------------------------------------------------------------------
D.Robinson, P.Lysaght, G.McGregor, U Strathclyde:
New CAD Framework Extends Simulation of Dynamically Reconfigurable 
Logic

W.Luk, S.McKeever, IC London:
Pebble: A Language For Parametrised and Reconfigurable Hardware 
Design

V.Sklyarov, R.Sal Monteiro, N.Lau, A.Melo, A.Oliveira, K.Kondratjuk,
Aveiro U:
Integrated Development Environment for Logic Synthesis of Digital 
Circuits Based on Dynamically Reconfigurable FPGAs

R.Hartenstein, M.Herz, F.Gilbert, U Kaiserslautern:
Designing for the Xilinx XC6200 FPGAs

--------------------------------------------------------------------
12.15 - 13.30 Lunch
--------------------------------------------------------------------
13.30 - 15.10 Session 2: General Aspects
--------------------------------------------------------------------
J.Becker, A.Kirschbaum, F.-M.Renner, M.Glesner, TU Darmstadt:
Perspectives of Reconfigurable Computing in Research, Industry and
Education

G.Brebner, U Edinburgh:
Field-Progammable Logic: Catalyst for New Computing Paradigms

W.Luk, NShirazi, P.Y.K.Cheung, IC London:
Run-time management of partially-reconfigurable designs

M.Platzner, G.De Micheli, Stanford U:
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware

--------------------------------------------------------------------
15.10 - 15.30 Coffee Break
--------------------------------------------------------------------
15.30 - 17.10 Session 3: Prototyping / Simulation
--------------------------------------------------------------------
J.Stohmann, K.Harbich, M.Olbrich, E.Barke, U Hannover:
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping

H.Krupnova, G.Saucier, INP Grenoble:
A Knowledge-Based System for Prototyping on FPGAs

R.Macketanz, W.Karl, TU Munich:
JVX - A Rapid Prototyping System Based on Java and FPGAs

J.Shetler, B.Hemme, C.Yang, C.Hinsz, Cal Poly:
Prototyping New ILP Architectures Using FPGAs

--------------------------------------------------------------------
18.30 Reception at Tallinn Town Hall
--------------------------------------------------------------------

====================================================================
Tuesday, Sep. 1
====================================================================
--------------------------------------------------------------------
8.30 - 10.10 Session 4: Development Methods
--------------------------------------------------------------------
Samary Baranov, Ben Gurion U Negev:
CAD System for ASM and FSM Synthesis

J.M.Emmert, A.Randhar, D.Bhatia, U Cincinnati:
Fast Floorplanning for FPGAs

M.Renovell, J.M.Portal, J.Figueras, Y.Zorian, LIRMM-UM2:
SRAM-Based FPGAs: A Fault Model for the Configurable Logic Modules

G.Haug, W.Rosenstiel, FZI Karlsruhe:
Reconfigurable Hardware as Shared Resource in Multipurpose Computers

--------------------------------------------------------------------
10.10 - 10.35 Coffee Break
--------------------------------------------------------------------
10.35 - 11.50 Session 5: Accelerators
--------------------------------------------------------------------
S.Robinson, M.Caffrey, M.Dunham, LANL
Reconfigurable Computer Array: The Bridge Between High Speed 
Sensors and Low Speed Computing

W.Luk, P.Andreou, N.Shirazi, D.Siganos, IC London:
A Reconfigurable Engine for Real-Time Video Processing

F.-M.Renner, J.Becker, M.Glesner, TU Darmstadt:
An FPGA Implementation of a Magnetic Bearing Controller for 
Mechatronic Applications

--------------------------------------------------------------------
11.50 - 13.05 Session 6: System Architectures
--------------------------------------------------------------------
R.Hartenstein, M.Herz, T.Hoffmann, U.Nageldinger, U Kaiserslautern:
Exploiting contemporary memory techniques in reconfigurable 
accelerators

A.Donlin, U Edinburgh:
Self Modifying Circuitry - A Platform for Tractable Virtual 
Circuitry

K. GajjalaPurna, K.Simha, D.Bhatia, U Cincinnati:
REACT: Reactive Environment for Runtime Reconfiguration

--------------------------------------------------------------------
13.05 - 14.20 Lunch
--------------------------------------------------------------------
14.20 - 16.00 Session 7: Applications
--------------------------------------------------------------------
S.Charlwood, P.James-Roxby, U Birmingham:
Evaluation of the XC6200-series architecture for cryptographic applications

A.Zakerolhosseini, P.Lee, E.Horne, U Kent:
An FPGA based object recognition machine

G.Acher, W.Karl, M.Leberecht, TU Munich:
PCI-SCI Protocol Translations: Applying Microprogramming Concepts to FPGAs

T.Callahan, J.Wawrzynek, UC Berkeley
Instruction-Level Parallelism for Reconfigurable Computing

--------------------------------------------------------------------
14.20 - 15.35 Session 8: Poster Introduction (parallel to S.7)
--------------------------------------------------------------------
15.35 - 16.20            Poster Exhibition (partially par. to S.7)
--------------------------------------------------------------------
N.L.Miller, S.F.Quigley, U Birmingham:
A Novel Field Programmable Gate Array Architecture for high speed
arithmetic processing

D.MacVicar, S.Singh, XILINX:
Accelerating DTP with Reconfigurable Computing Engines

C.N.Ojeda-Guerra, R.Esper-Chain, M.Estupinan, A.Suarez, 
U Las Palmas:
Hardware Mapping of a Parallel Algorithm for Matrix-Vector 
Multiplication

G.Brebner, U Edinburgh:
An Interactive Datasheet for the Xilinx XC6200

N.Woolfries, P.Lysaght, S.Marshall, G.McGregor, D.Robinson, 
U Strathclyde:
Fast Adaptive Image Processing in FPGAs using Stack Filters

S.Sawitzki, A.Gratz, R.Spallek, U Dresden:
Increasing Microprocessor Performance with Tightly-Coupled 
Reconfigurable Logic Arrays

N.Bergmann, P.Sutton, Queensland U:
A High-Performance Computing Module for a Low Earth Orbit Satellite 
using Reconfigurable Logic

S.Yamagiwa, M.Ono, T.Yamazaki, P.Kulkasem, M.Hirota, K.Wada, 
U Tsukuba:
Maestro-Link: A High Performance Interconnect for PC Cluster

T.Shiozawa, K.Oguri, K.Nagami, H.Ito, R.Konishi, N.Imlig, NTT:
A Hardware Implementation of Constraint Satisfaction Problem Based 
on New Reconfigurable LSI Architecture

P.Merino, J.Lopez, M.Jacome, U Politecnica de Madrid:
A Hardware Operating System for Dynamic Reconfiguration of FPGAs

E.Cerro-Prada, P.B.James-Roxby, U Birmingham:
High speed low level image processing on FPGAs using distributed 
arithmetic

T.-T.Do, H.Kropp, C.Reuter, P.Pirsch, U Hannover:
A Flexible Implementation of High-Performance FIR Filters on Xilinx 
FPGAs

I.Vassanyi, U Veszprem:
Implementing processor arrays on FPGAs

S.Holmstrom, K.Sere, Abo Akademi U:
Reconfigurable Hardware - A Study in Codesign

C.Ackad, TU Braunschweig:
Statechart-based HW/SW-Codesign of a Multi-FPGA-Board and a 
Microprocessor

--------------------------------------------------------------------
16.20 - 16.40 Coffee Break
--------------------------------------------------------------------
16.40 - 18.00 Session 9: Hardware/Software Codesign
--------------------------------------------------------------------
G.McGregor, D.Robinson, P.Lysaght, U Strathclyde:
A Hardware/Software Co-design Environment for Reconfigurable Logic 
Systems

K.Bondalapati, V.Prasanna, U of Southern California:
Mapping Loops onto Reconfigurable Architectures

S.Asaad, K.Warren, IBM T.J.Watson Research Center:
Speed Optimization of the ALR circuit using an FPGA with embedded 
RAM: A Design Experience

--------------------------------------------------------------------
19.30 Banquet at von Glehn's castle
--------------------------------------------------------------------

====================================================================
Wednesday, Sep. 2
====================================================================
--------------------------------------------------------------------
8.30 - 9.45 Session 10: System Development
--------------------------------------------------------------------
R.Kress, A.Pyttel, A.Sedlmeier, Siemens AG:
High-level Synthesis for Dynamically Reconfigurable HW/SW-Systems

N.McKay, S.Singh, XILINX:
Dynamic Specialisation of XC6200 FPGAs by Partial Evaluation

S.Guccione, XILINX:
Webscope: A Circuit Debug Tool

--------------------------------------------------------------------
9.45 - 10.00 Coffee Break
--------------------------------------------------------------------
10.00 - 11.40 Session 11: Algorithms on FPGAs
--------------------------------------------------------------------
D.Lavenier, Y.Saouter, IRISA-CNRS:
Computing Goldbach partitions using pseudo-random bit generator 
operators on a FPGA systolic array

P.Zhong, M.Martonosi, S.Malik, P.Ashar, Princeton U:
Solving Boolean Satisfiability with Dynamic Hardware Configurations

J.Põldre, M.Mandre, K.Tammemäe, Tallinn Technical U:
Modular exponentiator realization on FPGA

B.Feher, G.Szedo, TU Budapest:
Cost effective 2x2 inner product processors

--------------------------------------------------------------------
10.00 - 11.15 Session 12: Poster Introduction (parallel to S.11)
--------------------------------------------------------------------
11.15 - 12.00             Poster Exhibition (partially par. to S.11)
--------------------------------------------------------------------

A.Touhafi, W.F.Brissinck, E.F.Dirkx, U Brussel:
Simulation of ATM switches using Dynamically Reconfigurable FPGA's

T.Rissa, T.Mäkeläinen, J.Siirtola, J.Niittylahti, Tampere U:
Fast Prototyping Using System Emulators

A.Dandalis, V.Prasanna, U of Southern California:
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable 
Coarse-Grained Architectures

I.Lemberski, M.Ratniece, Riga Aviation U:
XILINX4000 Architecture-Driven Synthesis for Speed

V.Tomachev, Inst. of Eng. Cybernetics Belarus:
The PAL-implementation of Boolean function characterized by minimum 
delay

A.Abo Shosha, P.Reinhart, F.Rongen, Research Centre Jülich:
Reconfigurable PCI-Bus Interface (RPCI)

A.Trost, A.Zemva, B.Zajc, U Ljubljana:
Programmable Prototyping System for Image Processing

L.Palomar, T.Fukuda, E.Dadios, Nagoya U:
A VHDL Design of an Arithmetic Co-Processor to Implement the 
Kohonen's Self-Organizing (Feature) Map

J.Fischer, C.Müller, H.Kurz, TU Aachen:
A Co-Simulation Concept for an Efficient Analysis of Complex Logic 
Designs

A.Döring, W.Obelöer, G.Lustig, Med. U Lübeck:
Programming and Implementation of Reconfigurable Routers

M.Moure, U Vigo:
Virtual Instruments based on reconfigurable logic

C.Siemers, D.Möller, FH Westküste:
The >S<puter: Introducing a Novel Concept for Dispatching 
Instructions Using Reconfigurable Hardware

L.Lagadec, B.Pottier, U de Bretagne Occidentale:
A 6200 model and editor based on object technology

M.Eisenring, J.Teich, ETH Zuerich:
Interfacing Hardware and Software

J. Hwang, E. Dellinger, S. Mitra, S. Mohan, C. Patterson, R. Wittig,
XILINX:
Generating Layouts for Self-Implementing Modules

--------------------------------------------------------------------
12.00 - 13.00 Closing Session
--------------------------------------------------------------------
T.Maruyama, T.Funatsu, T.Hoshino, U of Tsukuba:
A Field-Programmable Gate-Array System for Evolutionary Computation

T.Miyazaki, K.Shirakawa, M.Katayama, T.Murooka, A.Takahara, NTT:
A Transmutable Telecom System

Conclusions, Award Ceremony and Announcements

--------------------------------------------------------------------
14.00 Tour to Lahemaa National Park, visiting manors, and dinner 
      in Altja tavern
--------------------------------------------------------------------

====================================================================
Thursday, Sep. 3
====================================================================
--------------------------------------------------------------------
8.30 - 12.00 Tutorial at Tallinn Tech. University
--------------------------------------------------------------------
B. Radunovic, V. Milutinovic, Univ. Belgrade:
A Survey of Reconfigurable Computing Architectures, Part 1

--------------------------------------------------------------------
13.00 - 16.00 Tutorial at Tallinn Tech. University 
--------------------------------------------------------------------
B. Radunovic, V. Milutinovic, Univ. Belgrade:
A Survey of Reconfigurable Computing Architectures, Part 2

--------------------------------------------------------------------
====================================================================

Conference Venue: 
-----------------
     Tallinn National Library, Tõnismägi 2, EE0100 Tallinn, Estonia

Program Committee:
------------------
     Peter Athanas, Virginia Tech, USA 
     Samary Baranov, Ben Gurion U. Negev,Israel 
     Stephen Brown, U. of Toronto, CA 
     Klaus Buchenrieder, Siemens AG, FRG 
     Steven Casselman, VCC, USA 
     Bernard Courtois, INPG, Grenoble, France 
     Carl Ebeling, U. of Washington, USA 
     Norbert Fristacky, Slovak Technical U., SK 
     Manfred Glesner, TH Darmstadt, FRG 
     John Gray, Xilinx, UK 
     Herbert Grünbacher, Vienna U., Austria 
     Reiner Hartenstein, U. of Kaiserslautern, FRG 
     Brad Hutchings, Brigham Young U., UAS 
     Udo Kebschull, U. of Tübingen, FRG 
     Andres Keevallik, Tallinn Technical U., Estonia 
     Wayne Luk, Imperial College, UK 
     Patrick Lysaght, U. of Strathclyde, Scotland 
     Toshiaki Miyazaki, NTT Laboratories, Japan 
     Will Moore, Oxford U., UK 
     Wolfgang Nebel, U. of Oldenburg, FRG 
     Paolo Prinetto, Politecnico di Torino, Italy 
     Jonathan Rose, U. of Toronto, Canada 
     Zoran Salcic, U. of Auckland, New Zealand 
     Marc Shand, Digital Systems Research Center, USA 
     Stephen Smith, Altera, USA 
     Steve Trimberger, Xilinx, USA 

General Chairman: 
-----------------
     Prof. Andres Keevallik
     Tallinn Technical University
     Raja 15	
     Tallinn EE-0026	
     Estonia 	
     Phone: 	+372-6104440
     Fax: 	+372-6202246
     email:	 akeev@cc.ttu.ee
     http://www.ttu.ee/fpl98

Program Chairman: 
-----------------
     Prof. Reiner W. Hartenstein
     University of Kaiserslautern
     P. O. Box 3049	
     D-67653 Kaiserslautern	
     Germany	
     Phone: 	+49 631 205-2606
     Fax: 	+49 631 205-2640
     email:	hartenst@rhrk.uni-kl.de
     http://xputers.informatik.uni-kl.de/FPL/index_fpl.html



Article: 10901
Subject: Re: Q: I squared C on an FPGA
From: Rune Baeverrud <fpga@iname.com>
Date: Mon, 29 Jun 1998 14:41:38 +0200
Links: << >>  << T >>  << A >>
I see that some people have given you satisfactory answers to this question
already. If you would like to save some work and use a ready-made function,
I have provided a master function - fully tested and documented - written in
Altera AHDL and which I provide free of charge. You can find this at
http://www.acte.no/freecore - and follow the links to the "modules" section.

Regards,
Rune Baeverrud

Bryn Wolfe wrote:

> Has anybody tried to implement an I squared C interface on an FPGA? I am
> trying to implement it in an HDL, say VHDL, but find that my logic is
> excessive for such a simple serial interface. I figure I'm missing some
> key insight into making the logic much simpler.
>
> If anybody has attempted this or knows where I might look for
> information on this subject, please help.
>
> --
> Bryn Wolfe - Robotics Engineer
> Metrica TRAC Labs



Article: 10902
Subject: Re: Xilinx file compression
From: Jamie Lokier <spamfilter.june1998@tantalophile.demon.co.uk>
Date: 29 Jun 1998 13:56:22 +0100
Links: << >>  << T >>  << A >>
Three suggestions:

 - Gzip sounds a bit heavyweight for your need, but it does compress
   very well.  The space saved by better compression might offset the
   space needed for decompression code.  Most of the run-time memory
   needed can go in the same place as the decompressed file.  (Result
   of sliding window technique -- a little additional memory needed for
   huffman decoder though).

   The Gzip decompressor is quite feasible to code in assembler, if you
   use a pure sliding window and especially if you use fixed huffman
   code weights.  Take a look at inflate.c in the Gzip or libz
   distributions. You can ignore all the error checking and buffering
   and so forth -- the sliding window expander/huffman decoder are
   pretty short when you get down to the minimum required.

 - Forget Bzip, it uses tons of memory and is slow.  It's very good
   compression (better than Gzip), but inappropriate for this problem.

 - Sliding window like Gzip but without the Huffman coding -- just use a
   fixed no. of bits for offset and a length, perhaps with a few special
   cases.  This is very similar to run-length encoding, but has the big
   advantage that it is good at representing repeated patterns with
   occasional differences interleaved.  Sounds ideal for an FPGA
   bitstream, but I haven't tried it.

   You can modify Gzip to generate this data (by forcing fixed Huffman
   weights and changing the maximum offset).

   Like run-length encoding, the code to decompress this is simple, tiny
   and very fast.  And it doesn't need any extra RAM.

 - Take a look on the net for the LZO decompressors, specifically
   designed for fast, simple decompression in embedded & multimedia
   systems.  (LZO = Lempel-Ziv-Oppenheimer I think).

   The code includes several different compression schemes, compressors
   and decompressors for each.  Some of the decompressors are available
   in i386 assembly language as well as C -- if that's not your
   processor, the code may still give ideas on coding for your CPU.  As I
   said, these schemes are designed for fast & simple decompression.  I
   wouldn't be surprised if some of the schemes do just as well as Gzip
   on an FPGA bitstream.  I don't think they need extra RAM to run.

   Announcements for the code crop up on comp.os.linux.announce from
   time to time, so maybe Dejanews will help you find it.  (It's not
   Linux specific, I just happen to have seen announcements there).
   
Hope this helps,
-- Jamie
Article: 10903
Subject: Re: Free Computer (Read--Easy, No money down)
From: cfischer <cfischer@frontiernet.net>
Date: 29 Jun 1998 15:58:13 GMT
Links: << >>  << T >>  << A >>
Rickman wrote:
> 
> The best way to deal with such things is for everyone to reply to the
> sender. I have already sent him a message indicating what I think. If
> enough people did that, it would make the posting not worth the junk
> replies. In fact this guy took the time to send me a reply!
> 
> The real problem is with the spammers that are advertising a web site or
> post a long distance phone number. There is not much point in wasting
> your time and money to reply to those.
> 
> But if they post a valid email address, then they are fair game!
> 
> Terry L. Zumwalt wrote:
> >
> > Dear Jeremy,
> >
> > I have toagree with the other newsgroup members.  Your solicitation is not really
> > what this news group is about.  I my not sound as emotional as some of the other
> > responses but my feelings are in agreement.  Aside from the fact that I think
> > your pyramid scheme preys on people who are desperate and need better help than
> > you are offering.  Please respect the wishes of the newsgroup and leave your
> > advertisement off this thread.  I would be surprised if you get even one positive
> > response on this thread.
> >
> > Hope to never hear from you again.
> > Best Regards
> > Terry

I find it's useful to CC the reply to postmaster@hisdomain, and root@hisdomain.
If enough sysadmins get pissed off, maybe they will put a halt to this sh*t.
-- 

Chris Fischer                       cfischer@frontiernet.net
Owner, Coda Software, Limited
Article: 10904
Subject: Re: DAC Experience
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 29 Jun 1998 13:21:11 -0400
Links: << >>  << T >>  << A >>
Goran.Bilski@enator.se wrote:
> 
> I'm a senior consultant from Sweden who attended to the 35th DAC. I have
...snip...
> Before DAC, I had seen a press release that Altera was going to show the
> software that will come after MaxPlus2, and since I have been using MaxPlus2,
> I was interested in what they had improved. So I walked to their demo suite
> and stepped in and asked if I could see a demo. A man came towards me and and
> said 'NO It is only for special invited people' and then turned his back on
> me. I could do nothing but walk away. I'm still stunned about this attitude
> to an unknown customer; he didn't care to find out who I was or what I was
> doing. I might have been a customer who was going to buy thousands of their
> FPGAs, but they didn't care. If they had just asked who I was, and then said
> it is only for beta-site people and then asked me if I would like to become a
> beta-site, that would have been o.k. For crying out loud, he could have
> talked to me. If they had a good reason for not showing me the demo, I would
> have accepted it. But no, they didn't care. Then I thought it might be only
> this one guy with an attitude problem, so I walked to their booth again and
> asked the same question, and I was given the same answer and attitude.
> 
> So, if Altera is ignoring me I will start to ignore Altera. My company is
...snip...
> You may say that I'm acting like a 5-year old kid, and that may be true. I
> will ban Altera as long as I'm so disgusted with their attitude. I seldom get
> angry, but when I do I get real angry.
> 
> Since I'm a consultant I will use Altera only if my client says so, and if the
> design really fits Altera.
> Otherwise I will look for alternative architectures.
> 
> Göran Bilski
 
I feel your pain and I understand your response. There is no excuse for
the way you were treated. No salesman should ever be so rude to anyone,
even after finding out that the potential customer was a small dollar
account. 

As engineers we have very little control over the products and sales
approaches from the semiconductor companies. With the one exception: the
purchase order. This is the sole reason for the existance of the sales
force... sales. But then the PO is a powerful tool that should be used
very carefully. Just like a gun, it can do harm to the person using it
if not used carefully. 

Before you get Altera blacklisted with your company, you might try
approaching your local sales office to see if they are interested in
attempting to make up for the way you were treated. I have found that
when you reach the people who are responsible for making you happy, they
often will bend over backward to make up for some problem that was
caused by someone else. Salesmen really are people too, honest!

I have no connection with Altera. I don't even use their parts. So I
have no axe to grind either way. 

In fact, if you are serious about sharing your VHDL designs, I would be
very interested in the FIFO, the SHARC DSP link receiver/transmitter and
the synthesizable conversion between IEEE Float and Std_Logic, as well
as the behavior model for the SHARC DSP. I don't have an immediate need
for these, but I can see use for them in Xilinx Virtex parts in the
future. 

Thanks in advance.

If you want to email me, please don't use the reply address. Use the
address below.

-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10905
Subject: Re: I squared C on an FPGA
From: tom_curran@memecdesign_dot_com (tom curran)
Date: Mon, 29 Jun 1998 18:48:54 GMT
Links: << >>  << T >>  << A >>
Simple vs. Complicated for an I2C interface is all a matter of
implementation.  If you want a fully compliant and robust interface,
complete with bus arbitration, you will use much more than 20 CLB's.


---
Tom Curran
Memec Design Services -- Boston
url:    www.memecdesign.com
email:  tom_curran@memecdesign_dot_com
phone:  978.266.9193
fax:    978.266.9194
vm:     800.688.7718 x3603

Article: 10906
Subject: Re: Q: I squared C on an FPGA
From: tom_curran@memecdesign_dot_com (tom curran)
Date: Mon, 29 Jun 1998 18:51:44 GMT
Links: << >>  << T >>  << A >>
Simple vs. Complicated for an I2C interface is all a matter of
implementation.  If you want a fully compliant and robust interface,
complete with bus arbitration, you will use much more than 20 CLB's.


---
Tom Curran
Memec Design Services -- Boston
url:    www.memecdesign.com
email:  tom_curran@memecdesign_dot_com
phone:  978.266.9193
fax:    978.266.9194
vm:     800.688.7718 x3603

Article: 10907
Subject: Re: Xilinx Foundation simulator problem?
From: "Richard B. Katz" <rich.katz@gsfc.nasa.NOSPAM.gov>
Date: Mon, 29 Jun 1998 16:28:02 -0400
Links: << >>  << T >>  << A >>
does it run at room temp with a slightly slowed clock?

will it run at room temp with an elevated supply voltage?

rk

Philip Freidin wrote:

> Given that your device runs when cold (internal paths and logic run
> faster), but not at room temp, here are SOME options:
>
> CAE/Vendor issues:
> 1) The speed files are not correct
> 2) Back annotating speed info did not work correctly
> 3) The simulator isn't using the speed info correctly
> 4) The device is faulty
> 5) Your design is relying on a path that the speed file doesn't cover
>
> Your issue:
> 6) Asynchronous logic
> 7) Paths that depend on N cycles taking N-1 cycles and logic
>    can't handle occasional metastables
> 8) Timespec coverage is not complete
> 9) Multiple clock domains, using more than 1 clock signal rather than CE
> 10) External issue that depends on higher drive when device is cold.
>
> Let me write a little about (8)
>
> At the end of the trace report, it should indicate the percentage
> coverage of your time specs. It should be over 99%. (for some designs it
> is impossible to get 100% because of bugs in the way this coverage
> percentage is calculated).
>
> Your design should not rely on any default specs.
>
> you can run trace from the command line with the following command:
>
> ¦trce mychip.ncd mychip.pcf -v 100 -u -o mychip.twr >> mychip.log
>
> The -v says give verbose info on the worst 100 paths for each timespec.
> The report can be quite long.
>
> The -u says list unconstrained paths. These will be listed in the .twr
> file in a section titled:
>
> =========================================================
> Timing constraint: Unconstrained path analysis
>  293 items analyzed, 0 timing errors detected.
>  Minimum period is  13.289ns.
>  Maximum delay is  19.354ns.
> ---------------------------------------------------------
>
> yada yada yada
>
> This section will be ommitted if ALL paths are covered by either specs you
> entered, or default specs. Following this heading it will list (verbosely)
> the worst 100 unconstrained paths. Go find them, and add tspecs to cover
> them. Re-netlist, PAR, trce. Repeat till this section disappears, or the
> paths are not constrainable (due to bugs in the SW. There are a few that
> affect this section, but they are REALLY rare.)
>
> At the end of the .twr file, you need to see something like:
>
> Timing summary:
> ---------------
>
> Timing errors: 0  Score: 0
>
> Constraints cover 40047 paths, 0 nets, and 22452 connections (100.0%
> coverage)
>
> Good luck.
> Philip Freidin
>
> In article <35969ebb.5128088@news.dial.pipex.com> ems@see_sig.com (ems) writes:
> >
> >the silicon works fine when frozen. it fails after a couple of
> >minutes at room temperature (20C, no cooling, to be precise), at 5V
> >+/- 2%, on one tested device.
> >
> >note that i'm *not* (yet) claiming that there's a problem with the
> >simulator or the speed file. however, the failure is very specific,
> >and i'm sure, as far as i can be, that the simulator can't reproduce
> >it.
> >
> >evan (ems@nospam.riverside-machines.com)
> >



Article: 10908
Subject: Sr. Hardware Engineer?
From: jcain <jcain@connectix.com>
Date: Mon, 29 Jun 1998 17:44:57 -0800
Links: << >>  << T >>  << A >>
Hello,


Connectix - the market leader in the design and manufacture of tethered
video cameras- is looking to hire a Sr. Hardware Engineer.

 Experience:

At least 5 years of board level design experience with FPGA prototyping
is required as is knowledge of embedded microcontrollers and PCB layout
techniques. Working knowledge of an HDL/ASIC design process is also
required, in addition to an understanding of CCD and/or CMOS sensor
technology.

Contact:

Jerel Cain
Connectix Corporation
http://www.connectix.com
650-295-7257 (phone)
650-571-8541 (fax)
jcain@connectix.com

Article: 10909
Subject: Re: Xilinx file compression
From: "Manfred Kraus" <mkraus@xxcesys.com>
Date: Tue, 30 Jun 1998 11:56:20 +0200
Links: << >>  << T >>  << A >>

Steve schrieb in Nachricht <3596c0ed.1378542@news.netspace.net.au>...
>Hi
>
>We are currently running an embedded system with segmented Flash.
>This allows us to have a Boot code section and a Main code section.
...snip...
>And it brings the 40k file down to about 5k.  But I would like more
>compression!
...snip...
>Anyone got any ideas?
>
>Steve
>

Keep in mind:
As your XILINX Projects grows, your compression rate will go down !!
It is easy to compress an EXO-file of an almost empty device.

Manfred


Article: 10910
Subject: testing internal paths
From: Robert Peach <rpeach@gelac.mar.lmco.com>
Date: Tue, 30 Jun 1998 08:18:20 -0400
Links: << >>  << T >>  << A >>
Hi,

 I know that Boundry Scan will let me test the FPGA at the inputs and
outputs, but I would also like to be able to test internal paths.  What
are the tools and methods to test the internal paths of a PLD?

Robert Peach
Lockheed Martin Aeronautical Systems
Atlanta, GA
(770) 494-7587
rpeach@gelac.mar.lmco.com

Article: 10911
Subject: complete testing
From: Robert Peach <rpeach@gelac.mar.lmco.com>
Date: Tue, 30 Jun 1998 08:27:52 -0400
Links: << >>  << T >>  << A >>
Hi again,

 I want to add to my last question.  I would like to test the FPGA part
so that it demonstrates proper operation under all combinations and
permutations at the gates and pins of the device.  I know that for very
dense FPGAs that this is not possible as it would take to much time.  I
would like feedback on testing tools and methods that test an FPGA to a
degree that I can be confident that I will not get a failure such as
Latchup or SEU.  Nothing is 100%, but if you know some things that are
close I would appreciate hearing about it.
Thank you.

Robert Peach
Lockheed Martin Aeronautical Systems
Atlanta, GA
(770) 494-7587
rpeach@gelac.mar.lmco.com

Article: 10912
Subject: Spartan test-board
From: mlankenau@yahoo.com (Marcus Lankenau)
Date: Tue, 30 Jun 1998 14:09:10 GMT
Links: << >>  << T >>  << A >>
Hi!


I'm currently developing a very simple test board for the spartan
XCS05 (PLCC84 package). I connected  program (pin55), din (pin71) and
cclk (pin73) using a 74ls14 schmidt-triger with a prallelport
connector. Are these three signals all I need to programm the fpga in
slave mode (I'm a little confudes with the datasheed)? Wich kind of
output file should I generate (MCS, hex....) with F1.4 to download the
bitstream (I want to write a litle transfer-software on my own)???



thanks in advance 




Marcus Lankenau
Article: 10913
Subject: Re: complete testing
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 30 Jun 1998 10:33:16 -0400
Links: << >>  << T >>  << A >>
Robert Peach wrote:
> 
> Hi again,
> 
>  I want to add to my last question.  I would like to test the FPGA part
> so that it demonstrates proper operation under all combinations and
> permutations at the gates and pins of the device.  I know that for very
> dense FPGAs that this is not possible as it would take to much time.  I
> would like feedback on testing tools and methods that test an FPGA to a
> degree that I can be confident that I will not get a failure such as
> Latchup or SEU.  Nothing is 100%, but if you know some things that are
> close I would appreciate hearing about it.
> Thank you.
> 
> Robert Peach
> Lockheed Martin Aeronautical Systems
> Atlanta, GA
> (770) 494-7587
> rpeach@gelac.mar.lmco.com

Depends on what you mean.  By the context, I think you are saying you
want to do device testing independent of the design loaded in by the
user?  If this is the case, the degree of testing depends on the FPGA
type.  For an SRAM device, you can run a set of tests that will check
the device fairly thoroughly.  The manufacturer has some hooks in there
that permit him to do more complete testing than the user however.  If
it is a one time programmable, then you as a user are more or less out
of luck. Xilinx has an app note that breifly describes the reliability
and some of the production testing.  For more detail, I would suggest
you contact you vendor of choice.  The vendors have already performed a
fairly exhaustive set of tests, so under an NDA you might be able to use
their results to satisfy your needs or to set up additional testing.

If you are talking about testing your design, then it obviously depends
on the design.  You can make your design more resistant to SEU by
incorporating fault detection and correction in your logic. 
Controllability and observability of internal nodes will reduce the
number of test vectors you need to get acceptable coverage of the
design.  You can get some access through the readback pins on some
devices, but it is somewhat awkward to use.  If you have the space and
pins, add test access to the design.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

The Andraka Consulting Group is a digital hardware design firm
specializing in high performance FPGA designs for digital signal
processing, computing and control applications.
Article: 10914
Subject: ARM ASPIRE Board Beta Trial
From: dp11@my-dejanews.com
Date: Tue, 30 Jun 1998 15:02:52 GMT
Links: << >>  << T >>  << A >>
ARM Ltd has developed a PCI board comprising of an ARM based Micro-controller
and two Xilinx FPGAs which are available for user applications.

It is possible that there might be a spare place on the beta trial which will
take place over the next three months. If you are interested please read the
extra information below and email me as soon as possible.

Thanks
Dominic Plunkett
OptionExist Ltd
Cambridge

ASPIRE Beta Trial
==================

The ASPIRE beta trial aims to test and evaluate the ASPIRE board and software
packages that go with the board. The trial will run for three months, at the
end we will require a report. OptionExist Ltd have been appointed by ARM Ltd
to run the trial.

If you have a use for the board and kit beyond the 3 month trial, it will be
available at a discounted price.

Please could you give us an indication as to the likely applications and
which software packages you would require for the trial, and your experience
with similar products.

The ASPIRE Board
----------------

This ASPIRE development board was jointly developed between ARM Ltd and
Oxford University under the ASPIRE project. The board contains the following:

MicroController ( based on the ARM7TDMI). Clocked at 16MHz.

BOOTROM with the Angel Debug Monitor. JTAG ICE many also be used

1/2Mbyte of Flash Memory for the MicroController.

RS232 port

DRAM SIMM (4/16Mbytes)

System Controller (in an XC4013XL) which provides a DRAM controller, DMA
Controller, Interrupt controller and other glue logic functions

AMCC PCI chip which can directly DMA into/out of the DRAM via the system
controller

Selectable clock rates 4/8/16MHz. On board Crystal or PCI Clock.

2 x XC4013XL FPGA's for user Applications, programmed by the AT91

256K SSRAM directly connected to the FPGAs

External power connector for standalone applications

Many Expansion connectors

Software
--------

For the Trial we have arranged the following software to be available for
evaluation if you need it.

ARM Development Tool Version 2.11a (www.arm.com)

HandelC : Oxford University Hardware Compilation Group have developed a C
like language that can target the FPGA's. So it becomes very easy to develop
hardware in a software environment. Oxford University now have a spin off
company Embedded Solutions Ltd (www.embedded-solutions.ltd.uk).

Xilinx Alliance standard, needed for HandelC or possible Xilinx Foundation
which is needed for VHDL or HandelC. This software places and route the
designs for the FPGA's. (www.xilinx.com)

Reports
--------

We are looking for people who could make use of the board in the 3 months.
We would like monthly email reports about the board and the software. At
the end of the trial we will require a final report, this should cover:

What the board has been used for?
How easy was it to use?
Was the board suitable?
Do you have enough information?
Any problems you have had?
It is useful to develop a product or test software?
Do you know of any competing product?
What improvements would you like?

Dominic Plunkett
OptionExist

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 10915
Subject: Visiting Faculty / Post-Doctoral Fellow Positions
From: sds@cardinal.cs.wustl.edu (Stephen D. Scott)
Date: 30 Jun 1998 15:43:03 -0500
Links: << >>  << T >>  << A >>

               Computer Science and Engineering Department
                    University of Nebraska - Lincoln


Visiting Faculty / Post-Doctoral Fellow Positions
Computer Science and Engineering Department
University of Nebraska - Lincoln


Applications are invited for Visiting Faculty / Post-Doctoral Fellow
positions for one year to begin on August 17, 1998. Duties will include
undergraduate and/or graduate instruction and research.

Outstanding candidates with teaching and/or research experience in the
following areas are sought:

   * VLSI design, design automation, and systems architecture,
   * Database and information systems,
   * Software engineering and human-computer interaction,
   * Communications, networking, and distributed systems, and
   * Theory and algorithms.

Applicants at all levels of experience and with a Ph.D. in Computer Science,
Computer Engineering, or a closely related field are eligible. Salary is
negotiable and will be commensurate with qualifications and experience.

These positions are non-tenure leading. However, the CSE Department has
tenure-line vacancies and will be conducting searches during the coming
academic year. Applications by visiting faculty for tenure-line positions
will receive full consideration.

The CSE Department currently has 20 full-time faculty lines (with three
vacancies). The Department offers degrees programs both in computer science
and in computer engineering leading to BS, MS, and PhD degrees. The CSE
Department doctoral program recently was rated by the National Research
Council second highest in the Big 8 Conference. The faculty research
interests cover a wide range of topics in the defined focus areas of
communication theory & foundations, distributed systems, human-centered
software design, and visual information processing. Currently 100 students
are enrolled in the graduate program and 500 in the undergraduate program.
CSE Department faculty members are active participants in state-supported
research centers, including the Center for Communication and Information
Sciences, the Center for Technology Management and Information Science, the
Center for Advanced Land Management Information Technologies, the Center for
Biotechnology, and the Center for Infrastructure Research. Current funding
for research from external sources is over $2.7M. Funding for active
projects from the past year exceeded $800K with over $250K institutional
support for more than 30 projects. Further information about the Department
may be obtained from the web page at "http://cse.unl.edu/".

As the largest educational institution in the state, UNL has since its
founding in 1869 been a distinguished land grant institution. A member of
the American Association of Universities, UNL also is a Carnegie I Research
University and a member of the National Association of State Universities
and Land Grant Colleges. There are nine undergraduate colleges and a law
college as well as a graduate division granting degrees at the
baccalaureate, master's and doctoral levels. Approximately 24,000 students
matriculate annually. There are 32 doctoral programs, 63 master's programs,
130 undergraduate sequences and 14 pre-professional areas of study. The
colleges are: Agricultural Sciences & Natural Resources, Architecture, Arts
& Sciences, Business Administration, Engineering & Technology, Fine &
Performing Arts, Human Resources and Family Sciences, Journalism & Mass
Communications, Law, and Teachers.

Screening begins immediately and will continue until suitable candidates are
hired. Applicants should submit a letter of interest, a current CV and
arrange to have three professional references sent as soon as possible, to:

CSE Search Committee Chair
(c/o: Ms. Linda Endres)
University of Nebraska - Lincoln
Lincoln, Nebraska 68588-0115
Telephone: (402)-472-5001
FAX: (402)-472-7767
E-mail: endres@cse.unl.edu
WWW Site: http://cse.unl.edu

The University of Nebraska is committed to a pluralistic campus community
through Affirmative Action and Equal Opportunity and is responsive to the
needs of dual career couples. We assure reasonable accommodation under the
Americans with Disabilities Act.
-- 
Department of Computer Science                       Stephen D. Scott
Washington University, Campus Box 1045               sds@cs.wustl.edu
One Brookings Drive                     http://www.cs.wustl.edu/~sds/
St. Louis, MO  63130-4899                              (314) 935-4425
Article: 10916
Subject: Xlinx CPLD bitstream format
From: n4mwd@dont.spam.me.flinet.com
Date: Wed, 01 Jul 1998 01:50:35 GMT
Links: << >>  << T >>  << A >>

Does anybody have the Xilinx jedec fuse format for 9500 devices?  

TIA,



Dennis Hawkins
n4mwd@dont.spam.me.flinet.com
(Remove "dont.spam.me." from address before replying)

Do you want to know who has been calling you and hanging up when you answer the 
phone? Visit http://www.afn.org/~afn40110/telescum.htm to find out.


Article: 10917
Subject: ZERO NRE ASICs update
From: "kash johal" <kash@ix.netcom.com>
Date: 1 Jul 1998 02:33:50 GMT
Links: << >>  << T >>  << A >>
Check out our updated web-site at http://www.macrotechsemi.com.

We offer Zero NRE ASICs.

We can integrate RAM, ROM, CPU etc for designs up to 1M gates.

Our process is 0.35 Micron 3.3V 5V tolerant.

We will be updating soon with a detailed ASIC price estimator---look for
that soon.

Regards,

Kash
Article: 10918
Subject: ZER) NRE ASICS update
From: "kash johal" <kash@ix.netcom.com>
Date: 1 Jul 1998 02:35:52 GMT
Links: << >>  << T >>  << A >>
Check out our updated web-site at http://www.macrotechsemi.com.

We offer Zero NRE ASICs.

We can integrate RAM, ROM, CPU etc for designs up to 1M gates.

Our process is 0.35 Micron 3.3V 5V tolerant.

We will be updating soon with a detailed ASIC price estimator---look for
that soon.

Regards,

Kash

Article: 10919
Subject: Re: I squared C on an FPGA
From: "Austin Franklin" <darkroom2@ix.netcom.com>
Date: 1 Jul 1998 03:56:53 GMT
Links: << >>  << T >>  << A >>
tom curran <tom_curran@memecdesign_dot_com> wrote in article
<3597dfd3.593512078@mdsXboston>...
> Simple vs. Complicated for an I2C interface is all a matter of
> implementation.  If you want a fully compliant and robust interface,
> complete with bus arbitration, you will use much more than 20 CLB's.

We did it in 24 CLBs in a 3142A and it is fully compliant (what ever that
means...but it works with Dallas, National and Philips peripherals) and has
arbitration for multiple masters (and that works too).  So, it does depend
on how you implement it ;-)

Austin Franklin
darkroom@ix.netcom.com

Article: 10920
Subject: Re: I squared C on an FPGA
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Wed, 01 Jul 1998 12:21:07 GMT
Links: << >>  << T >>  << A >>
If you want a fully compliant I2C interface you can't do it in a
regular 5V FPGA at all.
The I2C spec says that SDA and SCL can not be loaded when the power is
removed from the chip.
The parasitic diode due to the P channel pullup transistor in regular
FPGA outputs makes this impossible.

Perhaps you could use a 3V FPGA with 5V tolerant I/Os.

This is not a problem if you only have one power supply, and
everything powers down at the same time.  Otherwise, you'll have to
live with "not quite fully compliant" I2C interfaces.

I recall that the license agreement with Philips says that the
interface can only be called I2C if it is fully compliant.

Just my $0.02 worth,
Allan.

On 1 Jul 1998 03:56:53 GMT, "Austin Franklin"
<darkroom2@ix.netcom.com> wrote:

>tom curran <tom_curran@memecdesign_dot_com> wrote in article
><3597dfd3.593512078@mdsXboston>...
>> Simple vs. Complicated for an I2C interface is all a matter of
>> implementation.  If you want a fully compliant and robust interface,
>> complete with bus arbitration, you will use much more than 20 CLB's.
>
>We did it in 24 CLBs in a 3142A and it is fully compliant (what ever that
>means...but it works with Dallas, National and Philips peripherals) and has
>arbitration for multiple masters (and that works too).  So, it does depend
>on how you implement it ;-)
>
>Austin Franklin
>darkroom@ix.netcom.com
>

Article: 10921
Subject: Re: Xilinx Foundation simulator problem?
From: ems@see_sig.com (ems)
Date: Wed, 01 Jul 1998 14:00:59 GMT
Links: << >>  << T >>  << A >>
nice summary - thanks. one of the few usenet messages i've ever
bothered to print.

evan

Article: 10922
Subject: Re: Xilinx Foundation simulator problem?
From: ems@see_sig.com (ems)
Date: Wed, 01 Jul 1998 14:05:46 GMT
Links: << >>  << T >>  << A >>
I've managed to get a bit further with this. I ran up the offending
simulation as a VHDL testbench, under ModelSim. The results now
are:

1   Real device - doesn't work, has a timing problem
2   Foundation simulation (and timing analyser) - reports no problems
3   ModelSim - reports a timing error.

This simulation is pretty simple - I write six 16-bit words
into the device and, some time later, I get a string of 12
processed bytes out. This part of the device is also pretty simple -
an input register loading a DPRAM, counters for the ram read and
write addresses, some muxes on the ram output feeding two
4-bit registers, which are then combined into an 8-bit output
register. There's no fancy clocking (everything, including the
DPRAM, from the main 15.6ns clock), but all the stages have clock
enables.

I can't duplicate the simulation exactly on the bench, but
the ModelSim failure does look very similar to the real device
failure - ocassional bad data at the output. According to
Modelsim, one of the DPRAM outputs ocassionally has a nasty
glitch on it. The Foundation simulation *doesn't* show this.
At the same time in the 2 simulations, Aldec reports a
stable high level on the appropriate bit, but Modelsim
reports a long (6ns) glitch (1 -> X -> 1).

Unfortunately, this isn't the end of the problem. The
functional VHDL simulation of the DPRAM produced by logiblox
couldn't produce this glitch (the inputs couldn't result
in the outputs). The simprim (timing) model is producing the
glitch, but I don't have enough of the VITAL sources
to work out why, and there's nothing obvious in the SDF
data which could result in a glitch with this timing.
I'll post the timing and the DPRAM ins/outs if anyone's
interested.

So, my current feeling is that the glitch found by Modelsim
isn't 'real', and isn't responsible for the real device's
failure, despite the similarity. It looks like a problem with the
simprim cell, and I've got this one with Xilinx at the moment.

Evan  (ems@nospam.riverside-machines.com)

Article: 10923
Subject: Power consumption question
From: Botond Kardos <Kardos.Botond@hu.innomed.NOSPAM>
Date: Wed, 01 Jul 1998 11:42:08 -0400
Links: << >>  << T >>  << A >>
Hi,
   I have a minor problem. Let's suppose I have a simple PCB, it
contains a SRAM based FPGA (Altera Flex 8K), an EPROM, a single LED and
some resistors and capacitors. I measure the current consumption of the
whole PCB. The FPGA smoothly boots up and does nothing, the LED shows
that the FPGA finished the boot-up procedure. Ideally the card takes up
about 1.5 mA. After RESET I can see the following on my multimeter:
   - the consumption is about 4 mA, and slightly growing.
   - after 15 seconds (!) or so the consumption reaches 7-8 mA, then
drops to 1.5 mA and stays constant.
   The same can be observed with a PCB that contains a Hitachi H8/300h
uC, an EPROM, a quartz and the LED. Current consumption is of course
higher, but it changes the same way as described above.
   I simply don't know what causes this phenomena (every unused pin is
configured for output). I've already asked mailto:sos@altera.com but
they didn't answer (although they used to).
   So if someone has ever met something similar, please let me know,
what's the reason for it.
   Thanx in advance, and cheers

   Botond

-- 
Botond Kardos  -  at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
      To get my real address just put the domain
      name in reverse order and remove 'nospam'.
      x@1.2.3 -> x@2.1
Article: 10924
Subject: Re: Power consumption question
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 01 Jul 1998 09:43:56 -0700
Links: << >>  << T >>  << A >>
Botond Kardos wrote:

>  After RESET I can see the following on my multimeter:
>    - the consumption is about 4 mA, and slightly growing.
>    - after 15 seconds (!) or so the consumption reaches 7-8 mA, then
> drops to 1.5 mA and stays constant.
>  

It has to be a floating node somewhere, inside the chip or outside.The
only phenomena with that kind of time constant are:
1.thermal and
2. floating nodes.
I think we can eliminate thermal problems, since heat causes the current
to go down ( in CMOS ). Floating nodes can lead to internal contention
and can thus draw a lot of current. Now the question is: Where is the
floating node?

Just my $0.02 worth.

Peter Alfke, Xilinx Applications



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1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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