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Messages from 10925

Article: 10925
Subject: Re: Power consumption question
From: "Paul Taylor" <p.taylor@ukonline.co.uk>
Date: Wed, 1 Jul 1998 22:43:44 +0100
Links: << >>  << T >>  << A >>
Try this:

Connect the output of a signal generator via a 47K resistor to the
tip of a scope probe, then probe all chip pins in turn.
If the pin is floating, you'll see the signal on the scope.

It's best to fit a pullup resistor, if one is needed, as most chips
can sink current better than source it.


Paul.



Peter Alfke wrote in message <359A6676.8D62D412@xilinx.com>...
>Botond Kardos wrote:
>
>>  After RESET I can see the following on my multimeter:
>>    - the consumption is about 4 mA, and slightly growing.
>>    - after 15 seconds (!) or so the consumption reaches 7-8 mA, then
>> drops to 1.5 mA and stays constant.
>>
>
>It has to be a floating node somewhere, inside the chip or outside.The
>only phenomena with that kind of time constant are:
>1.thermal and
>2. floating nodes.
>I think we can eliminate thermal problems, since heat causes the current
>to go down ( in CMOS ). Floating nodes can lead to internal contention
>and can thus draw a lot of current. Now the question is: Where is the
>floating node?
>
>Just my $0.02 worth.
>
>Peter Alfke, Xilinx Applications
>


Article: 10926
Subject: Re: I squared C on an FPGA
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 01 Jul 1998 23:01:28 -0400
Links: << >>  << T >>  << A >>
Allan Herriman wrote:
> 
> If you want a fully compliant I2C interface you can't do it in a
> regular 5V FPGA at all.
> The I2C spec says that SDA and SCL can not be loaded when the power is
> removed from the chip.
> The parasitic diode due to the P channel pullup transistor in regular
> FPGA outputs makes this impossible.
> 
> Perhaps you could use a 3V FPGA with 5V tolerant I/Os.
> 
> This is not a problem if you only have one power supply, and
> everything powers down at the same time.  Otherwise, you'll have to
> live with "not quite fully compliant" I2C interfaces.
> 
> I recall that the license agreement with Philips says that the
> interface can only be called I2C if it is fully compliant.
> 
> Just my $0.02 worth,
> Allan.

I don't have my schematics handy, but I seem to recall that we used
transistor driver with resistor pullups for the I2C interface even
though we were using an "I2C interface" chip from Signetics (or
Philips). Perhaps this is the norm? I did not design this circuit, so I
don't know the whys and wherefores. 


-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10927
Subject: UPDATED ENGINEERING PAGE: Please Visit
From: Scott Paul Johnston <metad@globalnet.co.uk>
Date: Thu, 02 Jul 1998 10:30:15 -0700
Links: << >>  << T >>  << A >>
Please visit and comment on my Electronics and Electrical Engineering
pages located at:

http://www.users.globalnet.co.uk/~metad/eee.htm

Containing:
Introduction to EEE
Resources (over 100 web links)
Employment Statistics and newspaper excerpts
Engineering Poems, Quotations and Jokes
EEE at Glasgow University

In addition my homepage (http://www.users.globalnet.co.uk/~metad/)
contains:

A section about me
My CV
A James Bond Section
A guestbook
500+ cool links in the "new look" bookpage
Cool background MIDI and graphics
Literary quotations
Photo Album
Awards Page
Poems...

Basically, something for everyone!

PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS!

Please send you comments via the guestbook or by Email (containing
your full name and Email and webpage addresses) and visit via 
http://www.users.globalnet.co.uk/~metad/.

Thanks 
Scott Johnston
metad@globalnet.co.uk
Article: 10928
Subject: Re: Power consumption question
From: Botond Kardos <Kardos.Botond@hu.innomed.NOSPAM>
Date: Fri, 03 Jul 1998 09:58:44 -0400
Links: << >>  << T >>  << A >>
Thx for the hints, I forgot to pull up the 4 dedicated inputs of the
FPGA, only the programmable I/O-s were configured for output.
   I can only answer to Peter's post, beacuse our ISP-s news server
sucks and I don't see the other messages.

   Botond

-- 
Botond Kardos  -  at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
      To get my real address just put the domain
      name in reverse order and remove 'nospam'.
      x@1.2.3 -> x@2.1
Article: 10929
Subject: Consultants
From: tiltonjones@my-dejanews.com
Date: Sat, 04 Jul 1998 00:27:08 GMT
Links: << >>  << T >>  << A >>
Hi,

My company is looking for a consultant to help us out on a DSP design project
using Xilinx FPGA.  We have not used this technology previously but it seems
like a good approach for this particular project.

Can anyone recommend a good consultant in this area?  What is the going rate
for this kind of service?

Any pointers appreciated,

Tilton Jones.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 10930
Subject: Re: Consultants
From: msimon@tefbbs.com
Date: Sat, 04 Jul 1998 00:27:16 GMT
Links: << >>  << T >>  << A >>
As far as I am able to tell your area is the Earth (there presently
being no known extraterrestrial colonies.)

Perhaps you would care to localize it further.

Simon
---------------------------------------------------------------------------------------------------------------
tiltonjones@my-dejanews.com wrote:

>Hi,
>
>My company is looking for a consultant to help us out on a DSP design project
>using Xilinx FPGA.  We have not used this technology previously but it seems
>like a good approach for this particular project.
>
>Can anyone recommend a good consultant in this area?  What is the going rate
>for this kind of service?
>
>Any pointers appreciated,
>
>Tilton Jones.
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum

Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.
Article: 10931
Subject: UPDATED ENGINEERING PAGE: Please Visit
From: Scott Paul Johnston <metad@globalnet.co.uk>
Date: 4 Jul 1998 10:51:05 -0000
Links: << >>  << T >>  << A >>
Please visit and comment on my Electronics and Electrical Engineering
pages located at:

http://www.users.globalnet.co.uk/~metad/eee.htm

Containing:
Introduction to EEE
Resources (over 100 web links)
Employment Statistics and newspaper excerpts
Engineering Poems, Quotations and Jokes
EEE at Glasgow University

In addition my homepage (http://www.users.globalnet.co.uk/~metad/)
contains:

A section about me
My CV
A James Bond Section
A guestbook
500+ cool links in the "new look" bookpage
Cool background MIDI and graphics
Literary quotations
Photo Album
Awards Page
Poems...

Basically, something for everyone!

PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS!

Please send you comments via the guestbook or by Email (containing
your full name and Email and webpage addresses) and visit via 
http://www.users.globalnet.co.uk/~metad/.

Thanks 
Scott Johnston
metad@globalnet.co.uk

Article: 10932
Subject: Re: Spartan test-board
From: APS <resp@associatedpro.com>
Date: Sat, 04 Jul 1998 07:25:13 -0400
Links: << >>  << T >>  << A >>
The X84 FPGA Test board is a low cost FPGA board which canuse the SPARTAN
Chips and is already complete. You can see the details at

http://www.associatedpro.com

Marcus Lankenau wrote:

> Hi!
>
> I'm currently developing a very simple test board for the spartan
> XCS05 (PLCC84 package). I connected  program (pin55), din (pin71) and
> cclk (pin73) using a 74ls14 schmidt-triger with a prallelport
> connector. Are these three signals all I need to programm the fpga in
> slave mode (I'm a little confudes with the datasheed)? Wich kind of
> output file should I generate (MCS, hex....) with F1.4 to download the
> bitstream (I want to write a litle transfer-software on my own)???
>
> thanks in advance
>
> Marcus Lankenau



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 10933
Subject: Re: Consultants
From: APS <resp@associatedpro.com>
Date: Sat, 04 Jul 1998 07:27:03 -0400
Links: << >>  << T >>  << A >>
Look at the following website:

http://www.associatedpro.com

for consulting and a lot of great FPGA solutions

tiltonjones@my-dejanews.com wrote:

> Hi,
>
> My company is looking for a consultant to help us out on a DSP design project
> using Xilinx FPGA.  We have not used this technology previously but it seems
> like a good approach for this particular project.
>
> Can anyone recommend a good consultant in this area?  What is the going rate
> for this kind of service?
>
> Any pointers appreciated,
>
> Tilton Jones.
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 10934
Subject: Re: complete testing
From: APS <resp@associatedpro.com>
Date: Sat, 04 Jul 1998 07:36:39 -0400
Links: << >>  << T >>  << A >>
Often you can test all or protions of your design very thouroghly using
FPGA test boards. The X208 FPGA board from APS has board set up which works
nicely for this. It has a BUS FPGA and a TEST FPGA (socketed 208 pin QFP)
with both daughter board connectors and a 96 pin edge connector. It also
has a programmable Direct Digital Synthesized clock which allows for
testing with sub hertz resolution clocks. It also has 64K of SRAM which can
also be used for test vectors and the like. The DDS and SRAM are socketed
and can be removed if more pins are needed. The board's can be configured
via the bus or  via the on board XILINX download cable port or using
EPROMs. The board is designed to used over and over for maximum flexible
testing and development. See:

http://www.associatedpro.com

Robert Peach wrote:

> Hi again,
>
>  I want to add to my last question.  I would like to test the FPGA part
> so that it demonstrates proper operation under all combinations and
> permutations at the gates and pins of the device.  I know that for very
> dense FPGAs that this is not possible as it would take to much time.  I
> would like feedback on testing tools and methods that test an FPGA to a
> degree that I can be confident that I will not get a failure such as
> Latchup or SEU.  Nothing is 100%, but if you know some things that are
> close I would appreciate hearing about it.
> Thank you.
>
> Robert Peach
> Lockheed Martin Aeronautical Systems
> Atlanta, GA
> (770) 494-7587
> rpeach@gelac.mar.lmco.com



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 10935
Subject: FPGA Programming Bitstream Compression
From: "C. R. Johnson" <cjohnson11@snet.net>
Date: Sun, 05 Jul 1998 00:08:03 -0400
Links: << >>  << T >>  << A >>
I am looking at writing a compression/decompression
utility for FPGA bitstreams, as has been recently
discussed in this forum.

It would be a great help if people could send me some
bitstream files as test cases.  You can flip a few
random bits in the file if you're worried about
sending out your programming files.  You don't even
have to tell me what kind of device the file is
for.

I only have access to several Lattice pLSI and a few
Altera FLEX6000 programming files as test cases.

I am investigating what kind of compression would work
best, with emphasis on very simple decode, in order to
allow for a reasonable bit rate decompression from an
embedded implementation.

I will email a copy of the resulting code to anyone who
sends me a test programming file.

Regards,

Chris Johnson
Article: 10936
Subject: Re: FPGA Bitstream Programming Compression
From: Alexander Sherstuk <Sherstuk@amsd.com>
Date: Sun, 5 Jul 1998 16:05:37 +0400
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------ =_NextPart_001_01BDA80D.38C74159
Content-Type: text/plain

Hi Chris,

Here are bitstream's characteristics for XILINX FPGA's

File name    Uncompressed Compressed     FPGA device
              size        size (PKZIP)   utilization
LCA02V05.DAT 11876        9483 (-23%)    97% of XC4005E
LCA02V06.DAT 11876        9294 (-22%)    96% of XC4005E
LCA03V15.DAT  3854        3223 (-17%)    89% of XC3042A
X4096V10.DAT 10173        7743 (-24%)    70% of XC4005
X4096X11.DAT 11876        9079 (-24%)    72% of XC4005E
XLWRKA.DAT   11876        4558 (-62%)    12% of XC4005E
XPTSTB.DAT   22268        6532 (-71%)    26% of XC4010E

As you may see, PKZIP compression for the XILINX bitstreams is
not very good, when FPGA device is highly utilized, despite the
fact that all of my designs have a lot of regular repetetive structures:
   multibit registers, counters, adders, multibit buffers.
Also, it does not meet expectations for under-used FPGA designs.
Possibly, each type of XILINX device requires some bit reordering
pattern applied before compression. XILINX keeps in secret particular
bit
assignments for their devices bitstreams. So the data bits, which 
encode each logic block, need not be located together in the bitstream.
What is known for sure - bit reordering is always the same for each
given
part type (e.g. XC3042A, XC4005E, XC4010E, ...) 

Anyway, if you would achieve some compression, (even without any bit 
reordering tricks) that would be great - every byte of ROM storage is 
precious for embedded designs.

Please, do not forget about important requirement for embedded
decompressing routines: minimize RAM usage! 
8051 has only about several dozens bytes to be used as
storage for program variables.
I think, RAM limitation is much more important, than CPU time needed
for decompression.

Wishing you success in your effort. 

   Alex Sherstuk
    Sherstuk@amsd.com

-----Original Message-----
From: C. R. Johnson [mailto:cjohnson11@snet.net]
Posted At: Sunday, July 05, 1998 8:08 AM
Posted To: comp.arch.fpga
Conversation: FPGA Programming Bitstream Compression
Subject: FPGA Programming Bitstream Compression


I am looking at writing a compression/decompression
utility for FPGA bitstreams, as has been recently
discussed in this forum.

It would be a great help if people could send me some
bitstream files as test cases.  You can flip a few
random bits in the file if you're worried about
sending out your programming files.  You don't even
have to tell me what kind of device the file is
for.

I only have access to several Lattice pLSI and a few
Altera FLEX6000 programming files as test cases.

I am investigating what kind of compression would work
best, with emphasis on very simple decode, in order to
allow for a reasonable bit rate decompression from an
embedded implementation.

I will email a copy of the resulting code to anyone who
sends me a test programming file.

Regards,

Chris Johnson

------ =_NextPart_001_01BDA80D.38C74159
Content-Type: text/html
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.1960.3">
<TITLE>Re: FPGA Bitstream Programming Compression</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Hi Chris,</FONT>
</P>

<P><FONT SIZE=3D2>Here are bitstream's characteristics for XILINX =
FPGA's</FONT>
</P>

<P><FONT SIZE=3D2>File name&nbsp;&nbsp;&nbsp; Uncompressed =
Compressed&nbsp;&nbsp;&nbsp;&nbsp; FPGA device</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; size&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; size =
(PKZIP)&nbsp;&nbsp; utilization</FONT>
<BR><FONT SIZE=3D2>LCA02V05.DAT =
11876&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 9483 =
(-23%)&nbsp;&nbsp;&nbsp; 97% of XC4005E</FONT>
<BR><FONT SIZE=3D2>LCA02V06.DAT =
11876&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 9294 =
(-22%)&nbsp;&nbsp;&nbsp; 96% of XC4005E</FONT>
<BR><FONT SIZE=3D2>LCA03V15.DAT&nbsp; =
3854&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3223 =
(-17%)&nbsp;&nbsp;&nbsp; 89% of XC3042A</FONT>
<BR><FONT SIZE=3D2>X4096V10.DAT =
10173&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 7743 =
(-24%)&nbsp;&nbsp;&nbsp; 70% of XC4005</FONT>
<BR><FONT SIZE=3D2>X4096X11.DAT =
11876&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 9079 =
(-24%)&nbsp;&nbsp;&nbsp; 72% of XC4005E</FONT>
<BR><FONT SIZE=3D2>XLWRKA.DAT&nbsp;&nbsp; =
11876&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4558 =
(-62%)&nbsp;&nbsp;&nbsp; 12% of XC4005E</FONT>
<BR><FONT SIZE=3D2>XPTSTB.DAT&nbsp;&nbsp; =
22268&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 6532 =
(-71%)&nbsp;&nbsp;&nbsp; 26% of XC4010E</FONT>
</P>

<P><FONT SIZE=3D2>As you may see, PKZIP compression for the XILINX =
bitstreams is</FONT>
<BR><FONT SIZE=3D2>not very good, when FPGA device is highly utilized, =
despite the</FONT>
<BR><FONT SIZE=3D2>fact that all of my designs have a lot of regular =
repetetive structures:</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp; multibit registers, counters, adders, =
multibit buffers.</FONT>
<BR><FONT SIZE=3D2>Also, it does not meet expectations for under-used =
FPGA designs.</FONT>
<BR><FONT SIZE=3D2>Possibly, each type of XILINX device requires some =
bit reordering</FONT>
<BR><FONT SIZE=3D2>pattern applied before compression. XILINX keeps in =
secret particular bit</FONT>
<BR><FONT SIZE=3D2>assignments for their devices bitstreams. So the =
data bits, which </FONT>
<BR><FONT SIZE=3D2>encode each logic block, need not be located =
together in the bitstream.</FONT>
<BR><FONT SIZE=3D2>What is known for sure - bit reordering is always =
the same for each given</FONT>
<BR><FONT SIZE=3D2>part type (e.g. XC3042A, XC4005E, XC4010E, ...) =
</FONT>
</P>

<P><FONT SIZE=3D2>Anyway, if you would achieve some compression, (even =
without any bit </FONT>
<BR><FONT SIZE=3D2>reordering tricks) that would be great - every byte =
of ROM storage is </FONT>
<BR><FONT SIZE=3D2>precious for embedded designs.</FONT>
</P>

<P><FONT SIZE=3D2>Please, do not forget about important requirement for =
embedded</FONT>
<BR><FONT SIZE=3D2>decompressing routines: minimize RAM usage! </FONT>
<BR><FONT SIZE=3D2>8051 has only about several dozens bytes to be used =
as</FONT>
<BR><FONT SIZE=3D2>storage for program variables.</FONT>
<BR><FONT SIZE=3D2>I think, RAM limitation is much more important, than =
CPU time needed</FONT>
<BR><FONT SIZE=3D2>for decompression.</FONT>
</P>

<P><FONT SIZE=3D2>Wishing you success in your effort. </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp;&nbsp; Alex Sherstuk</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp; Sherstuk@amsd.com</FONT>
</P>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: C. R. Johnson [<A =
HREF=3D"mailto:cjohnson11@snet.net" =
TARGET=3D"_blank">mailto:cjohnson11@snet.net</A>]</FONT>
<BR><FONT SIZE=3D2>Posted At: Sunday, July 05, 1998 8:08 AM</FONT>
<BR><FONT SIZE=3D2>Posted To: comp.arch.fpga</FONT>
<BR><FONT SIZE=3D2>Conversation: FPGA Programming Bitstream =
Compression</FONT>
<BR><FONT SIZE=3D2>Subject: FPGA Programming Bitstream =
Compression</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>I am looking at writing a compression/decompression</F=
ONT>
<BR><FONT SIZE=3D2>utility for FPGA bitstreams, as has been =
recently</FONT>
<BR><FONT SIZE=3D2>discussed in this forum.</FONT>
</P>

<P><FONT SIZE=3D2>It would be a great help if people could send me =
some</FONT>
<BR><FONT SIZE=3D2>bitstream files as test cases.&nbsp; You can flip a =
few</FONT>
<BR><FONT SIZE=3D2>random bits in the file if you're worried =
about</FONT>
<BR><FONT SIZE=3D2>sending out your programming files.&nbsp; You don't =
even</FONT>
<BR><FONT SIZE=3D2>have to tell me what kind of device the file =
is</FONT>
<BR><FONT SIZE=3D2>for.</FONT>
</P>

<P><FONT SIZE=3D2>I only have access to several Lattice pLSI and a =
few</FONT>
<BR><FONT SIZE=3D2>Altera FLEX6000 programming files as test =
cases.</FONT>
</P>

<P><FONT SIZE=3D2>I am investigating what kind of compression would =
work</FONT>
<BR><FONT SIZE=3D2>best, with emphasis on very simple decode, in order =
to</FONT>
<BR><FONT SIZE=3D2>allow for a reasonable bit rate decompression from =
an</FONT>
<BR><FONT SIZE=3D2>embedded implementation.</FONT>
</P>

<P><FONT SIZE=3D2>I will email a copy of the resulting code to anyone =
who</FONT>
<BR><FONT SIZE=3D2>sends me a test programming file.</FONT>
</P>

<P><FONT SIZE=3D2>Regards,</FONT>
</P>

<P><FONT SIZE=3D2>Chris Johnson</FONT>
</P>

</BODY>
</HTML>
------ =_NextPart_001_01BDA80D.38C74159--

Article: 10937
Subject: Re: Consultants
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sun, 5 Jul 1998 09:55:18 -0700
Links: << >>  << T >>  << A >>
Without knowing more about your location,  I can only give you five names as
a recommendation for consultants specializing in XC4000 and DSP (all in the
US).


Fliptronics
-----------
http://www.geocities.com/SiliconValley/2256/


The Andraka Group
-----------------
http://users.ids.net/~randraka/


Morphologic
-----------
http://www.morphologic.com/pres1.htm
Their site is primarily about their software but they also do some
DSP-related consulting.


PC Engineering
--------------
http://home.att.net/~pcuenin/HOME1.HTM



Rapid Prototypes
----------------
http://www.fpga.com/


These are a few of the select listing from the consulting section of The
Programmable Logic Jump Station at
http://www.optimagic.com/consultants.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------




tiltonjones@my-dejanews.com wrote in message
<6njsss$ueg$1@nnrp1.dejanews.com>...
>Hi,
>
>My company is looking for a consultant to help us out on a DSP design
project
>using Xilinx FPGA.  We have not used this technology previously but it
seems
>like a good approach for this particular project.
>
>Can anyone recommend a good consultant in this area?  What is the going
rate
>for this kind of service?
>
>Any pointers appreciated,
>
>Tilton Jones.
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum




Article: 10938
Subject: Re: Spartan test-board
From: mlankenau@yahoo.com (Marcus Lankenau)
Date: Sun, 05 Jul 1998 20:59:45 GMT
Links: << >>  << T >>  << A >>
Too expensive (student) ...
Thanx for the hint!

APS <resp@associatedpro.com> wrote:

>The X84 FPGA Test board is a low cost FPGA board which canuse the SPARTAN
>Chips and is already complete. You can see the details at
>
>http://www.associatedpro.com

Article: 10939
Subject: FREE ASIC ESTIMATOR
From: "kash johal" <kash@ix.netcom.com>
Date: 6 Jul 1998 03:45:36 GMT
Links: << >>  << T >>  << A >>
>>>>>>>>>  Binary SPAM deleted by Archive Owner



Article: 10940
Subject: Altera MAX+PLUS 8.1
From: "koh bongseok" <stonesys@chollian.net>
Date: Mon, 06 Jul 1998 07:18:06 GMT
Links: << >>  << T >>  << A >>
Hello.

I want to download MAX+PLUS 8.1  for pc
please tell me where this program is located

Thank you.


Article: 10941
Subject: Altera MAX+PLUS 8.1
From: "koh bongseok" <stonesys@chollian.net>
Date: Mon, 06 Jul 1998 07:36:20 GMT
Links: << >>  << T >>  << A >>
Hello.

I want to download MAX+PLUS 8.1  for pc
please tell me where this program is located

Thank you.

mail me:  stonesys@chollian.net


Article: 10942
Subject: Re: FREE ASIC ESTIMATOR
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 6 Jul 1998 10:08:21 GMT
Links: << >>  << T >>  << A >>

May I recommend that everyone make a copy of this persons most recent 
SPAM article that included a binary (well an excel spread sheet if you 
trust the file name), and email it back to him. Dont post it to the news 
group :-)


In article <01bda890$0a7f16e0$c5e96dd1@kash.ix.netcom.com> "kash johal" <kash@ix.netcom.com> writes:
>Feel free to review our free ZERO NRE asic price estimator.
>
>Would appreciate feedback on ease of use, competitiveness and how we can
>make it better.
>
>Normally pricing is hidden, we hop to cahnge all that.
>
>Best regards,
>
>Kash
>
>begin 600 webcost71.xls
>MT,\1X*&Q&N$`````````````````````/@`#`/[_"0`&```````````````!
yada yada yada

>M`&4`;@!T`%,`=0!M`&T`80!R`'D`20!N`&8`;P!R`&T`80!T`&D`;P!N````
>M```````````X``(!________________%A `37D@1&]C=6UE;G1S`$U91$]#
>;57XQ````_]T``*"H>D0`&0`````0``"BV @`
>`
>end
>


Article: 10943
Subject: How to download bitstream on a SUN ...
From: Walter Schweigart <Walter.Schweigart@e-technik.uni-ulm.de>
Date: Mon, 06 Jul 1998 12:14:37 +0200
Links: << >>  << T >>  << A >>
Hello,

We are working with Xilinx M1.4 Alliance Software on a SUN
Workstation under Solaris 2.5. The Sofware as well as the
Synopsys Interface runs well - only the Download with the
Xchecker cable to the serial port /dev/term/a doesn't work.

It seem's to be a UNIX problem because the error message is
"can't communicate with /dev/ttya ..."

Does anybody know a solution for this problem?


Thank you very much


Walter.Schweigart@e-technik.uni-ulm.de




Albert-Einstein-Allee 43
Universitaet Ulm
D - 89069 Ulm




Article: 10944
Subject: Xilinx Foundation Frustartions
From: Paul Walker <paul@walker.demon.co.uk>
Date: Mon, 6 Jul 1998 12:14:08 +0100
Links: << >>  << T >>  << A >>
Perhaps you get what you pay for, and the very cheap Foundation Base
package is a pretty good buy, particularly as the "10k gates" limit only
applies to the 4kE family, and the package seems to be able to work with
Spartans up to XCS40.

But I begin to tear (what's left of) my hair out when saving an edit to
a symbol, and the message appears "Incorrect Pin Name" and it refuses to
save the symbol; No indication which pin, nor what is wrong with the
name; nothing in Help to say what a correct pin name is; nothing
produced from the menu item "test symbol" other than the same "Incorrect
Pin Name". 

Of course there is a workaround to a problem like this --- throw away
all the edits to the symbol and start again, saving this time after
every tiny edit to catch the one that went wrong. But should we really
have to do so?

This prompts me to write up a few other frustrations. If anyone has any
good ways to avoid them, or has similar experiences with other parts of
Foundation or with other products, please let us know.

Auto-Placement: The critical timing on a Spartan part, a single level of
logic between the two edges of a clock, was ok but about 80% logic delay
so I wondered if a faster device would go faster. With the same
constraint file, a 4kE-1 actually went slower, not because of this
critical path, but because other paths had been made worse by the
ugliest placement imaginable. I spent about half an hour with EPIC doing
a crude placement based on the rats' nest, and without any reference to
the logic design. Two or three passes of EPIC's router then produced a
routing that went almost twice as fast as the original auto
implementation.

Copying projects: When you copy a project, the UCF file that constrained
timings or pins is copied across, but a dummy new one is generated for
the new project. Design Manager proceeds to use this new file rather
than the old one. The documentation does actually say this, but there is
a big inconsistency between Project Manager's concept of attaching files
to the project, and Design Managers's concept of using default filenames
regardless.

Upper and Lower Case: There are dire warnings in some of the
documentation that while M1.4 is case insensitive, M1.5 will be case
sensitive and so users should be consistent. Fine, I'd love to use
signal names such as TxClock and RxClock, and am totally happy to be
consistent with the upper and lower case. But the Schematic entry
package that comes with Foundation insists that all signal names are
upper case, regardless of what I type. I would, politely as I can,
suggest to Xilinx that this is INCONSISTENT_AND_VERY_ANNOYING.

The old PLDShell software produced by Intel and canned by Altera was and
still is extremely good. We have a number of designs in PLDShell, and
several of these are now designed for a fan-in of four, so are optimised
for Xilinx (and other) FPGA LUTs. We can convert the PLDShell to Abel
for input to Foundation, and this poses no problem. What causes more of
a problem is that ABL2EDIF seems to do its own optimisations which turn
our one level of logic into two or three levels. What's more, there is
no way to turn this optimisation off. Of course it is possible to
convert to VHDL, but at a large increase in cost, a large learning time,
and the expectation suggested by many contributors to this news group
that the performance will be poor. If anyone has any suggestions of how
to take a design for 4-input LUTs straight through to an implementation
which preserves the original design, I'd be most grateful.

Thanks

Paul

PS. In spite of all this, I still like the RAM of the 4kE, and like many
aspects of the Foundation package. The UK help desk has been very
helpful, even when I've not read the manual and even when there is
nothing they can do.
-- 
Paul Walker                      4Links                      phone/fax
paul@walker.demon.co.uk          P O Box 816, Two Mile Ash    +44 1908
http://www.walker.demon.co.uk    Milton Keynes MK8 8NS, UK      566253
Article: 10945
Subject: Re: Consultants
From: jimmeans@my-dejanews.com
Date: Mon, 06 Jul 1998 17:17:58 GMT
Links: << >>  << T >>  << A >>
In article <359d7659.2764430@news.megsinet.net>,
  msimon@tefbbs.com wrote:
>
> As far as I am able to tell your area is the Earth (there presently
> being no known extraterrestrial colonies.)
>
> Perhaps you would care to localize it further.
>
> Simon
>
--------------------------------------------------------------------------------
-------------------------------
> tiltonjones@my-dejanews.com wrote:
>
> >Hi,
> >
> >My company is looking for a consultant to help us out on a DSP design project
> >using Xilinx FPGA.  We have not used this technology previously but it seems
> >like a good approach for this particular project.
> >
> >Can anyone recommend a good consultant in this area?  What is the going rate
> >for this kind of service?
> >
> >Any pointers appreciated,
> >
> >Tilton Jones.
> >
> >-----== Posted via Deja News, The Leader in Internet Discussion ==-----
> >http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
>
> Opinions expressed herein are solely my own and may or may not reflect my
opinion at this particular time or any other.
>

I believe there are also Internet connections to orbiting spacecraft, so
Tilton could be in space. ;-)

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 10946
Subject: Spartan S30 DOUT/SGCK4 pin
From: dfrevele@li.net
Date: Mon, 06 Jul 1998 18:46:21 GMT
Links: << >>  << T >>  << A >>
I'm doing a design with a Spartan S30 in a PQ208 package and noticed what I
consider an odd pin assignment. Pin P154 is labeled "I/O, SGCK4, (DOUT)" . So
during configuration the pin acts as DOUT which is an _OUTPUT_ and after that
I can make it SGCK4 which is an _INPUT_. Is this correct?

If I want to use this pin as a global clock buffer I have to provide a
resistor or something to prevent contention? Is this pin an output during
configuration even if it is the only device being configured?

Was this a good pin assignment made by Xilinx?

Don Frevele
GEC-Marconi Hazeltine Corp.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 10947
Subject: Configure with BIT file
From: dfrevele@li.net
Date: Mon, 06 Jul 1998 20:11:25 GMT
Links: << >>  << T >>  << A >>
easy question:

I want to configure a single Xilinx from a microprocessor. Can I just download
the .bit file produced from the implementation tools? I've previously loaded
multiple daisy-chained Xilinxs from a microprocessor and had to use makeprom
(promgen) to produce the download file. But for a single device can the .bit
file be used directly.


Don Frevele
GEC-Marconi Hazeltine Corp.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 10948
Subject: Re: Configure with BIT file
From: Ed McCauley <edmccauley@bltinc.com>
Date: Mon, 06 Jul 1998 22:04:28 -0400
Links: << >>  << T >>  << A >>
Don,

The .bit file basically contains the same data as the .mcs files
produced by makeprom.  
Differences: .mcs contains address info that is used by the prom
programmer to locate the values in the data fields.  prom files also
contains row length and check sum values, again used by the prom
programmer, NOT written into the PROM.  That's key.... the extra values
don't go into the prom, they only control the operation of the
programmer.  

If you want just the 1s and 0s, you want to turn on the "Produce ASCII
Configuration File" option in the configuration/configuration template. 
What are you really trying to do?

BTW, we flew into Republic a week or so ago and met with John Holst and
Fred LaMarca (the Hamilton salesperson and FAE) to discuss how BLT might
help your company.

-- 
Ed McCauley
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA, (908) 996-0817
FAX:   (908) 996-0817

dfrevele@li.net wrote:
> 
> easy question:
> 
> I want to configure a single Xilinx from a microprocessor. Can I just download
> the .bit file produced from the implementation tools? I've previously loaded
> multiple daisy-chained Xilinxs from a microprocessor and had to use makeprom
> (promgen) to produce the download file. But for a single device can the .bit
> file be used directly.
> 
> Don Frevele
> GEC-Marconi Hazeltine Corp.
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 10949
Subject: CRC's and PRBS in Paralell
From: Dominick Cafarelli <dcafarel@bestweb.net>
Date: Mon, 06 Jul 1998 22:11:41 -0400
Links: << >>  << T >>  << A >>
Has anyone done CRC's or Pseudo Random Bit Sequences (BERT patterns) in
paralell in FPGA's.

THanks,
Dominick



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