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Messages from 109600

Article: 109600
Subject: Re: state machine dead problem
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 30 Sep 2006 10:23:04 GMT
Links: << >>  << T >>  << A >>
On Fri, 29 Sep 2006 16:07:08 -0400, "Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote:
>A slightly more paranoid version of this would include glitch filtering 
>as well - add some extra FFs and update the internal net only when all 
>FFs match, hold the previous value otherwise.

Any glitch filter should only depend on some function of the flipflops
after the flipflops used for the synchronizer. If you involve the
synchronizer FFs in the glitch filter, you have probably created a
bypass path that may defeat much of your efforts to manage
metastables within the synchronizer.

>BTW, make sure the first FF gets packed into IOBs since these are 
>usually designed to reduce the likelyhood of metastability ever 
>happening and settle faster in case they fail to prevent it. Regular FFs 
>are designed for highest speed and smallest footprint, they might never 
>settle when they go metastable.

This is not the case. There is nothing about the IOB FFs that makes them
inherently better at resolving metastables, and likewise, the main array
FFs are certainly not some how worse. In fact the high speed of the FFs
(in both the main array and the IOBs) is a characteristic that leads to
the very good metastable recovery characteristics of current products.

There is some cleverness in the delay paths for the D and CLK pins of
IOB input FFs that help in achieving close to 0.0 ns hold time, but this
in no way helps or hinders the metastable charateristics of the IOB FF.

Philip Freidin

===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG

Article: 109601
Subject: DDR RAM
From: "vittal" <vittal.patil@gmail.com>
Date: 30 Sep 2006 03:31:12 -0700
Links: << >>  << T >>  << A >>
Hi ,
i am new to the memory modules .I want to study about DDR Rams .
So please send me the links to study in depth about various rams
and their controllers,
Vits


Article: 109602
Subject: Re: DDR RAM
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 30 Sep 2006 13:18:50 +0200
Links: << >>  << T >>  << A >>
"vittal" <vittal.patil@gmail.com> schrieb im Newsbeitrag 
news:1159612272.505495.186910@k70g2000cwa.googlegroups.com...
> Hi ,
> i am new to the memory modules .I want to study about DDR Rams .
> So please send me the links to study in depth about various rams
> and their controllers,
> Vits
>
there is only one link that can help you so i am giving it to you!

www.google.com

Antti
http://www.microfpga.com



Article: 109603
Subject: Re: DDR RAM
From: "Slurp" <slip@slap.slop>
Date: Sat, 30 Sep 2006 14:21:35 +0100
Links: << >>  << T >>  << A >>

"vittal" <vittal.patil@gmail.com> wrote in message 
news:1159612272.505495.186910@k70g2000cwa.googlegroups.com...
> Hi ,
> i am new to the memory modules .I want to study about DDR Rams .
> So please send me the links to study in depth about various rams
> and their controllers,
> Vits
>
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  Nickles.de - Forum: RAM - Module, Marken, Murks - [ Translate this 
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  Computerhilfen.de: Hilfe: Hardware-Fragen - [ Translate this page ]Hi, hab 
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  eBay Österreich: DDR-RAM, 184-polig, RAM-Speicher, Computer, 333 - [ 
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  [PDF] Xilinx XAPP697 Dynamic Phase Alignment Using Asynchronous Data 
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        Up to 800 Mbps Double Data Rate (DDR) in Virtex-II FPGAs. Up to 1 
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Article: 109604
Subject: Re: DDR RAM
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sat, 30 Sep 2006 17:03:21 +0200
Links: << >>  << T >>  << A >>
vittal schrieb:
> Hi ,
> i am new to the memory modules .I want to study about DDR Rams .
> So please send me the links to study in depth about various rams
> and their controllers,
> Vits
> 

www.micron.com

Regards
Falk

Article: 109605
Subject: Re: DDR RAM
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Sat, 30 Sep 2006 08:56:29 -0700
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> there is only one link that can help you so i am giving it to you!
> 
> www.google.com

I've heard rumours of other similiar sites, but I've never
tried them myself. :)

-Dave

-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 109606
Subject: Re: DDR RAM
From: nico@puntnl.niks (Nico Coesel)
Date: Sat, 30 Sep 2006 16:19:11 GMT
Links: << >>  << T >>  << A >>
vittal" <vittal.patil@gmail.com> wrote:

>Hi ,
>i am new to the memory modules .I want to study about DDR Rams .
>So please send me the links to study in depth about various rams
>and their controllers,
>Vits
>
Visit www.jedec.org and look for JESD79 (DDR specification). Jedec
maintains the specifications. If your DDR controller conforms to the
specifications for a given speed, it should work with any Jedec
compliant DDR memory suitable to run at the given speed.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 109607
Subject: System ACE woes
From: Tommy Thorn <foobar@nowhere.void>
Date: Sat, 30 Sep 2006 10:19:23 -0700
Links: << >>  << T >>  << A >>
I'm trying to use the System ACE CF feature of the nice Xilinx ML401 board, but 
mysteriously, my .ace files doesn't work.  Instead it results in the shiny red 
"Err" LED.

I have a very simple "blink LED" style design that works fine when programmed 
over JTAG. Every configuration option has been left at their default value 
(except the start up clock where I tried both JTAG and CCLK). Impact happily 
generated my .ace file which was roughly the same size as the 
"system_my_ace.ace" that it overwrote, but when that entry is chosen from the 
ML401's bootloader, it fails loading.

I haven't been able to find much documentation; with some digging I found the 
DS080 "System ACE CompactFlash Solution", but it didn't cast light on this problem.

To add insult to injury, I reformatted the CF under Windows and unzipped the 
SystemACE_CF.zip recovery image and now nothing from the CF works, not even the 
bootloader. (This is with the Xilinx supplied CF card).

Thanks,
Tommy

Article: 109608
Subject: using spartan 3E starter kit for CAN bus probe ?
From: rponsard@gmail.com
Date: 30 Sep 2006 14:31:07 -0700
Links: << >>  << T >>  << A >>
Hi experts !

in your opinion, is it possible to build a CAN field bus probe (simple
app. for edu. ; needs only to display Id and data , no CANopen objects)
with the spartan 3E starter kit + ISE and EDK ?

1) Does is have enough bram ? and mips ? ... ?

2) The minimalistic system should be build around a picoblaze soft
processor for data display to lcd and www.opencores.org CAN controler
(is it reliable ?) How much work is it for, say, a software developper
new to fpga design (already done an I2C slave node and Quadrature
encoder for spartan3)

3) Is it realistic trying to implement a uclinux (as murakana.info) ,
plus an IP stack and some kind of httpserver to publish the CAN data as
a web app. ?

raph


Article: 109609
Subject: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Sat, 30 Sep 2006 23:34:26 +0200
Links: << >>  << T >>  << A >>
Hi KJ,

> On the SOPC Builder side of things I can flatly state that the tool itself
> is very poor for anything other than the most minimal of 'programmable
> systems on a chip'.

I was told that this was also recognized by Altera themselves, and that SOPC
Builder will have had a complete overhaul in Quartus II 6.1. The PTF file
will be gone (I vaguely remember a slide mentioning XML combined with
something else as the replacement).

Having designed and debugged a few SOPC Builder bits and pieces, I can't say
how happy I am that Altera finally took this horribly over-evolved
proof-of-concept code behind the barn and shot it. Kudos to the guys that
kept it going in the meantime, and I'm really curious about the successor.

As a sidenote, if you run SOPC Builder on Solaris or Linux, you'll cream
your pants over the speed at which the generator runs on those platforms -
the generator is written in Perl and doesn't need the Cygwin emulation
there. I've witnessed tenfold speed improvements on large (30+ components)
designs.

Best regards,



Ben




Article: 109610
Subject: PLB/OPB Bus Access from ISE
From: "akcooper8@gmail.com" <akcooper8@gmail.com>
Date: 30 Sep 2006 16:48:08 -0700
Links: << >>  << T >>  << A >>
Is there an easy way to access the PLB or OPB buses from XIlinx ISE
without going through the PowerPC and EDK?
I am using the XUP Virtex II Pro Development Board and want to
read/write from DDR RAM in ISE rather then EDK for speed reasons.
So I need to access the PLB/OPB buses from ISE which are connected to
the DDR RAM.

Thanks

Ashwin


Article: 109611
Subject: Re: Are you ready for Virtex-5? We are...
From: zwsdotcom@gmail.com
Date: 30 Sep 2006 19:57:34 -0700
Links: << >>  << T >>  << A >>

Peter Alfke wrote:
> We are only interested in serious designers, not just "tire-kickers".
> The registration is not a hurdle if you are serious.

This is patently untrue. Choosing the right silicon for a new project
is an immense task. Selecting the micro for even a small job (except in
special cases) requires me to generate a mountain of paperwork. I have
to show a matrix of choices, pro/con points, cost targets, how that
will affect the BOM of the board, expected EMI issues, first-order
approximation of power budget, etc.

A vendor who puts me through 20 minutes of registration (especially on
Xilinx's bouncy servers - here one second, down the next - and
braindead browser requirements "you must be running IE6 from Win XP SP2
and you must have the patches up to 9/1/2005 installed BUT NOTHING
LATER, and you must have all security disabled and some unstated
ActiveX control installed") is going to be kicked into the "too hard"
pile immediately.

Special case exceptions I referred to above are projects that will
reuse a lot of code from an existing device, so the micro choice is
constrained.


Article: 109612
Subject: Re: System ACE woes
From: "Antti" <Antti.Lukats@xilant.com>
Date: 1 Oct 2006 00:05:37 -0700
Links: << >>  << T >>  << A >>
Tommy Thorn schrieb:

> I'm trying to use the System ACE CF feature of the nice Xilinx ML401 board, but
> mysteriously, my .ace files doesn't work.  Instead it results in the shiny red
> "Err" LED.
>
> I have a very simple "blink LED" style design that works fine when programmed
> over JTAG. Every configuration option has been left at their default value
> (except the start up clock where I tried both JTAG and CCLK). Impact happily
> generated my .ace file which was roughly the same size as the
> "system_my_ace.ace" that it overwrote, but when that entry is chosen from the
> ML401's bootloader, it fails loading.
>
> I haven't been able to find much documentation; with some digging I found the
> DS080 "System ACE CompactFlash Solution", but it didn't cast light on this problem.
>
> To add insult to injury, I reformatted the CF under Windows and unzipped the
> SystemACE_CF.zip recovery image and now nothing from the CF works, not even the
> bootloader. (This is with the Xilinx supplied CF card).
>
> Thanks,
> Tommy

the first partition must be FAT16, windows selects FAT32 as default
try reformatting with FAT16 (select FAT in format options)

Antti


Article: 109613
Subject: Re: Migration from Spartan-2E to Spartan-3E
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 01 Oct 2006 09:58:22 GMT
Links: << >>  << T >>  << A >>
John_H <newsgroup@johnhandwork.com> wrote:
>pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
>>> I think S2 had tristate buffers but not S2E; either way, S3 and S3E 
>>> don't have them.  Memory blocks are now larger and DLLs are more 
>>> functional as DCMs, both have "compatibility modes" for older designs. 
>>> There's no longer a power-on surge.  You also have new, cheaper 
>>> programming ROM options.
>> 
>> Are you sure the power-on surge is gone ..?, so far what I have seen this
>> issue is on Spartan-3/3E aswell.

>There are power on requirements, indeed.  Simply not the 4x operating 
>current (wild estimate, unsubstantiated) of previous parts.  I haven't 
>taken a current probe to my well-behaved boards, however.  The 
>fundamental problem with the older parts was addressed in the silicon.

What's the power-on requirements for Spartan-3/3E 200-400k chips then..?
I read a some power supply design documents. Seemed like a mess.. ;)


Article: 109614
Subject: Declaration of xilkernel_main()
From: "Bernhard Sputh" <sputhnic@yahoo.de>
Date: 1 Oct 2006 15:07:58 GMT
Links: << >>  << T >>  << A >>
Hi group,

I'm currently developing a Communicating Sequential Processes library for
the Xilinx Micro Kernel (XMK). I recently went and used the compiler flags
-Wall and -Werror to let the compiler detect any potential problems. So
far everything works out fine, except that now the compiler complains
about an implicit declaration of the function: `xilkernel_main()'. I
searched through the include files for the corresponding MicroBlaze core
without finding any declaration for it. Does anybody out there know where
this function is declared?

Another problem I have run into is to detect which version of XMK my code
is currently being compiled with. Any idea how I could acquire this
information during compile time?


Cheers
Bernhard

-- 
William of Ockham, Albert Einstein, and Stephen Hawking walk into a bar.
Bartender: Oh, NO! Not another bloody parallel programming joke.

Article: 109615
Subject: Re: ddr2 sodimm controller
From: Markus Meng <meng.engineering@bluewin.ch>
Date: Sun, 01 Oct 2006 17:46:34 +0200
Links: << >>  << T >>  << A >>
Hi,

can you tell a little what kind of software versions besides MIG
you are using. Concerning the FIFO16 issues, this has been covered
within MIG V1.6 in the generated source code. Are you using VHDL
or Verilog?

Anyhow search for the Answer Record 22462 in the source code. You
will discover the fix being made in the src.

I have a board working for a customer with 6 DDR2 memories being
connected to a LX60 from Xilinx. It seems to work ;-)

However I use the older concept with the IDELAY logic to delay incoming
data from the DDR2 memory. As you have the option I don't see what
you have choosen so far.

Concerning your simulation problem, have you applied reset for the
DCM being involved?

In order to support you more, we need more info of how you did
use the MIG generated code in your design.

What MIG generates is something you may use as a starter.
However in my very personal opinion and experience with it, there is no 
way out, but you need to walk through all the code and try to understand 
what Xilinx does in its DDR2 controller design.
Then you may change things and make things easier ...

You can email me directly. Maybe I'am able to assist you.

Best Regards
Markus



waishanl@gmail.com schrieb:
> Joseph Samson wrote:
>> waishanl@gmail.com wrote:
>>> Hi! i am having problem to communicate between virtex4 fx60 to 512
>>> SODIMM. I use the MIG1.6 to generate a controller. I add one module
>>> into the design, change some names and run ModelSim. The simulation
>>> looks fine. So, i use the ICE tools to get my bit file. When i check
>>> all the report, I saw the map report have the follwoing message:
>>>
>>> WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please
>>> note that
>>>    there are additional requirements for the FIFO16 to guarantee full
>>>    functionality. For more information regarding requirements for the
>>> FIFO16
>>>    primitive, please see Answer Record 22462.
>>>
>>> is that going to cause me fail on the design? I didn't fine any .edn or
>>> ngc file in the folder that MIG generate.
>>>
>>> I also run the time simulation, it didn't match with the funcational
>>> simulation. Seems like signal start fail in 200ns. Am i missing
>>> anything?
>>>
>>> In addition, I chipscope the signal. It seems like data did get in the
>>> fifo. But the controller never request a read. Any ideas?
>> There has been quite a bit written lately about DDR2 and MIG in this
>> newsgroup. Search for ddr2 and MIG. I recommend replacing the FIFO16s
>> with FIFOs generated by CoreGen that don't use the FIFO16 primitive. I
>> had problems with the address/command FIFO. It would be empty, but still
>> indicate that it had data, so the same memory cycle would run forever.
>>
>> ---
>> Joe Samson
>> Pixel Velocity
> 

Article: 109616
Subject: Re: Anyone had success with MIG, DDR2 and V2Pro?
From: Markus Meng <meng.engineering@bluewin.ch>
Date: Sun, 01 Oct 2006 18:46:25 +0200
Links: << >>  << T >>  << A >>
Hi Greg,

I would suggest that you might check support.xilinx.com in the Answer
database. There are much more topics for DDR than for DDR2. I haven't
check all the IO capabilities, however the IO's do not have the same
possibilities in Virtex-2P as they have in Virtex-4.

For DDR as for DDR2 you need to in deep knowledge if the functionality
of the controllers. Use MIG as a starting point for your design, but
you need to go through in order to manage all the constraints that come
with it, for example IO-placment DCM, global buffers, Fifo's ... etc.

You also need to study the generated UCF-File, and check this influences
the remaining part of your design. IO-Bank constraints ...

For real designs, there is "No-Easy-Path" to DDR2 memory interface
designs ...

Markus

Greg Watson schrieb:
> Hi
> 
> We are planning to use MIG to generate a DDR2 interface for a V2Pro30 
> design, but I'd like to know if anyone has done this successfully 
> already? The MIG tool doesn't seem to have the quality level of other 
> Xilinx tools and that makes me a bit nervous for something as timing 
> critical as a DDR2 controller.
> 
> We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So 
> far the only irritations we have encountered is that it forces the use 
> of specific DCMs and requires the user to reselect every option each 
> time it is invoked (no saving of current design).
> 
> We plan to run 1 32 bit controller at 200MHz (400 Mb/s/pin) with Micron 
> MT47H16M16.
> 
> We would like to hear of any experiences with MIG and DDR2 and V2P, if 
> only to convince us that this is doable. Our final design should be open 
> sourced and available to all, if that encourages you to be open about 
> your experiences.
> 
> If you would rather contact me directly I am at gwatson@stanford.edu
> 
> Thanks
> 
> Greg Watson

Article: 109617
Subject: Re: Are you ready for Virtex-5? We are...
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 1 Oct 2006 09:46:34 -0700
Links: << >>  << T >>  << A >>
Thank you for that info.
I will contact the right people in Xilinx, and will try to streamline
this process.
There is no reason to run potential (or real) customers through such an
agony.
Thanks again.
Peter Alfke, from home.
=============================
zwsdotcom@gmail.com wrote:
> Peter Alfke wrote:
> > We are only interested in serious designers, not just "tire-kickers".
> > The registration is not a hurdle if you are serious.
>
> This is patently untrue. Choosing the right silicon for a new project
> is an immense task. Selecting the micro for even a small job (except in
> special cases) requires me to generate a mountain of paperwork. I have
> to show a matrix of choices, pro/con points, cost targets, how that
> will affect the BOM of the board, expected EMI issues, first-order
> approximation of power budget, etc.
>
> A vendor who puts me through 20 minutes of registration (especially on
> Xilinx's bouncy servers - here one second, down the next - and
> braindead browser requirements "you must be running IE6 from Win XP SP2
> and you must have the patches up to 9/1/2005 installed BUT NOTHING
> LATER, and you must have all security disabled and some unstated
> ActiveX control installed") is going to be kicked into the "too hard"
> pile immediately.
>
> Special case exceptions I referred to above are projects that will
> reuse a lot of code from an existing device, so the micro choice is
> constrained.


Article: 109618
Subject: Re: Are you ready for Virtex-5? We are...
From: Austin Lesea <austin@xilinx.com>
Date: Sun, 01 Oct 2006 10:31:56 -0700
Links: << >>  << T >>  << A >>
zwsdotcom,

I agree with Peter, it should not be that hard.  I use Mozilla, and 
mostly Firefox as browsers.  And, as long I enable cookies for the 
Xilinx site, I have not had any issues.  But I believe you that you have 
had a bad experience in the past.  I trust Peter to look into it.

Austin (on the road - presented at RADECS 2006 in Athens,Greece.  Now in 
France to look in on our SEU eperimental platforms.

Austin

> Peter Alfke wrote:
> 
>>We are only interested in serious designers, not just "tire-kickers".
>>The registration is not a hurdle if you are serious.
> 
> 
> This is patently untrue. Choosing the right silicon for a new project
> is an immense task. Selecting the micro for even a small job (except in
> special cases) requires me to generate a mountain of paperwork. I have
> to show a matrix of choices, pro/con points, cost targets, how that
> will affect the BOM of the board, expected EMI issues, first-order
> approximation of power budget, etc.
> 
> A vendor who puts me through 20 minutes of registration (especially on
> Xilinx's bouncy servers - here one second, down the next - and
> braindead browser requirements "you must be running IE6 from Win XP SP2
> and you must have the patches up to 9/1/2005 installed BUT NOTHING
> LATER, and you must have all security disabled and some unstated
> ActiveX control installed") is going to be kicked into the "too hard"
> pile immediately.
> 
> Special case exceptions I referred to above are projects that will
> reuse a lot of code from an existing device, so the micro choice is
> constrained.
> 

Article: 109619
Subject: Re: Are you ready for Virtex-5? We are...
From: zwsdotcom@gmail.com
Date: 1 Oct 2006 10:59:02 -0700
Links: << >>  << T >>  << A >>

Austin Lesea wrote:

> I agree with Peter, it should not be that hard.  I use Mozilla, and
> mostly Firefox as browsers.  And, as long I enable cookies for the

I've never seen anything approaching a reasonable explanation.
xilinx.com simply Does Not Work properly from where I'm sitting. MSIE,
Firefox, Safari on a Mac, Mozilla on a Linux box - NONE of them worked
properly for me.

And results are distinctly varied, as you've seen from the responses in
that thread I posted. People for whom it doesn't work, like me, REALLY
have ENORMOUS trouble getting in. People for whom it "just works" seem
to have no trouble even if they switch to a different browser.

Maybe Xilinx runs some load-balancing system that bounces visitors to
different mirrors according to their geographical location, and maybe
one or more of the mirrors is broken.

All this is a bit moot anyway. Xilinx has no rational reason to make
people jump through these flaming hoops to get basic information about
their parts. If they want people to go with other vendors whose
procedures are less broken, they're going the right way about it.


Article: 109620
Subject: Re: Migration from Spartan-2E to Spartan-3E
From: John_H <newsgroup@johnhandwork.com>
Date: Sun, 01 Oct 2006 18:08:40 GMT
Links: << >>  << T >>  << A >>
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
> John_H <newsgroup@johnhandwork.com> wrote:
>> pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
>>>> I think S2 had tristate buffers but not S2E; either way, S3 and S3E 
>>>> don't have them.  Memory blocks are now larger and DLLs are more 
>>>> functional as DCMs, both have "compatibility modes" for older designs. 
>>>> There's no longer a power-on surge.  You also have new, cheaper 
>>>> programming ROM options.
>>> Are you sure the power-on surge is gone ..?, so far what I have seen this
>>> issue is on Spartan-3/3E aswell.
> 
>> There are power on requirements, indeed.  Simply not the 4x operating 
>> current (wild estimate, unsubstantiated) of previous parts.  I haven't 
>> taken a current probe to my well-behaved boards, however.  The 
>> fundamental problem with the older parts was addressed in the silicon.
> 
> What's the power-on requirements for Spartan-3/3E 200-400k chips then..?
> I read a some power supply design documents. Seemed like a mess.. ;)

There aren't Iccpo values published in the data sheets any more because 
the power up requirements are captured within the quiescent maximum 
values on the data sheet.

Check out the TechXclusives article Austin Lesea wrote "back in the day"


http://tinyurl.com/pfaef

or the longurl version:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=al_power


While there may not be a large amount of "data" in this article, it 
addresses the issue that was and where it is now.  If you need more 
specifics, I'm sure you can get it directly from Xilinx, perhaps even 
Austin.  If you maintain the correct supply ramp rates with the 
Spartan3/L/E/A devices (touched on in that article and in some other 
Answers Database notes) you should have no surge issues.

Article: 109621
Subject: Re: System ACE woes
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 1 Oct 2006 11:34:31 -0700
Links: << >>  << T >>  << A >>
Antti wrote:
> the first partition must be FAT16, windows selects FAT32 as default
> try reformatting with FAT16 (select FAT in format options)

Thanks Antti, I should have known better.

In my defense, "FAT" is the only option presented to me, but I should
obviously format it in Linux.

Any help with the original problem?

Thanks,
Tommy


Article: 109622
Subject: Re: Are you ready for Virtex-5? We are...
From: John_H <newsgroup@johnhandwork.com>
Date: Sun, 01 Oct 2006 19:51:06 GMT
Links: << >>  << T >>  << A >>
zwsdotcom@gmail.com wrote:
> All this is a bit moot anyway. Xilinx has no rational reason to make
> people jump through these flaming hoops to get basic information about
> their parts. If they want people to go with other vendors whose
> procedures are less broken, they're going the right way about it.


Are errata considered at least *slightly* sensitive information?  It's 
true that people can falsify registration information to get the info, 
but those getting the errata (as opposed to the data sheet) should agree 
to some specific issues regarding the errata; a good way to track that 
the agreement was accepted is with a registration.

While I understand there should be nothing like the experience you've 
seen to stand between an engineer and an errata, should this information 
be made available without condition?  Ar is it just that the hoops 
should be simpler?

Article: 109623
Subject: spartan 3E starter kit : usb/jtag write cmdbuffer failed
From: rponsard@gmail.com
Date: 1 Oct 2006 13:22:17 -0700
Links: << >>  << T >>  << A >>
I am testing uclinux with microblaze (as explain in
http://muranaka.info) on spartan 3E starter kit (digilent rev. D) and
have configuration nightmare.

tools : ISE 81 EDK 81 /  window XP (Xilinx EDK 8.1.02 Build EDK_I.20.4)
PC : usb host controler is a via vt6212

I can download design to fpga (i.e. implementation/donload.bit, and
numerous other .bit files) but
I can't download  uclinux image into ram : "write cmdbuffer failed"

I already test with 3 other usb cables, an other usb host controler (I
had to buy a new one because with the one integrated to asus mb K8VSE,
Impact didn't succeed even to enumerate devices on board) ... any ideas
...

(I hope ISE/EDK 82i I am dowloading has a patch...)


xmd console
-=-=-=-=-=-=-

Checking cable driver.
 Driver xusbdfwu.sys version: 1018 (1018).
 Driver windrvr6.sys version = 7.0.0.0.Calling setinterface num=0,
alternate=0.
DeviceAttach: received and accepted attach for:
  vendor id 0x3fd, product id 0x8, device handle 0x27b0038
 Max current requested during enumeration is 280 mA.

----------------------------------------- IS 280mA NOMINAL (muranaka
has only 150 mA ?????)

 Cable Type = 3, Revision = 0.
 Setting cable speed to 750 KHz.
Cable connection established.
Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 0006h.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       01c22093           6        XC3S500E
 2       05046093           8        XCF04S
 3       06e5e093           8        XC2C64A_VQ44_1532
Assuming, Device No: 1 contains the MicroBlaze system
Connected to the JTAG MicroProcessor Debug Module (MDM)
No of processors = 1

MicroBlaze Processor 1 Configuration :
-------------------------------------
Version............................4.00.a
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0x22000000
Instruction Cache High Address.....0x23ffffff
Data Cache Support.................on
Data Cache Base Address............0x22000000
Data Cache High Address............0x23ffffff
Exceptions  Support................off
FPU  Support.......................off
FSL DCache Support.................off
FSL ICache Support.................off
Hard Divider Support...............off
Hard Multiplier Support............on
Barrel Shifter Support.............off
MSR clr/set Instruction Support....off
Compare Instruction Support........off
Number of FSL ports..............1
MBsfsl(0)-MDMmfsl(0) Connected..........Yes
JTAG MDM Connected to MicroBlaze 1
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD%


downloading image.bin
-=-=-=-=-=-=-=-=-=-=-=

XMD% dow -data images/image.bin 0x22000000
write count != nBytes(0), rc = C0000011.
write cmd failed C0000011.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
XMD%


Article: 109624
Subject: Re: Are you ready for Virtex-5? We are...
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 1 Oct 2006 13:32:38 -0700
Links: << >>  << T >>  << A >>
Yes, errata are somewhat sensitive information. Different from the
usual marketing spiel, they admit and explain warts. But that's life,
and microprocessors have paved the way to consider errata as facts of
life..
Our PR folks may not like the idea that the "bad competiton" gets hold
of it, but that would really underestimate their cleverness. They get
it anyhow...
And I think the press has better things to do than run anybody's errata
up the flagpole.
So, there really is no rational reason to treat  errata like a state
secret...
Peter Alfke, from home.
========================
John_H wrote:
> zwsdotcom@gmail.com wrote:
> > All this is a bit moot anyway. Xilinx has no rational reason to make
> > people jump through these flaming hoops to get basic information about
> > their parts. If they want people to go with other vendors whose
> > procedures are less broken, they're going the right way about it.
>
>
> Are errata considered at least *slightly* sensitive information?  It's
> true that people can falsify registration information to get the info,
> but those getting the errata (as opposed to the data sheet) should agree
> to some specific issues regarding the errata; a good way to track that
> the agreement was accepted is with a registration.
>
> While I understand there should be nothing like the experience you've
> seen to stand between an engineer and an errata, should this information
> be made available without condition?  Ar is it just that the hoops
> should be simpler?




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