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Add a series-resistor in the lines and/or use the current-limiting feature of the I/O-ports (if available). (too reduce the slopes of the signals) Kind regards, Stef? "Dolphin" <Karel.Deprez@gemidis.be> schreef in bericht news:1159368842.453549.244660@b28g2000cwb.googlegroups.com... > Hello, > > In my future design I could win a lot of pins if I could drive a bus at > 160MHz. Because of bank restrictions and because this bus is connected > to a CPLD, I will have to use LVTTL. > Has anybody tried driving a bus in LVTTL at 160MHz? > > I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has > LVDS CPLDs but only the large CPLDs support LVDS inputs. > > I am afraid that this bus will have a lot of EMI/EMC problems. What do > you think of it, should series termination be adequate to limit the > EMI/EMC problems? > > best regards, > Dolphin >Article: 109701
Well I did say look-alike I didn't say the same. It looks the same to the Xilinx software so it can use it without issue. Prog2 actually performs very well against the competition and works in circumstances where many others fail. We have tried several of these in compatibility testing with our own boards. Our Prog2 isn't as good as Cable IV but then it is about 1/5 th of the price when buying and we do give them away with our own development boards. John Adair Enterpoint Ltd. John_H wrote: > I don't see where the "Parallel Cable III look-alike" PROG2 is 2.5V > compliant since the Parallel Cable III doesn't work so well from 2.5V. > > I think I've gotten the III to work with a 3.3V supply for 2.5V JTAG but > the IV or USB versions of the cable are certainly more robust. > > Perhaps the Xilinx online store could ship to Switzerland with a simple > credit card purchase. > > The Parallel Cable IV doesn't include schematics but it does show what > the input and output stages look like, easily replacing the simple > buffers in the Parallel Cable III which does have full schematics. > > - John Handwork > > > John Adair wrote: > > Markus > > > > Our Prog2 cable(ask for narrow head version) is available in the standa= rd 14 > > way 2mm connector. Cost GBP=A310. It is a Cable III look-alike as most = third > > party cables are. Schematics for Cable IV are generally not in public d= omain > > and generally not replicated by anyone as far as I know. > > > > The only advantage of the Cable IV is the download speed. > > > > Our shop website has those listed under programming solutions for an ea= sy > > order solution. > > > > John Adair > > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > > Board. > > http://www.enterpoint.co.uk > > > > "Markus Zingg" <m.zingg@nct.ch> wrote in message > > news:ahn4i25ir1pnpqbol22na85ggkrjeoam3m@4ax.com... > >> Hi group > >> > >> I'm a newbee, so please bear with me if this does not make sense. > >> > >> I got a AVNet (MEMEC) Virtex 4 based developper kit based on the > >> Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as > >> "a 2.5V compatible JTAG chain header". The pinout is identical to what > >> Xilinx seems to use (14 pins etc.). The docs seem to asume that one > >> must use the Xilinx parallel cable IV which from what I understand > >> seems to automatically sense the voltage needs of the target and is > >> having other nice to have features. However, due to several reasons > >> which are beond the scope of this post, I can't simply pick up the > >> phone and order one from a supplier last not least also because I > >> don't know any that would carry this item here in Switzerland. > >> > >> The net seems to be full of homebrew JTAG cable websites giving > >> instructions to build you own. The question is can I use one of those? > >> I'm a bit afraid that this will not work cause from what I understand > >> they seem to be designed for 5V or 5V tolerant devices. What other > >> options do I have? Any links to a schema of the Xilinx paralell cable > >> IV or such to build my own JTAG cable running at 2.5V? > >> > >> I would also not mind to shell out the needed $$$ to get that original > >> cable if I could easily purchase it somewhere online using paypal or a > >> credit card and get it deliverd quickly. Any ideas? > >> > >> TIA > >> > >> MarkusArticle: 109702
Hi, Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze Development Kit in european union ?? (DO-ML403-EDK-ISE, http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Intellectual+Property&category=&iLanguageID=1&key=DO-ML403-EDK-ISE ) I tried via XIlinx on-line store but since their products are not RoHS compliant it's not possible to ship it to EU. Thanks, MarcinArticle: 109703
Austin Lesea wrote: > Agreed, > > A Toulouse, > > Austin > > > Peter Alfke wrote: > >> Yes, errata are somewhat sensitive information. Different from the >> usual marketing spiel, they admit and explain warts. But that's life, >> and microprocessors have paved the way to consider errata as facts of >> life.. >> Our PR folks may not like the idea that the "bad competiton" gets hold >> of it, but that would really underestimate their cleverness. They get >> it anyhow... >> And I think the press has better things to do than run anybody's errata >> up the flagpole. >> So, there really is no rational reason to treat errata like a state >> secret... >> Peter Alfke, from home. >> ======================== >> John_H wrote: >> >>> zwsdotcom@gmail.com wrote: >>> >>>> All this is a bit moot anyway. Xilinx has no rational reason to make >>>> people jump through these flaming hoops to get basic information about >>>> their parts. If they want people to go with other vendors whose >>>> procedures are less broken, they're going the right way about it. >>> >>> >>> >>> Are errata considered at least *slightly* sensitive information? It's >>> true that people can falsify registration information to get the info, >>> but those getting the errata (as opposed to the data sheet) should agree >>> to some specific issues regarding the errata; a good way to track that >>> the agreement was accepted is with a registration. >>> >>> While I understand there should be nothing like the experience you've >>> seen to stand between an engineer and an errata, should this information >>> be made available without condition? Ar is it just that the hoops >>> should be simpler? >> >> >> I must also agree. Here's my view as a system designer: 1. Errata are a fact of life in silicon. I have never met a device in the last 10 years that did not have errata against it. 2. If the device itself has no NDA requirement, then neither should the errata. The press _might_ make a meal of it, but probably not; designers expect it - indeed we welcome it because it makes our life easier if we know about issues. That said, make it easy for me to design something in at the hardware level (easier than your competition) and I will live with other issues. Compiler / PAR etc., can be dealt with if I can at least design with the part, but that requires full disclosure at the time I am designing. If Xilinx makes it difficult for me to find that info, then I won't design with their parts - nothing personal, but that's the way it is. I have rejected certain vendors because they won't provide me with what I consider sufficient information _without jumping through hoops_ to design their parts. I like Xilinx parts - indeed, a friend of mine used to be a Xilinx employee doing IP cores (and may still be for all I know), and that colours my view :) So please - do the right thing and just make it open on the same page as the basic docs. (A lot of others do) Cheers PeteSArticle: 109704
Jim Wu wrote: > vlib my_cores > vlog -work my_cores core0.v > > HTH, > Jim > http://home.comcast.net/~jimwu88/tools/ > > > Weng Tianxiang wrote: > > Hi, > > I have a project that have many files generated by Xilinx > > CoreGenerator. > > > > Now I put all those vhdl files generated by Xilinx CoreGenerator into > > my project. > > > > I want to put those files that never change into a library monitored by > > ModelSim software. Hi Wu, I found the simplest way to create a library for a project while using ModelSim: 1. Put all necessary *.vhd files into one proejct directory; 2. Compile them without errors; 3. Delete all *.vhd files that are generated by Xilinx CoreGenerator or something similar; These deleted *.vhd code are still referenced properly in the work library and there are no need to generate a separate library. Any comments? Thank you. Weng > > > > I don't know how to create a ModelSim library. > > > > Please help. > > > > Thank you. > > > > WengArticle: 109705
Jim Wu wrote: > vlib my_cores > vlog -work my_cores core0.v > > HTH, > Jim > http://home.comcast.net/~jimwu88/tools/ > > > Weng Tianxiang wrote: > > Hi, > > I have a project that have many files generated by Xilinx > > CoreGenerator. > > > > Now I put all those vhdl files generated by Xilinx CoreGenerator into > > my project. > > > > I want to put those files that never change into a library monitored by > > ModelSim software. > > > > I don't know how to create a ModelSim library. > > > > Please help. > > > > Thank you. > > > > WengArticle: 109706
Johan Bernspång wrote: > Hi all, > > I'm about to convert the amplitude output from a Cordic to dB, > 20*log(amp) that is. The output from the Cordic is 24 bits wide, the > maximum value would thus be approximately 144.5 dB. It is sufficient > with 12 bits resolution on the logarithm, 8 integer bits and 4 > fractional bits. > > My idea is to create a look-up table out of BRAM in the FPGA, and since > I want 12 bits resolution the size should not be larger than 2312 words > (the largest value is 10010000.0111 which is equal to 2311 if the binary > point is removed) each 12 bits wide. The problem has proved to be to > create a clever address function though. > > Any thoughts or ideas I have forseen? I'm sure this has been done > before, but some Googling didn't really help me in the right direction. > > Regards Left shift the CORDIC output to get the first '1' bit into the left most position, keeping track of how many bit positions you shift. Each shift is 6dB. The residue that is left has the MSB always '1' so it can be discarded (it is implied), and then use as many MSBs of the remaining residue to address a smaller table. Add the number of bit shifts * 6dB to the table output to get your complete log. A 4 bit look-up will get you to about 1/4dB, which is often sufficient. In that case, no BRAMs are used or harmed for testing the product :-)Article: 109707
I have a differential data stream going into the FPGA via two pins. The two signals, data_p and data_n, connect to an IBUFDS internally. Now, is it possible to route that single-ended data output from the IBUFDS to 4 different ISERDES modules? I have tried, but map gives errors about having the source to the D input of an ISERDES driving other loads. Apparently you can't do this. But I need that data signal to go to 4 independently clocked ISERDES setups. I am trying to do data recovery via 4 phased clocks. Is there any way to do this without routing 4 differential pairs into the FPGA? Apparently the maximum number of IBUFDS's you can drive with the same input is 2. thanks for any ideas.Article: 109708
Hi, I am trying to do the partial reconfiguration. I almost came to the final step which is place and route of the logic of the completely expanded design. After using this command: par -w top.ncd top_routed.ncd I meet this error: FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.3:286 - A previous module has placed the comp: Pim/myRegister/myRegister/PWR_VCC_0 on the same site: SLICE_X43Y159 where the current guide comp PWR_VCC_0 also needs to be placed. Please tell me what happens and how to fix it. Thank you so much for your time. Thang NguyenArticle: 109709
On 3 Oct 2006 13:36:56 -0700, "czeczek" <czeczek@gmail.com> wrote: >Hi, >Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze >Development Kit in european union ?? (DO-ML403-EDK-ISE, >http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Intellectual+Property&category=&iLanguageID=1&key=DO-ML403-EDK-ISE >) >I tried via XIlinx on-line store but since their products are not RoHS >compliant it's not possible to ship it to EU. > >Thanks, >Marcin Avnet/Memec sell in EU. ZaraArticle: 109710
>Avnet/Memec sell in EU. True, but the RoHS issue is a serious one. Many developement boards simply are not yet RoHS redy and those are not available by Avnet/Memec (or any other distribution) in the EU because it's simply not legal for them to sell non complying boards. To the OP, how about ordering the board from Xilinx online store and have it shipped to a non EU location? HTH MarkusArticle: 109711
Hi, I'm sending a TTL pulse-width modulated signal to an FPGA I/O pin with the hope of sampling it at 10 MHz to create a binary signal that can be processed digitally. What logic function in VHDL do I have to use to sample this signal at the I/O pin at that required speed? Hopefully this is simple. Thanks, AArticle: 109712
Andrew You need to pass this through a register or flip-flop to put the signal into you sampling frequency domain. You may get metastability oscillation effects on samples close to transition edges and a second flip-flop to sample the output of the first flip-flop is advisable before actual use in any designs. Your sample will have a jitter on pulse width of +/- 1clock on the real width so make sure your sample rate is high enough such that this jitter does not cause you issues. There are some links to useful web resources in our TechiTips part of our website here http://www.enterpoint.co.uk/techitips/techitips_useful_things.html including links to VHDL and Verilog tutorials and how to build designs. John Adair Enterpoint Ltd. Andrew Lohbihler wrote: > Hi, > > I'm sending a TTL pulse-width modulated signal to an FPGA I/O pin with the > hope of sampling it at 10 MHz to create a binary signal that can be > processed digitally. What logic function in VHDL do I have to use to sample > this signal at the I/O pin at that required speed? Hopefully this is simple. > > Thanks, > AArticle: 109713
Hi Thang Nguyen, are you using VCC-components in your bus-macros(*.nmc)? Don't include VCC-Blocks in bus-macros. Regards Jens THANG NGUYEN schrieb: > Hi, I am trying to do the partial reconfiguration. I almost came to the final step which is place and route of the logic of the completely expanded design. After using this command: > > par -w top.ncd top_routed.ncd > > I meet this error: FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.3:286 - A previous module has placed the comp: Pim/myRegister/myRegister/PWR_VCC_0 on the same site: SLICE_X43Y159 where the current guide comp PWR_VCC_0 also needs to be placed. > > Please tell me what happens and how to fix it. > > Thank you so much for your time. Thang NguyenArticle: 109714
Hi all I want to receive 70 MHz PM+BPSK modulated signal. Video bandwidth:138 kHz Modulation index for PM: 1.2 radian Subcarrier frequency of BPSK:65536 Hz. I have been using Matlab /Simulink and TMS320C6713 DSK. 1. I need suitable ADC daughtercard for C6713 DSK. 2. What is the sampling rate according to this spec.s? How can I calculate? I want to proof my calculation method. 3. These spec.s are for "satellite telemetry receiver". And also, I want to design "telecommand transmitter" for various spec.s of them: wider bandwidth higer data rates etc. Would you like to suggest me a set (DSK,ADC card, EVM...) which can be useful for all types of applications? tnxArticle: 109715
You mayt just go to this page and buy lots of xilinx boards within the EU: http://www.silica.com/en/products/evaluationkits/evaluationkits_xilinx.html Best regards, ZaraArticle: 109716
Go here for a list of local distributors: http://www.xilinx.com/company/sales/ww_disti.htm Cheers Markus Zingg wrote: > >Avnet/Memec sell in EU. > > True, but the RoHS issue is a serious one. Many developement boards > simply are not yet RoHS redy and those are not available by > Avnet/Memec (or any other distribution) in the EU because it's simply > not legal for them to sell non complying boards. > > To the OP, how about ordering the board from Xilinx online store and > have it shipped to a non EU location? > > HTH > > MarkusArticle: 109717
Hello again experts, Thanks for all the suggestions and help. I have partially understood the test bench of PCI core and was able to write my own task of PCI transaction from PCI bridge (configured as guest) to one of the behavorial model of PCI device written in test bench. Now here is the problem. I want to write data from the master of bridge to its OWN target and read written data back. This might sound stupid but this is what I have to do. Please tell is it possible or not. IMHO it is possible. I have tried to do it in the following way but failed. 1. I have configured all the PCI target images. 2. I just called the task wb_single_write with target_address = `TAR0_BASE_ADDR_2. 3. But target did not accept the data which was sent to it. I am trying to figure it out but failed. Please, Please help me to accomplish this task. If someone wants, I can send him the test bench which I have written. Your timely help will greatly help me to solve my problems. With best regards AdnanArticle: 109718
in order not to reinvente the wheel is there a free and publicly available CAN protocol IP for microblaze/EDK (8.1 eval. version) ? or does somebody port the one in opencores into an IP for EDK 8.1 ? thanksArticle: 109719
rponsard@gmail.com schrieb: > in order not to reinvente the wheel is there a free and publicly > available CAN protocol IP for microblaze/EDK (8.1 eval. version) ? > > or does somebody port the one in opencores into an IP for EDK 8.1 ? > > > thanks no there isnt anttiArticle: 109720
Hi Andrea,
> Herein I'll refer to the Xilinx world: EDK, Microblaze as
> microprocessor, XC2v1000 as FPGA and XC18V04 as ISP PROM.
Thanks; that is useful to know.
> Thinking on the section on a PROM (configuration, SW, User Data), I
> wonder how these sections are filled.
> ...
> I believe there is a way to use the FPGA resource almost only for the
> "HW" and to use other external devices for storing data/program.
> I'm still a little bit confused...
First of all let's look at your system and how it works. The XC18V04 device
is a specially-designed PROM that knows how to use the configuration data
that's stored within it to initialize an FPGA. It doesn't know anything
about what the FPGA does, whether the FPGA has a processor inside it,
whether you are running software, or anything like that. It just "brings up"
the FPGA at startup.
The second thing to note is that the FPGA is pretty much unaware that the
XC18V04 exists in the system at all. By the time the FPGA is operational,
i.e. the clocks are running and it's out of reset, the PROM has played its
part and the FPGA cannot (and does not need to) access its contents.
So where is the software code that the Microblaze core is running, then? In
your case, I think the answer is that it's inside some of the Block RAM
resources of the FPGA. While the PROM is initializing the FPGA, one of the
tasks it performs is to initialize the contents of all the memories inside
it - the data for this is just another part of the FPGA configuration data.
Assume then that your application code fits completely inside the BRAM
resources in the FPGA. What EDK does in this case is to take the hardware
bitstream (.bit) that is produced by the implementation tools, and take the
application binary (.elf) produced by the compiler, and fill in the
appropriate memories in the former with data from the latter. The resulting
bitstream is "self-contained" and will run your application as soon as the
FPGA is configured and running.
What happens if your application is bigger than the BRAM resources available
in the FPGA? The technique described above won't quite work in that case;
you will need some other non-volatile storage to hold the application
program, or you'll have to find some other way to provide it to the FPGA.
The XC18V04 isn't suitable for storing anything other than an FPGA ("HW")
image alone.
Also, you will most likely require some external volatile storage attached
to the FPGA, so there is sufficient space for the program's variables,
stack, heap etc. Your system may already have such external memories
attached to the FPGA - you'd have to check the manual/schematics or look
around on the circuit board for chips that look like flash/SRAM/SDRAM.
It is certainly true that using external memories for your application will
often allow you to use a smaller FPGA device, since the BRAM resources are
probably the limiting factor (and buying and FPGA is a very expensive way to
buy memory!). The XC2V1000 has 40 x 18kbit block RAMs, or 80KBytes. Assuming
that all this memory is available to the Microblaze processor, this should
be enough for a modest control algorithm. But for more sophisticated
applications it might not be enough.
> Do you know some good site/book/document that can help me?
Unfortunately, I have to say no! Most people seem to learn all these things
"on the job" as you're doing right now. I'm sure there are introductory
texts on embedded systems which will talk about memory selection and system
design issues for microprocessor and microcontroller applications, although
they may not mention FPGAs explicitly. So, you are probably best off just
asking lots of questions!
Hope this helps.
Cheers,
-Ben-
Article: 109721Thank Jens, Actually I use the bus macro bm_4b_v2p.nmc in the folder \bus_macros\angle_delimiter of the axemple xapp290 of Xilinx because I use the ML310 with the FPGA Virtex II Pro. As your recommend, should I recreate the bus macro? Thank so much for your time. Thang NguyenArticle: 109722
Hi, As I know, there is not VCC-Blocks in the bus macro. Is this the problem about bus macro? Or the broblem of the module myRegister? Thanks Thang NguyenArticle: 109723
hello i am a student, working on development kit nios 2 cyclone edition. i want to use the logic analyzer to import data to the fpga from the logic analyzer, can i do it?Article: 109724
> I found the simplest way to create a library for a project while using > ModelSim: > 1. Put all necessary *.vhd files into one proejct directory; > 2. Compile them without errors; > 3. Delete all *.vhd files that are generated by Xilinx CoreGenerator or > something similar; > > These deleted *.vhd code are still referenced properly in the work > library and there are no need to generate a separate library. > > Any comments? Not sure what you're trying to do. If you just want to avoid re-compiling the core libraries, you don't have to delete the source files. What you can do is to do the compile in two steps: vlog -f my_core_files vlog -f my_design_files If you make any changes to your design files, you only need to run the second step. HTH, Jim http://home.comcast.net/~jimwu88/tools/ > > > Weng
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Compare FPGA features and resources
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