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Messages from 109825

Article: 109825
Subject: Re: System ACE woes
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 05 Oct 2006 15:42:39 -0700
Links: << >>  << T >>  << A >>
Tommy Thorn wrote:
> Siva Velusamy wrote:
>> In the majority of cases, the issue is improper formatting of the CF. So
>> did you try again after reformatting? (Use Linux or mkdosfs to format).
> 
> Yes indeed. After a mkdosfs -F16 under Linux and a fresh copy of the
> reference CF, the demos worked again.  Unfortunately, the original
> problem remains: I can't seem to create .ace files myself, ie. I
> followed what seemed to be straight forward steps to transform my
> design to an .ace file, but after copying it to the CF card,
> overwriting one of the demos, the .ace file doesn't load (instead
> lights up the Err LED).
> 
> Thanks,
> Tommy
> 

The most likely problem that you are is that you are not setting up the
chain correctly.  If you have only the 4VLX25 in the chain with a bit
file attached to it, this is wrong.  You need to describe the chain as
seen from the System ACE part in iMPACT correctly or the ACE file won't
work as it has no information as to what device it is supposed to be
downloaded into.

ML401
-----
   Device #0 XCF32P
   Device #1 XC4VLX25     <- Assign bit file here
   Device #2 XC95144LX

And make sure that you are using 8.1i-SP3 or above as there were some
issues with V-4 support in earlier versions.

This was covered in a recent thread
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/b734e6591d700376/e80ce592bf58ea4c?lnk=gst&rnum=3#e80ce592bf58ea4c

Ed McGettigan
--
Xilinx Inc.

Article: 109826
Subject: Re: An implementation of a clean reset signal
From: "Andrew FPGA" <andrew.newsgroup@gmail.com>
Date: 5 Oct 2006 15:46:02 -0700
Links: << >>  << T >>  << A >>
> The next question to ponder is, given that the reset must be synchronized
> anyway, why use an asynchronous reset anywhere in your design (with the
> exception of course of the above mentioned synchronizer)?

A purely synchronous reset requires the clock to be running for the
reset to take effect.  The async initiated reset can still initiate the
reset even though the clock may have stopped (for whatever reason).

The xilinx primitives library shows async and sync reset flops - I was
under the impression there is no performance difference between the two
for current generation Xilinx FPGA families?
 
Regards
Andrew


Article: 109827
Subject: Re: BSD indi processor IP compiles at ($13.30)
From: "jacko" <jackokring@gmail.com>
Date: 5 Oct 2006 16:11:02 -0700
Links: << >>  << T >>  << A >>
hi

MAX II EPM570T100C5 just fits at 68% utilization.
altera quotes $13.30 per chip. If i can get io in there, and possibly
change the way interrupts are done then bingo. 512 x 16 bit eeprom
onboard and an external ram and rom.

jacko wrote:
> jacko wrote:
> > hi
> >
> > 283 LEs
> > 6% Cyclone II EP2C5T144C6
> > 44 Warnings
> > Still unverified.
>
> just retargeted to MAX II to see how it went. looks good.
> 386LEs
> 17% MAX II EPM2210F256C3
>
> > yes got it to compile at last after discovering a bit more about buses
> > and naming of them.
> >
> > TEST16 toplevel object schematic encapsulates the indi16 with reset
> > logic and tristate databus, to connect with external pins on the chip.
> >
> > Hopefully not a lot more editing needs to be done for the basic design,
> > and i am now in a position to start puting together more architecture
> > documentation.
> >
> > cheers
> >
> > p.s. the cpu is suitable for having a C compilier written for it and
> > will not be limited to forth.
> >
> > http://indi.joox.net
> > http://indi.microfpga.com
> > http://indi.hpsdr.com
> > 
> > all three url work but some do not have directory listing yet.


Article: 109828
Subject: .ise project files, episode N+1
From: "Brian Davis" <brimdavis@aol.com>
Date: 5 Oct 2006 17:25:54 -0700
Links: << >>  << T >>  << A >>
johnp recently wrote:
>
>Yet again I've had to completely re-build a project because
>Navigator corrupted the .ise file and the backup version.
>

  Although the "right" answer probably is to use a makefile,
I recently noticed the following Answer Records regarding the
use of external text files to import/export all XST HDL source files:

 Answer Record: 23141
   8.2i XST - "ERROR:HDLParsers:3501 - Circular dependency is
               not supported!"
   see the "Creating a Custom Compile File for Synthesis" section

 Answer Record: 23672
   8.2i ISE - Is there a way to list of all source files in an ISE
project?

Also, some earlier .ise recovery notes from
http://groups.google.com/group/comp.arch.fpga/msg/17c09b2f9d4df197
>
>If you haven't already spotted them, here's a few things that can help
>with the #$%&^! .ise file problems:
>
> - there's a tcl script mentioned in Answer Record 21067 that converts
>   from .ise <-> ASCII dump
>
> - try using the .ise_ISE_Backup file when the .ise has been corrupted
>
> - for the registry key to edit to prevent opening last project, see :
>   Answer Record: 20892  8.1i ISE - Project Navigator hangs at startup
>   and project does not open 
>

Brian


Article: 109829
Subject: Re: BSD indi processor IP compiles at ($13.30)
From: "jacko" <jackokring@gmail.com>
Date: 5 Oct 2006 17:26:36 -0700
Links: << >>  << T >>  << A >>

jacko wrote:
> hi
>
> MAX II EPM570T100C5 just fits at 68% utilization.
> altera quotes $13.30 per chip. If i can get io in there, and possibly
> change the way interrupts are done then bingo. 512 x 16 bit eeprom
> onboard and an external ram and rom.

Changed design to only mirror P reg on super/user interrupt toggle pin,
and got down to 303 LEs in the MAX II EPM570T100C5. This gives more
free space for IO and control.

> > > TEST16 toplevel object schematic encapsulates the indi16 with reset
> > > logic and tristate databus, to connect with external pins on the chip.
> > >
> > > Hopefully not a lot more editing needs to be done for the basic design,
> > > and i am now in a position to start puting together more architecture
> > > documentation.
> > >
> > > cheers
> > >
> > > p.s. the cpu is suitable for having a C compilier written for it and
> > > will not be limited to forth.
> > >
> > > http://indi.joox.net
> > > http://indi.microfpga.com
> > > http://indi.hpsdr.com
> > >
> > > all three url work but some do not have directory listing yet.


Article: 109830
Subject: Spartan 3 Starter Kit I/O ports
From: "vu_5421" <nugentoffer@gmail.com>
Date: 5 Oct 2006 17:44:56 -0700
Links: << >>  << T >>  << A >>
Hello,

I am relatively new to VHDL design, and I bought this board as a first
time learning kit.

I was mainly interested in the I/O expansion connector for this board.
It appears that the connector has both 3.3V and 5V outputs. If I had
wanted to interface the board with a PS/2 port for example (which uses
5V logic levels), how can I force the Spartan board to output 5V logic
levels and not 3.3V output?

I'm not too sure if this is even possible since the FPGA's voltage
requirements is only 3.3v. 

Thanks for your help.


Article: 109831
Subject: Re: Just a matter of time
From: "rickman" <gnuarm@gmail.com>
Date: 5 Oct 2006 19:53:15 -0700
Links: << >>  << T >>  << A >>
Thanks Peter.  Of all the things a vendor can do to tick me off, spam
is pretty high on the list.  I would really appreciate any help in
getting Xilinx to stop this.

I once received similar junk email to an address I had given only to
Altera.  When I contacted them they had no idea how it was given out,
or at least that is what they told me.  So Xilinx is not alone.


Peter Alfke wrote:
> Rickman, you can be sure that I will chase this all the way up and down
> the Xilinx management chain!
> Peter Alfke, from home
>
> rickman wrote:
> > Over the years I have gotten a lot of junk email from Xilinx to email
> > addresses that I have given out only to support and never to any
> > marketing channel.  I have always been disappointed that Xilinx has
> > done this.  But now they have sunk to a new low, they are giving or
> > selling my email address to third party junk emailers.
> >
> > I guess I should not be surprised at this since it is getting to be the
> > norm rather than the exception.  Everyone seems to think it is
> > perfectly ok to post a non-"privacy" statement saying in typical
> > crypto-speak that they share your information with anyone that suits
> > them.  I have found that if I contact a vendor directly and say I want
> > to opt out of their "privacy" policy and they should not share my info
> > with anyone at all, they will honor this.  But why is this necessary?
> > Why can't a privacy policy be a PRIVACY policy and not a NON-privacy
> > policy?  
> > 
> > Am I alone in being irritated by these practices?


Article: 109832
Subject: Re: Virtex-II Pro Platform FPGA : Assembling the modules
From: "THANG NGUYEN" <airthang@yahoo.com>
Date: Thu, 5 Oct 2006 23:17:45 -0700
Links: << >>  << T >>  << A >>
Hi Jens, Thank you for your patience answering my questions. Your help is really important with me. I am very appreciate your answers.

I installed the Service Pack 3 for ISE 6.3i. After that I rebuild the system again. And when I came to the command:

par -w top.ncd top_routed.ncd

I meet a new error:

Loading device database for application Par from file "..\Pim/myRegister/myRegister.ncd". "top" is an NCD, version 2.38, device xc2vp30, package ff896, speed -6 FATAL_ERROR:Guide:basgitaskphyspr.c:333:1.28.20.4:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at <http://support.xilinx.com>. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at <http://support.xilinx.com>

Do I miss any package? Because I just found the SP3 for ISE 6.3i. The Early Access Partial Reconfiguration Suite is only support for ISE 8.1i, while I use ISE 6.3i.

Article: 109833
Subject: Design of a programmable delay line
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 5 Oct 2006 23:52:09 -0700
Links: << >>  << T >>  << A >>
Hello,

For a future project I need to design a programmable delay line. The
specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
PLLs left so I can't use a high-speed pipeline to design this. Note
that the delay should be fixed when temperature varies, this means that
I'll probably need some calibration.
I think that Xilinx uses something like this to delay the DQS signal in
the S3E DDR controller.
Has anybody got an idea how I should implement this?

best regards,
Dolphin


Article: 109834
Subject: Re: An implementation of a clean reset signal
From: "Eli Bendersky" <eliben@gmail.com>
Date: 5 Oct 2006 23:59:07 -0700
Links: << >>  << T >>  << A >>

Andrew FPGA wrote:
> > The next question to ponder is, given that the reset must be synchronized
> > anyway, why use an asynchronous reset anywhere in your design (with the
> > exception of course of the above mentioned synchronizer)?
>
> A purely synchronous reset requires the clock to be running for the
> reset to take effect.  The async initiated reset can still initiate the
> reset even though the clock may have stopped (for whatever reason).
>

This is an important point, which the synchronizer circuit I presented
addresses. Since the reset is asserted asynchronously (take a look at
the code), all flops will get into reset even if the clock isn't
working.


Article: 109835
Subject: Re: Design of a programmable delay line
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 06 Oct 2006 09:15:41 +0200
Links: << >>  << T >>  << A >>
Dolphin schrieb:
> Hello,
> 
> For a future project I need to design a programmable delay line. The
> specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no

Why reinvent the wheel? Such delay lines are available off the shelf.

Regards
Falk

Article: 109836
Subject: Re: An implementation of a clean reset signal
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 6 Oct 2006 00:15:44 -0700
Links: << >>  << T >>  << A >>
HI,

Eli Bendersky wrote:
> best and the safest way to use resets in FPGA designs is to use a
> special synchronizer circuit that assures that the reset of the FFs is
> asserted asynchronously, but is deasserted synchronously.
[..]
> What does this technique lack to be the perfect solution for resets in
> FPGA designs ? It seems that it evades all the common disadvantages of
> conventional sync and async resets.

I use this style, too. But this has a few (minor) disadvantages:
- It needs additional logic
- you need a good buffering as your signal has to be distributed to
every FF in the design within one clock cycle.
- it requires the possibility to drive the asynch. reset out of a FF.
This is normaly no problem, but if you use a dedicated clock routing to
have a fast distributed reset, you _might_ encounter a problem on
exotic fpgas.
- You have some work to do, if your design uses multiple clock domains.

- You have to think about scanchains (no problem for pure fpga designs,
but a bit harder for designs  targeting asic and fpga)
- the design needs at least one additional clock cycle to recover from
reset.  

bye Thomas


Article: 109837
Subject: Re: Design of a programmable delay line
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 6 Oct 2006 00:18:46 -0700
Links: << >>  << T >>  << A >>

Falk Brunner schreef:

> Dolphin schrieb:
> > Hello,
> >
> > For a future project I need to design a programmable delay line. The
> > specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
>
> Why reinvent the wheel? Such delay lines are available off the shelf.
>
> Regards
> Falk

These programmable delay lines are rather expensive.
Each IC counts for this design.

best regards,
Dolphin


Article: 109838
Subject: Re: Open protocol USB JTAG cable
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Fri, 06 Oct 2006 09:28:10 +0200
Links: << >>  << T >>  << A >>
goss wrote:
> Hi everybody,
> 
> I'm going to build a USB JTAG cable and I don't know what protocol
> should I use for communication. The only cable I can fully implement
> this time is the Digilent USB cable... (according to the code of Zoltan
> Csizmadia's cable server project)
> I was trying to reverse engineer Xilinx's USB Platform cable protocol,
> but after a point I gave up. (Mostly becouse the firmware of the cable
> is shipped with the PC software, so they can easily modify the protocol
> in the new version of ISE)
> 
> So, some questions:
> Is Digilent's protocol free to implement in my device?
> 
> Is there any cable with open protocol? (with a GPL like license)
> If exists an open protocol cable, is this well supported by
> applications?
> 
> Thanks,
>  goss
> 
Checkout JTAGkey and JTAGkey-Tiny from http://www.amontec.com .
Amontec will provide the jtagkey.dll very soon!
But you can still use the OpenOCD JTAG server, and it is GPL and fully 
supporting the JTAGkey products.
Note the JTAGkey products are based on FTDI FT2232!


Best regards,
LOL

Article: 109839
Subject: Instantiating Altera M4K block without MegaWizard
From: "RadioShox" <robert.leune@gemidis.be>
Date: 6 Oct 2006 00:44:44 -0700
Links: << >>  << T >>  << A >>
Hello,



I'm trying to write a VHDL video line buffer. I've done this several
times before, but this time I have to write ONE single entity for both
Xilinx and Altera. Selection of the RAM blocks for a design has to be
done using a generic, based on the brand of FPGA. This generic is used
in generate statements to toggle between RAM instances.

For Xilinx, there is no problem. I instantiate a RAMB16_Sm_Sn, and off
I go for a lot of Xilinx devices. I wrap a generate statement around
that and I'm done with the Xilinx job.

But now for Altera. I cannot find a instantiatable primitive called M4K
in the documentation. I really have to use the MegaWizard, which is
fine, but not for this design. Using the wizard would mean that I have
to do it over and over again for each new Altera design, and go through
simulation and verification every time. So there goes the idea of
switching between brands using an generic map.

Has somebody ever found an Altera primitive for internal RAMs?



Best regards,
RadioShox


Article: 109840
Subject: Re: Design of a programmable delay line
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 06 Oct 2006 09:46:34 +0200
Links: << >>  << T >>  << A >>
Dolphin schrieb:

> These programmable delay lines are rather expensive.
> Each IC counts for this design.

Hmm, did you do a rough calculation of part cost versus design cost? 
Such a delay line in a FPGA is not done on a sunny weekend.
What quantities are required?

Regards
Falk

Article: 109841
Subject: Re: Virtex-II Pro Platform FPGA : Assembling the modules
From: "Jens Hagemeyer" <jenze@et.upb.de>
Date: 6 Oct 2006 00:46:48 -0700
Links: << >>  << T >>  << A >>
Hi Thang,

installing a service pack is always a good idea. Seems like the links
on the archive site points to the new patch. You can use this link:

http://jenze.ancientspledge.com/xilinx_early_access_6

It contains the old patches for 6.3.03. As you can see in the
userguide, the final assembly phase has been replaced by the merge
phase. What prevents you from using the "new" patch for 8.1.01?

Regards

Jens

THANG NGUYEN schrieb:

> Hi Jens, Thank you for your patience answering my questions. Your help is really important with me. I am very appreciate your answers.
>
> I installed the Service Pack 3 for ISE 6.3i. After that I rebuild the system again. And when I came to the command:
>
> par -w top.ncd top_routed.ncd
>
> I meet a new error:
>
> Loading device database for application Par from file "..\Pim/myRegister/myRegister.ncd". "top" is an NCD, version 2.38, device xc2vp30, package ff896, speed -6 FATAL_ERROR:Guide:basgitaskphyspr.c:333:1.28.20.4:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at <http://support.xilinx.com>. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at <http://support.xilinx.com>
>
> Do I miss any package? Because I just found the SP3 for ISE 6.3i. The Early Access Partial Reconfiguration Suite is only support for ISE 8.1i, while I use ISE 6.3i.


Article: 109842
Subject: Re: Design of a programmable delay line
From: "Dolphin" <Karel.Deprez@gemidis.be>
Date: 6 Oct 2006 01:01:12 -0700
Links: << >>  << T >>  << A >>
Falk,

This design is for a consumer product. It is for big quantities
(10K/year).
Each dollar counts.
Do you know cheap delay lines? I've checked the maxim parts but they
are rather expensive.

best regards,
Dolphin


Article: 109843
Subject: Re: An implementation of a clean reset signal
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Fri, 6 Oct 2006 09:07:20 +0100
Links: << >>  << T >>  << A >>

"mk" <kal*@dspia.*comdelete> wrote in message 
news:9voai2t95dnijnajekg8734bkmbjbtd4n9@4ax.com...

> How about this: In an FPGA all the flops are already async (unlike
> ASICs) so you're getting hit by the potential slow setup, clk->q issue
> already so you might as well take advantage of it because going to
> sync reset will need a mux at the input.

This may have been true in the early '90s, but it's not true today. Any 
modern FPGA will have a dedicated set/reset input on every storage element 
that is configurable between synchronous and asynchronous operation. There 
is no size or speed penalty of using synchronous reset semantics in such a 
device.

There are a very few believable arguments for using asynchronous resets on 
certain I/O elements, depending on one's design and board-level 
requirements. I have never heard a credible excuse for using an async reset 
for any internal logic. I'm racking my brains to come up with some 
clock-domain-crossing circuit that needs one, but I still think the correct 
design practice in that case is to re-synchronize the reset into each clock 
domain separately...

Cheers,

        -Ben- 



Article: 109844
Subject: Re: BSD indi processor IP compiles at ($13.30)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 6 Oct 2006 01:20:01 -0700
Links: << >>  << T >>  << A >>
jacko schrieb:

> hi
>
> MAX II EPM570T100C5 just fits at 68% utilization.
> altera quotes $13.30 per chip. If i can get io in there, and possibly
> change the way interrupts are done then bingo. 512 x 16 bit eeprom
> onboard and an external ram and rom.
>
> jacko wrote:
> > jacko wrote:
> > > hi

MAX2 chips are WAY WAY WAY too expensive.
just compare the Lattice XP3 pricing and features.

MAX2 has no onchip ram, thats the major problem.

Antti


Article: 109845
Subject: Re: a clueless bloke tells Xilinx to get a move on
From: Kolja Sulimma <news@sulimma.de>
Date: Fri, 06 Oct 2006 10:20:48 +0200
Links: << >>  << T >>  << A >>
Brannon wrote:
> 2.	Use a different algorithm. I understand that the tools currently
> rely on simulated Annealing algorithms for placement and routing. This
> is probably a fine method historically, but we are arriving at the
> point where all paths are constrained and the paths are complex (not
> just vast in number). If there is no value in approximation, then the
> algorithm loses its value.  Perhaps it is time to consider a Branch and
> Bound algorithm instead. This has the advantage of being easily
> threadable.

Threading will gain you a factor of 4 at most in a quad core processor.
When doing placement algorithm development you are talking about orders of magnitude!
Branch and bound would probably be the slowest possible way to do placement.
I am talking billions of years here ;-)

Simulated annealing has the advantage that you can stop at any time just reducing the
quality of the result. There was a post here recently that showed how Xilinx tool run
time depends on the timing constraint set. The difference was larger than the factor of 4.

Anyway, you are right that simulated annealing is old school, but I am sure that ISE
start with some kind of constructive placer (quadratic or recursive bipartitioning)
and do not let the annealing do all the work. Just the refinement probably.

Actually Xilinx placement times are not bad compared to other tools.

Kolja Sulimma

(writing this while waiting for my computer to finish the benchmarks for my constant delay
asic placement PhD thesis)





Article: 109846
Subject: Re: Virtex-5 FX when ?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 6 Oct 2006 01:26:09 -0700
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:

> It is up to marketing to orchestrate product announcements and press
> releases, and I will not steal their thunder. As usual, Antti is pretty
> well informed...
> Peter Alfke

well I peek and poke and wonder ;)

some things are at least weird, like the thing with the PCI Express MAC
hard block in Virtex-5, its no secret as there are already two AR's at
Xilinx website

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23803

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23430

dealing with the PCI Express primitive in Virtex-5,
but where is the other information?

I am really excited!

Antti


Article: 109847
Subject: Re: Design of a programmable delay line
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 06 Oct 2006 03:43:53 -0500
Links: << >>  << T >>  << A >>

>Do you know cheap delay lines? I've checked the maxim parts but they
>are rather expensive.

> specifications are: steps of +/- 1 ns, range of 0 to 8 ns.

PCB traces are about 6 inches per ns.


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 109848
Subject: Re: Design of a programmable delay line
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 06 Oct 2006 10:44:36 +0200
Links: << >>  << T >>  << A >>
Dolphin schrieb:
> Falk,
> 
> This design is for a consumer product. It is for big quantities
> (10K/year).
> Each dollar counts.
> Do you know cheap delay lines? I've checked the maxim parts but they
> are rather expensive.

Sorry, I don't.

Regards
Falk

Article: 109849
Subject: Re: An implementation of a clean reset signal
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 06 Oct 2006 10:05:35 +0100
Links: << >>  << T >>  << A >>
"Ben Jones" <ben.jones@xilinx.com> writes:

> I have never heard a credible excuse for using an async reset 
> for any internal logic. I'm racking my brains to come up with some 
> clock-domain-crossing circuit that needs one

Hi Ben,

Does the flancter count? XCELL37, which doesn't seem to be on the
Xilinx site anymore... and Google isn't helping me find the original
place I saw it :-(

Anwyay, it's the only thing in my latest design that has one...

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

   



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