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That's why (as I posted earlier) all Xilinx FPGA asynchronously initiate all flip-flops as part of the initiating and configuration process, and also keep the outputs 3-stated until configuration is finished. Nothing new for you, Bob, but somebody else may have forgotten. Peter Alfke ==================== Bob Perlman wrote: > On Mon, 09 Oct 2006 00:04:37 GMT, "KJ" <kkjennings@sbcglobal.net> > wrote: > > > > >"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message > >news:1160349835.918930.124340@i42g2000cwa.googlegroups.com... > >>> If you take a step back and realize that you probably shouldn't expect > >>> anything useful out of a part that is not receiving the proper inputs yet > >>> (perhaps by design, after all it could be a power saving measure) then > >>> the > >>> outputs that do not actually reset themselves until the clock does start > >>> up > >>> is not really an issue. > >> > >> Ok but what if those FPGA outputs can cause problems for other parts of > >> the system, say if the FPGA is on a bus. Maybe there are some bus > >> protocols out there where the bus clock can stop, and the peripheral > >> needs to be able to be reset by the bus master?? > >Like I said, I don't discount that there may be these cases...but have yet > >to hear anyone actually name a specific case where the clock isn't running > >but a specific reset condition is required. > > > >Can anyone actually provide one? Hard to believe that such a case doesn't > >exist, but also hard to believe that one hasn't been articulated > >either....oh well. > > How about TriState contention? If I'm controlling TriState buffers > with FFs that aren't initialized until the clock comes along, I run > the risk of turning on more than one set of TriStates on a signal or > bus. And when you're using high-current drivers, this can cause > smoke; I've seen it. > > Bob Perlman > Cambrian Design Works > http://www.cambriandesign.comArticle: 109951
Peter Alfke wrote: > We do not need any speculation. Antifuse FPGAs have been around for 20 > years, Actel is the oldest supplier, Quicklogic the younger one. > The antifuse is a very small (lless than one cubic micron?) speck of > silicon that is normally an insulator, but becomes permanently > conductive when a certain (rather high) voltage and current is applied. > > The system advantages are "instant-on" (no configuration process), > inherent (but limited) security and a higher radiation tolerance. > The disadvantages that have relegated antifuses to a niche market, are > one-time-only (and very slow) programmability (now that designers have > become accustomed to reprogrammability, and volatility is no longer a > dirty word), the inability of complete testing, and a seemingly natural > max size limitation. > > But no need for speculation, just google Actel or Quicklogic, they will > be happy to explain... > Peter Alfke > ============== > jacko wrote: > > scott moore wrote: > > > Does anyone have experience with antifuse fpgas? Are they lower cost > > > than static ram fpgas? > > > > > > Thank you, > > > > > > Scott Moore > > > > are they the eeprom ones, or a high current blow? > > > > just wondering if a reverse biased very small diode potential divider > > pair could charge a FET for passthrough switch on, by the division > > node. a discharge on the reverse bias diode using fet gate c as energy > > source, goes forward bias, and may melt open circuit fuse. achiving cut > > off. > > > > EEPROM cell best, but physical failure is potential after so many > > reprogramming cycles. > > > > a quantum tunnel PIN+ diode gate arrangement would work the best due to > > electron injection being the conduction charger of the P- gate rather > > than zenner breake down. this allows the substrate voltage to be > > increased. but then discharging of the floating gate becomes > > statistically unlikely. UV-EPROM magnetic induction discharge also > > possible. > > > > N+ doping on far gate end placed over insulator, and also p track in > > the substate beloe that, allows substrate discharge of whole chip. and > > p track can be volts held to reverse bias of discharge PIN+ diodes via > > p track. external to chip would be a two pin header with preserve > > jumper. > > > > cheers Peter, Reprogrammability, and testing, aren't an issue once the design is stable. Where I work, we use SRAM based devices to proof designs intended for OTP targets, and once it is functional, we migrate it to the final device. Generally speaking, we only do this for designs that must function in high-radiation environments, or the customer is nervous about the bitstreams not being "secure", but it isn't that difficult to port vendor neutral code. It's not perfect, and any problems with the migration result in expensive duds, but we treat it kind of like an ASIC flow, so the actual "dud rate" is very low. This is also the primary reason why our site doesn't use any coregen/megawizard/etc tools to generate IP. *All* of our IP must be in the form of VHDL, or vendor-neutral netlists, such as EDIF or VQM. It can be a pain, but all of our code can be shared without worrying about the target device.Article: 109952
Hi all, I hope I'm posting in the right place. I'm newbie in FPGA and want to have a development board. My choice is Spartan 3E Starter Kit (HW-SPAR3E-SK-US in xilinx's website). But, xilinx online store refuse to sell the board to my country (I live in Bali -Indonesia...). No exceptional reason except : "Currently we cannot deliver to your country" (sucks !!). I've also already contacted NU Horizon (http://www.nuhorizons.com/), xilinx distributor in SE Asia, but they didn't response to my email. Well, if they don't like to sell it to me, I'll find someone who does. Right now, I'm planning to go to Singapore / Malaysia to find electronic store who sells the Spartan 3E starter kit development board. If anyone in this group know which store(s) that sells it, could you pass the info to me ? Thanx in advance.. Regards, -daniel Bali - IndonesiaArticle: 109953
Well, we could get into a long discussion about relative security, and about radiation mitigation, but this is not the right place for that. I must, however, point out that "vendor-neutral" design pays a very high price in not being able to take advantage of all the "goodies" that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, clock manipulation and clock distribution, Serdes and 75-picosecond I/O granularity, to name just a few that come to mind. And just wait what we will announce in V-5LXT...) Portability forces you to design with 15 year-old basic structures. That's like living without indoor plumbing, electricity and telephone. :-( But your company seems to know why they like you to do it. Frugality envigorates body and soul... Peter Alfke, Xilinx ================= radarman wrote: > Peter Alfke wrote: > > We do not need any speculation. Antifuse FPGAs have been around for 20 > > years, Actel is the oldest supplier, Quicklogic the younger one. > > The antifuse is a very small (lless than one cubic micron?) speck of > > silicon that is normally an insulator, but becomes permanently > > conductive when a certain (rather high) voltage and current is applied. > > > > The system advantages are "instant-on" (no configuration process), > > inherent (but limited) security and a higher radiation tolerance. > > The disadvantages that have relegated antifuses to a niche market, are > > one-time-only (and very slow) programmability (now that designers have > > become accustomed to reprogrammability, and volatility is no longer a > > dirty word), the inability of complete testing, and a seemingly natural > > max size limitation. > > > > But no need for speculation, just google Actel or Quicklogic, they will > > be happy to explain... > > Peter Alfke > > ============== > > jacko wrote: > > > scott moore wrote: > > > > Does anyone have experience with antifuse fpgas? Are they lower cost > > > > than static ram fpgas? > > > > > > > > Thank you, > > > > > > > > Scott Moore > > > > > > are they the eeprom ones, or a high current blow? > > > > > > just wondering if a reverse biased very small diode potential divider > > > pair could charge a FET for passthrough switch on, by the division > > > node. a discharge on the reverse bias diode using fet gate c as energy > > > source, goes forward bias, and may melt open circuit fuse. achiving cut > > > off. > > > > > > EEPROM cell best, but physical failure is potential after so many > > > reprogramming cycles. > > > > > > a quantum tunnel PIN+ diode gate arrangement would work the best due to > > > electron injection being the conduction charger of the P- gate rather > > > than zenner breake down. this allows the substrate voltage to be > > > increased. but then discharging of the floating gate becomes > > > statistically unlikely. UV-EPROM magnetic induction discharge also > > > possible. > > > > > > N+ doping on far gate end placed over insulator, and also p track in > > > the substate beloe that, allows substrate discharge of whole chip. and > > > p track can be volts held to reverse bias of discharge PIN+ diodes via > > > p track. external to chip would be a two pin header with preserve > > > jumper. > > > > > > cheers > > Peter, > Reprogrammability, and testing, aren't an issue once the design is > stable. Where I work, we use SRAM based devices to proof designs > intended for OTP targets, and once it is functional, we migrate it to > the final device. Generally speaking, we only do this for designs that > must function in high-radiation environments, or the customer is > nervous about the bitstreams not being "secure", but it isn't that > difficult to port vendor neutral code. > > It's not perfect, and any problems with the migration result in > expensive duds, but we treat it kind of like an ASIC flow, so the > actual "dud rate" is very low. > > This is also the primary reason why our site doesn't use any > coregen/megawizard/etc tools to generate IP. *All* of our IP must be in > the form of VHDL, or vendor-neutral netlists, such as EDIF or VQM. It > can be a pain, but all of our code can be shared without worrying about > the target device.Article: 109954
Hi, You can try to buy from Avnet <http://www.avnet.com/>Article: 109955
Peter Alfke wrote: > Well, we could get into a long discussion about relative security, and > about radiation mitigation, but this is not the right place for that. > I must, however, point out that "vendor-neutral" design pays a very > high price in not being able to take advantage of all the "goodies" > that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, > clock manipulation and clock distribution, Serdes and 75-picosecond I/O > granularity, to name just a few that come to mind. And just wait what > we will announce in V-5LXT...) > Portability forces you to design with 15 year-old basic structures. > That's like living without indoor plumbing, electricity and telephone. > :-( > But your company seems to know why they like you to do it. Frugality > envigorates body and soul... > Peter Alfke, Xilinx > ================= Wau - does this mean that V-5LXT has some other super cool new goodies above PCI Express MAC !? Guess so. Peter - you usually use simple sentences, but this time I had to look up 2 words out of 5 word sentence, I found one at wikipedia, the other not. I am just saying that non-english speaking people will not be able to understand your last sentence to radarman (not even after a quick search at wikipedia!). AnttiArticle: 109956
Just add the 2nd MicroBlaze in the XPS tool. Göran Bilski <me_2003@walla.co.il> wrote in message news:1160296753.788965.57640@m73g2000cwd.googlegroups.com... > Hi all, > I have a microblaze processor that I've built using the EDK and > afterwards simulated and it seems to work fine. Now I need to make two > instances of this Microblaze system in my design. > Can I use the same module and instantiate it twice or I maybe I need to > make a copy of the system and name it differently. If I instance the > same module twice I figured out that it will be problematic to fill the > BRAM with code data. > Can anyone help ? > Thanks, Mordehay. >Article: 109957
Hi Urban, It also depends on what setting you put on MicroBlaze and how your system looks like. If you post your settings for Microblaze from the .mhs file, I can tell you if there is anything you should change. Göran Bilski <u_stadler@yahoo.de> wrote in message news:1160340640.441443.162960@i3g2000cwc.googlegroups.com... > hi > > i hvea a question about implementing a microblaze with ethernet. i'm > using a spartan 3e 500 an edk8.2. i created a new project with a > microblaze, an ethernet core, sdram, timer debug module an uart. in the > ethernet datasheet it says that in order to be able to use 100MBit the > obp bus hast to run at least with 65 MHz. my problem now is the the > design wont synthesize with more than 59 MHz even if i do multiple > iterations. > can anybody give me a hint what to do? > do i have to set some more constraints or anything else? > > thanks > urban >Article: 109958
Hi, Peter Alfke schrieb: > I must, however, point out that "vendor-neutral" design pays a very > high price in not being able to take advantage of all the "goodies" > that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, > clock manipulation and clock distribution, Serdes and 75-picosecond I/O > granularity, to name just a few that come to mind. And just wait what > we will announce in V-5LXT...) Portability is freedom for the designer. I'm very lucky, that portability is given for standard RTL-Code. No I like to have portability for specialised features. Why can't there be one way to instanciate RAM without dependancy on tool and target lib? My last XCV-code is fixed to XST and won't work (easily) with Synplify. Bad thing, if XiIlinx changes the synthesis tool again and I have to migrate old code. You will allways need to check, wheter a new technology provides features necessary for your code, but I would prefer to have no problem to transfer code for RAM of DPLLs from one vendor or tool to another. bye ThomasArticle: 109959
Thomas Entner wrote: > Hi Jake, > > do you have any estimates regarding license-costs? > > Thomas EUR 2500,- for programming 10.000 FPGA's Regards, JakeArticle: 109960
scott moore schrieb: > Does anyone have experience with antifuse fpgas? Are they lower cost > than static ram fpgas? Define lower cost *g*. Cost per device? Cost from the equipment view? You need generally more money per device for same complexity and have additional costs for the programming. But your equipment needs only one device, reducing costs from the equipment point of view. You need to think about a lot of parameters, before you could say if antifuse fpgas have lower or higher costs. I guess most designs are cheaper with ram-based fpgas. bye ThomasArticle: 109961
How can I do a "clean up project" with Quartus II 6.0? TIA, FrankArticle: 109962
hi well thanks for the answers. i tried a design with no cach and with data and instruction cache (2k). with multiple iterations i meant that i was using xplorer. here ist the system.mhs file (with cach) and the system.ucf file http://www.pfeilheim.sth.ac.at/xilinx/system.mhs http://www.pfeilheim.sth.ac.at/xilinx/system.ucf thanks urbanArticle: 109963
Antti wrote: > Peter Alfke wrote: > >>Well, we could get into a long discussion about relative security, and >>about radiation mitigation, but this is not the right place for that. >>I must, however, point out that "vendor-neutral" design pays a very >>high price in not being able to take advantage of all the "goodies" >>that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, >>clock manipulation and clock distribution, Serdes and 75-picosecond I/O >>granularity, to name just a few that come to mind. And just wait what >>we will announce in V-5LXT...) >>Portability forces you to design with 15 year-old basic structures. >>That's like living without indoor plumbing, electricity and telephone. >>:-( >>But your company seems to know why they like you to do it. Frugality >>envigorates body and soul... >>Peter Alfke, Xilinx >>================= > > Wau - does this mean that V-5LXT has some other super cool > new goodies above PCI Express MAC !? > > Guess so. > > Peter - you usually use simple sentences, but this time I had to look > up 2 words out of 5 word sentence, I found one at wikipedia, the other > not. I am just saying that non-english speaking people will not be able > to understand your last sentence to radarman (not even after a quick > search at wikipedia!). did you try "invigorates" ? ;) -jgArticle: 109964
Antti wrote: > Nico Coesel wrote: > >>"Antti" <Antti.Lukats@xilant.com> wrote: >> >> >>>hi > > [snip] > >>Got any links where there is more information? An S3 with internal >>flash + copy protection is something I could use in a design which >>needs some work on the PCB anyway... >> >>-- >>Reply to nico@nctdevpuntnl (punt=.) >>Bedrijven en winkels vindt U op www.adresboekje.nl > > > sorry - no links, nothing confirmative :( > > just thinking about why? and piece of unverified gossip. > > Well we have to wait. If there is no flash in Spartan-3A > then it really makes me wonder why make it at all? > > Is it really only because additional power saving modes? > sound unlikely, but you never know what consideration > are driving the Spartan-3A development. Didn't Actel do a low power mode respin, but then they made a larger name change for that! > hmm, it has ICAP added, so this maybe used to access > the internal flash, no extra interface needed. Xilinx will do what they can, with least effort. To copy lattice would need a new die design, "3A" is more likely to be a dual-die variant. [Like Atmel did with (IIRC) AT94S ? - their fading dual die FpSLIC ] -jgArticle: 109965
On 8 Oct 2006 23:20:38 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >Peter Alfke wrote: >> Well, we could get into a long discussion about relative security, and >> about radiation mitigation, but this is not the right place for that. >> I must, however, point out that "vendor-neutral" design pays a very >> high price in not being able to take advantage of all the "goodies" >> that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, >> clock manipulation and clock distribution, Serdes and 75-picosecond I/O >> granularity, to name just a few that come to mind. And just wait what >> we will announce in V-5LXT...) >> Portability forces you to design with 15 year-old basic structures. >> That's like living without indoor plumbing, electricity and telephone. >> :-( >> But your company seems to know why they like you to do it. Frugality >> envigorates body and soul... >> Peter Alfke, Xilinx >> ================= >Wau - does this mean that V-5LXT has some other super cool >new goodies above PCI Express MAC !? > >Guess so. > >Peter - you usually use simple sentences, but this time I had to look >up 2 words out of 5 word sentence, I found one at wikipedia, the other >not. I am just saying that non-english speaking people will not be able >to understand your last sentence to radarman (not even after a quick >search at wikipedia!). > >Antti I think dictionary.com is really helpful here: http://dictionary.reference.com/browse/envigorates. You see even people whose mother tongue is english make mistakes sometimes ;-)Article: 109966
Hi all. I'm using EDK ver. 8.1.02i ISE ver. 8.1.03i. I have to develop a project with Microblaze and so I'm programming firmware for this CPU. Reading about mb-gcc compiler features I have seen typical directive related to uBlaze setting. For example if Barrel Shifter has been enabled then mb-gcc issues the directive: -mxl-barrel-shift in compiling/linking to generate good code using HW barrel shifter. So enabling HW integer multiplier in microblaze I expected to get also the directive: "-mno-xl-soft-mul Use the hardware multiplier instead of emulation" But it NEVER appear in the automatically compiling steps !!! Moreover if I create and use a my makefile to compile my library sources and application I can force this directive: "-mno-xl-soft-mul" and get library and application code little smaller: all works fine in uBlaze because its setting include NO software integer multplier --> That is integer multiplier enabled. Why EDK Xilinx NEVER use "-mno-xl-soft-mul" directive when uBlaze has been set with HW integer multiplier ? Shoud it be a bug ? Thanks in advance for any answer. Best regards, Al.Article: 109967
Did you try to run Modelsim using WINE on Linux ? Henrik Pedersen wrote: > Hey there > > I have a lot of trouble finding directions/guides/manuals on how to get > subject working. > > Anyone able to point me in the right direction ? > > HenrikArticle: 109968
"Ben Jones" <ben.jones@xilinx.com> writes: > "Martin Thompson" <martin.j.thompson@trw.com> wrote in message > news:ulkntke5c.fsf@trw.com... > > "Ben Jones" <ben.jones@xilinx.com> writes: > > > >> I have never heard a credible excuse for using an async reset > >> for any internal logic. I'm racking my brains to come up with some > >> clock-domain-crossing circuit that needs one > > > Does the flancter count? XCELL37, which doesn't seem to be on the > > Xilinx site anymore... and Google isn't helping me find the original > > place I saw it :-( > > I have to confess, I've never heard of it. > Hmm, google seems to not provide any sources for it at all! The XCELL archives seem broken as well :-( I'll try and dig up an schematic and ASCII it later... > Then again, I don't do much flancting in most of my designs. :-) > Maybe you should :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 109969
I purchased Spartan3E starter kit (for edu.) It is shipped with ISE8.1 and EDK8.1 Is 8.2 (with last patches) better than 8.1 (with last patches) ? Is there a way to use EDK8.1 (only a CD in box) with ISE 8.2 (webpack freely available) ? Is it possible to download an other evaluation version of EDK (8.2 in place of 8.1) ? thank xilinx folks...Article: 109970
I seem to have a licensing problem with the Quartus Web edition. I receive the error message: Warning: FLEXlm software error: System clock has been set back Feature: quartus_lite License path: <filename> FLEXlm error: -88,309 For further information, refer to the FLEXlm End User Manual, available at "www.macrovision.com". I checked the manual, which lists this error message in the appendix E, but does not explain how to fix it. I requested a new license file from Altera, but no success. I also uninstalled Quartus II and re-installed it again - no success. I'm out of ideas. Any suggestions??? Thank you, MichaelArticle: 109971
"KJ" <kkjennings@sbcglobal.net> writes: > "Martin Thompson" <martin.j.thompson@trw.com> wrote in message > news:uhcyhk8u8.fsf@trw.com... > > Not to mention that using either lpm_ram_* or writing it yourself would make > it portable between Xilinx and Altera and probably most other FPGA vendors > and would not require any sort of generic to 'select' between the two > non-portable options. > Re: LPMS: You'd hope so wouldn't you, but I've never had any joy getting LPMs into Xilinx without rewriting them as coregen blocks. Xilinx: You *still* haven't got a way for me to instantiate arbitrarily sized (from generics) blocks of RAM like Altera let me! Grrr. Instantating specific lumps of RAM blocks and wiring them up right is not my idea of fun. I know, I can do it once in a big generic'd wrapper that figures it out for me, but why should I have to? I then have to modify by wrapper each time a new size of RAM block comes along. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 109972
dez.ambrose@gmail.com writes: > I'd like to turn the question around. Does Xilinx have something like > ALTSYNCRAM? That is one module that is completely parameterizable, > rather that a plethora of fixed dimension modules. Like the original > post, I want to do it without coregen so that I can write parameterized > code. Also, inferring doesn't seem to work because of mixed read and > write widths, meaning in some cases the the end result will be a mix of > RAM and luts. > Nope - I've ranted on this subject elsewhere (on a number of occasions)! Sorry! Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 109973
rickman wrote: > Thanks Peter. Of all the things a vendor can do to tick me off, spam > is pretty high on the list. I would really appreciate any help in > getting Xilinx to stop this. > > I once received similar junk email to an address I had given only to > Altera. When I contacted them they had no idea how it was given out, > or at least that is what they told me. So Xilinx is not alone. > > One thing to consider here is that automated spam bots try out random email addresses regularly, especially for big domains like hotmail and gmail. Thus you should not take it for granted that Xilinx, Altera, or anyone else has leaked or sold your email address. If you make a new address "rick123@gmail.com", you are going to get spam pretty quickly even if you never use the address. Add to that the fact that some of the big free email providers have leaked address lists (both accidentally, and intentionally), and you can see that there's a definite spam risk before you get to Xilinx marketing conspiracies. Of course, I could be wrong - you could be using completely unguessable addresses and Xilinx could be passing on your address. > Peter Alfke wrote: >> Rickman, you can be sure that I will chase this all the way up and down >> the Xilinx management chain! >> Peter Alfke, from home >> >> rickman wrote: >>> Over the years I have gotten a lot of junk email from Xilinx to email >>> addresses that I have given out only to support and never to any >>> marketing channel. I have always been disappointed that Xilinx has >>> done this. But now they have sunk to a new low, they are giving or >>> selling my email address to third party junk emailers. >>> >>> I guess I should not be surprised at this since it is getting to be the >>> norm rather than the exception. Everyone seems to think it is >>> perfectly ok to post a non-"privacy" statement saying in typical >>> crypto-speak that they share your information with anyone that suits >>> them. I have found that if I contact a vendor directly and say I want >>> to opt out of their "privacy" policy and they should not share my info >>> with anyone at all, they will honor this. But why is this necessary? >>> Why can't a privacy policy be a PRIVACY policy and not a NON-privacy >>> policy? >>> >>> Am I alone in being irritated by these practices? >Article: 109974
On 9 Oct KJ wrote: > > "Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message > news:1160349835.918930.124340@i42g2000cwa.googlegroups.com... > > Ok but what if those FPGA outputs can cause problems for other parts of > > the system, say if the FPGA is on a bus. Maybe there are some bus > > protocols out there where the bus clock can stop, and the peripheral > > needs to be able to be reset by the bus master?? > Like I said, I don't discount that there may be these cases...but have yet > to hear anyone actually name a specific case where the clock isn't running > but a specific reset condition is required. > > Can anyone actually provide one? Hard to believe that such a case doesn't > exist, but also hard to believe that one hasn't been articulated > either....oh well. The PCI spec requires all outputs to be tristated on reset even in the absense of a clock, so you need an async reset there. -- Christian Ludlam christian at recoil dot org
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