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Messages from 110025

Article: 110025
Subject: Re: a clueless bloke tells Xilinx to get a move on
From: mk <kal*@dspia.*comdelete>
Date: Mon, 09 Oct 2006 19:59:00 GMT
Links: << >>  << T >>  << A >>
On Mon, 09 Oct 2006 10:35:54 -0700, Austin Lesea <austin@xilinx.com>
wrote:

>mk,
>
>How well does it deal with memory?
>
>Can you place 16 or 32 Gbytes in the box?

Nope, when you install vista x64,  4 of the 8 2G dimms pop out of the
computer...
Seriously though, in my experience it's no different than linux. If
you have a two cpu socket machine with 8 dimms, you can make a quad
core machine with 16G and all of it is available to the 64 bit
processes.

Article: 110026
Subject: Re: a clueless bloke tells Xilinx to get a move on
From: mk <kal*@dspia.*comdelete>
Date: Mon, 09 Oct 2006 20:00:47 GMT
Links: << >>  << T >>  << A >>
On Mon, 09 Oct 2006 19:54:44 +0200, Falk Brunner <Falk.Brunner@gmx.de>
wrote:

>Austin Lesea schrieb:
>> mk,
>> 
>> How well does it deal with memory?
>> 
>> Can you place 16 or 32 Gbytes in the box?
>
>Much more important question.
>
>How mature is it? The Xilinx software itself makes trouble enough. 
>Adding a very beta stage operating system will bring a lot of "fun" to 
>the software guys.

As I have mentioned vista is the second version of 64 bit windows.
It's stable enough to run ISE 8.2 to run to completion where it
wouldn't on win32 because there it gets only 2G address space whereas
on win64, 32 bit binaries get the full 4G address space.

Article: 110027
Subject: Re: Quartus II 6.0
From: Henry Wong <henry@stuffedcow.wox.org>
Date: Mon, 09 Oct 2006 13:23:29 -0700
Links: << >>  << T >>  << A >>
Frank van Eijkelenburg wrote:
> How can I do a "clean up project" with Quartus II 6.0?
> 

I don't believe there is an automated way to "clean up" the project...

- Project -> Archive project, then unarchive the generated .qar into a 
new directory. There's quite a few unnecessary files saved in the .qar 
though, but the 'database' is gone, at least.

- Manually clean the project (Make a backup first, just in case!)
As far as I know, the only necessary files are:
   - *.qpf, *.qsf
   - your source files (and the source files the MegaWizard generates)

- Maybe write a script/batch file that deletes files?
   db subdirectory, *.rpt, *.sof, *.pof, *.eqn, *.summary, *.pin, *.xml, 
*.done, ...

Article: 110028
Subject: Re: Antifuse, lower cost?
From: "Peter Alfke" <peter@xilinx.com>
Date: 9 Oct 2006 13:24:08 -0700
Links: << >>  << T >>  << A >>
Kolja is right.
I was just careful to not make this an anti-Actel response.
The days where we had to shout and prove that Xilinx usually offers a
better solution, those days are long over..
Peter
=============.
Kolja Sulimma wrote:
> radarman wrote:
>
> > Peter,
> > Reprogrammability, and testing, aren't an issue once the design is
> > stable.
>
> I believe that Peter was talking about chip test during manufacturing.
> You can not test an antifuse before shipping it to the customer.
> Therefore it is impossible to build large antifuse FPGAs.
> (Yield has an exponentian dependency size)
> 
> 
> Kolja Sulimma


Article: 110029
Subject: Re: FPGA to SRAM port interface
From: "oen_br" <oen_no_spam@yahoo.com.br>
Date: 9 Oct 2006 13:33:52 -0700
Links: << >>  << T >>  << A >>
Hi Falk,

> Clock signal for what? The BRAM inside the FPGA? NO WAY!

Yes, for the BRAM too. Why not?
The ALE, READ# and WRITE# signals will never overlap!

> Use a clean clock (from a XO or so) to clock the FPGA logic. Not clock
> gating etc.! Build text book style FSMs to contol the BRAM and generate
> appropiate signals for your external SRAM. Than it will work fine.
>
> Hint. Register at least WRITE# to the SRAM, so it will not glitch.

I don't know what 'XO' means, but I think you mean a crystal (it
reminded me Galactica Colonel Tigh :-) ).
Anyway the tranfer rate is 60MHz (mega transfers per second), so, to
sample ALE, etc, I will need a very high frequency clock signal (200MHz
maybe?). Even if it is possible, it will spend a lot of power!
Did I misunderstand you?

There is no external SRAM, just the internal BRAM used as a mail box!
Two processors, each one using one BRAM port.

Thank's,

Luiz Carlos.


Article: 110030
Subject: Re: An implementation of a clean reset signal
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Tue, 10 Oct 2006 09:40:37 +1300
Links: << >>  << T >>  << A >>
Bob Perlman wrote:
> On 9 Oct 2006 11:57:12 -0700, "KJ" <Kevin.Jennings@Unisys.com> wrote:
> 
>>In any case, nobody has articulated yet the application that really
>>does require specified reset behaviour PRIOR to the clock starting thus
>>requiring use of the async reset (with the exception of the reset
>>signal synchronizer flip flop itself).
> 
> Uh, I did.  Took me 20 minutes to type it up, too.  I'm not exactly
> sure what the disagreement is: if you have FFs controlling TriState
> enables, you should initialize them asynchronously.  Whether that's
> done by an end-of-config reset or some other reset signal doesn't
> really matter--you need the asynchronous reset.
> 
> And I didn't even get to the open-the-bomb-bay-doors and
> throw-the-countermeasures-out-the-back-of-the-plane and
> start-radiating-the-patient signals.  Proper design etiquette demands
> that they be initialized immediately, too.  (Yes, those signals go
> through other interlocks, but as soon as you rely on redundancy, it
> ceases to exist.)

Correct, and you also need Async control, in such paths as Watchdog.
If the wdog fires due to clock failure, and your reset is only Sync,
guess what happens next ?
Maybe the FPGA core does not care, but the system design certainly does,
and if the FPGA cannot handle this, then downstream, logic must be added.

-jg


Article: 110031
Subject: FPGA and ZBT/NoBL SRAM timing issue
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 9 Oct 2006 13:57:15 -0700
Links: << >>  << T >>  << A >>
Greetings comp.arch.fpga group,

I am having some trouble implementing
a ZBT or NoBL SRAM interface. I am
using a Xilinx ML402 board but my
trouble is generic in nature.

I am trying to divide the interface into
four ports, each port having a particular
time slice to read or write to the SRAM.
In my case I am trying to do one write
slice and three read slices, however, my
issue happens with any write followed by
a read.

The design is synchronous lets say at 50MHz
to make the numbers easier. So a 20nS period.

Let's say at t=0nS the FPGA issues a write
enable along with the write address.

I have a separate DCM clocking the SRAM and
say for setup purpose I delay this clock by
4 ns. So at t=4nS, the SRAM has a write command
and the write address.

At t=20nS, the FPGA does a read at a specified
read address. This gets clocked into the SRAM
at t=24ns.

At t=40ns the FPGA issues the write data,
according to the staggered data delivery
architecture of the ZBT or NoBL SRAMs.

At t=44 the SRAM gets another clock. Let's
say it's another write enable and address,
although it doesn't matter.

After Tco(time clock to output) about 3ns,
or at about t=47ns, the SRAM is outputing data
for the read clock at 24ns.

There's the issue. The FPGA is outputing data
from t=40ns to t=60ns and the SRAM is outputting
data from 47 ns to perhaps 67ns creating a
collision on the bidirectional lines.

I have thought of minimizing this affect by
using a clock pin that is negatively delayed
by the FPGA clock, something of the order
of Tco, but it doesn't seem right that I should
have to split hairs like this. Isn't the point
of the ZBT architecture is so you can have write
and read effortlessly meshed?

Any insight will be appreciated.

Best Regards,

Brad Smallridge
aivision dot com



Article: 110032
Subject: Re: FPGA to SRAM port interface
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Mon, 09 Oct 2006 14:03:25 -0700
Links: << >>  << T >>  << A >>
oen_br wrote:
> I'm interfacing an FPGA to a multiplexed SRAM port (ALE, READ, WRITE,
> DATA/ADDR bus).
> I want to read from/write to the FPGA internal block RAM (SPARTAN 3E),
> using burst accesses.
> 
> This is a write access example.
>            ____
> ALE    ___/    \__________________________________________________
>        _______________        __        __        __        ______
> WRITE#                \______/  \______/  \______/  \______/
>             ________  ________  ________  ________  ________
> DTADD  ____/  ADDR  \/ DATA0  \/ DATA1  \/ DATA2  \/ DATA3  \______
>            \________/\________/\________/\________/\________/
> 
> For the address load and increment I combined ALE, READ and WRITE
> signals to generate one clock signal.
> CLOCK <= WRITE# and READ# and (not ALE);
> 
> The problem is, to determine if I must load a new address I must know
> if it is the ALE cycle:
> 
> if rising_edge (CLOCK) then
>    if (ALE = '1') then  -- problem
>       ADDRESS_REG <= DTADD;
>    else
>       ADDRESS_REG <= ADDRESS_REG+1;
>    end if;
> end if;

In order for the CLOCK signal to go high, ALE must
be low, in your logic, since (not ALE) is AND'd with
WRITE# and READ#. So that implies inside your
'if' the ALE='1' can never be true.

Perhaps changing your logic to falling_edge(CLOCK)
might fix it within your approach. Or invert the CLOCK
signal from what it is now.

-Dave


-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 110033
Subject: Re: Quartus II 6.0: System clock has been set back
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Mon, 09 Oct 2006 23:07:41 +0200
Links: << >>  << T >>  << A >>
radarman wrote:

> I believe the reason is that you can convert the "free" edition into
> the "full" edition by buying a license with no need to do a full
> reinstall. However, I understand there are some problems with that
> approach.

Yep - for one thing, the device map files for all but the smalles Stratix I
and II will be missing, as well as the netlist viewers, floorplanner and
other stuff.

A full Quartus install now runs around 1GB, while the Web Edition is around
250MB. Something has to go then ;-)

Best regards,


Ben


Article: 110034
Subject: Re: Quartus II 6.0
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Mon, 09 Oct 2006 23:29:16 +0200
Links: << >>  << T >>  << A >>
Frank van Eijkelenburg wrote:

> Ben Twijnstra wrote:
>> Frank van Eijkelenburg wrote:
>> 
>>> How can I do a "clean up project" with Quartus II 6.0?
>> 
>> What do you mean with "clean up Project"? Remove unreferenced source
>> files from the project? Remove unwanted settings? Or so?
>> 
>> Best regards,
>> 
>> 
>> Ben
>> 
> 
> Generated netlists etc. All file which are generated from synthesis till
> assembler phase. In ISE it is an option in one of the menus, in Quartus I
> can't find it.
> 
> Frank

As Henry Wong stated, doing Archive Project and recreating the project from
the archive somewhere else would be a good start, but there's quite a lot
of reports that get included in the archive by default that you wouldn't
want.

Today I got my hands on a pre-release beta version of Quartus II 6.1, and it
has the option of specifying a directory where you want all Quartus's
_output_ to go. If you make that different from the project's working
directory, life will be a whole lot easier - just delete the db and that
specified output directory and you should be all set - but it'll be a few
weeks before Quartus II 6.1 will be publically available.

Best regards,



Ben


Article: 110035
Subject: Re: An implementation of a clean reset signal
From: Ray Andraka <ray@andraka.com>
Date: Mon, 09 Oct 2006 18:04:36 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> That's why (as I posted earlier) all Xilinx FPGA asynchronously
> initiate all flip-flops as part of the initiating and configuration
> process, and also keep the outputs 3-stated until configuration is
> finished.
> Nothing new for you, Bob, but somebody else may have forgotten.
> Peter Alfke
> ====================
> Bob Perlman wrote:
> 
>>On Mon, 09 Oct 2006 00:04:37 GMT, "KJ" <kkjennings@sbcglobal.net>
>>wrote:
>>
>>
>>>"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message
>>>news:1160349835.918930.124340@i42g2000cwa.googlegroups.com...
>>>
>>>>>If you take a step back and realize that you probably shouldn't expect
>>>>>anything useful out of a part that is not receiving the proper inputs yet
>>>>>(perhaps by design, after all it could be a power saving measure) then
>>>>>the
>>>>>outputs that do not actually reset themselves until the clock does start
>>>>>up
>>>>>is not really an issue.
>>>>
>>>>Ok but what if those FPGA outputs can cause problems for other parts of
>>>>the system, say if the FPGA is on a bus. Maybe there are some bus
>>>>protocols out there where the bus clock can stop, and the peripheral
>>>>needs to be able to be reset by the bus master??
>>>
>>>Like I said, I don't discount that there may be these cases...but have yet
>>>to hear anyone actually name a specific case where the clock isn't running
>>>but a specific reset condition is required.
>>>
>>>Can anyone actually provide one?  Hard to believe that such a case doesn't
>>>exist, but also hard to believe that one hasn't been articulated
>>>either....oh well.
>>
>>How about TriState contention?  If I'm controlling TriState buffers
>>with FFs that aren't initialized until the clock comes along, I run
>>the risk of turning on more than one set of TriStates on a signal or
>>bus.  And when you're using high-current drivers, this can cause
>>smoke; I've seen it.
>>
>>Bob Perlman
>>Cambrian Design Works
>>http://www.cambriandesign.com
> 
> 

Yup, that's what I do for those cases that need an async reset.  The PGM 
pin on the FPGA works fine as a reset, as it instantly drives all but a 
few pins to hi-Z.  FPGAs are not really designed for Async reset; the 
tools do not support it very well (timing analysis issues).  If it were 
up to me, I'd remove the async resets from the internal logic and reap 
the increased performance that would result.

Article: 110036
Subject: Re: An implementation of a clean reset signal
From: Ray Andraka <ray@andraka.com>
Date: Mon, 09 Oct 2006 18:06:38 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Output tristate in Xilinx FPGAs is driven by a flip-flop.
> Peter Alfke

Doesn't have to be.  There are flip-flops in the IOBs for the tristate 
control, but they can be bypassed.

Article: 110037
Subject: Re: FPGA and ZBT/NoBL SRAM timing issue
From: "John_H" <newsgroup@johnhandwork.com>
Date: Mon, 09 Oct 2006 22:14:10 GMT
Links: << >>  << T >>  << A >>
You might find some good app notes with the memory manufacturer.  I recall 
looking at the ZBT/NoBL format and came across the same trouble.  Say, isn't 
there a Xilinx App note, too?  The first hit in the Xilinx search for ZBT 
referenced the 3rd hit: XAPP136.

It appears the devices are designed for limited bus contention but I don't 
recall values anywhere near 7 ns.  The contention of the app note (I had to 
say it) is the total power dissipated during contention is a quickly 
calculated value that the designer includes in the overall power numbers. 
This makes sense if series impedances are part of the connection to the SRAM 
such as the SSTL or HSTL standards might recommend.

As long as the contention doesn't present power problems and is resolved 
within the setup time, the process should flow.  If you can shift your clock 
to guarantee *just* meeting the setup time at the SRAM for writes, all the 
better.  This gets a little complicated since you want to *just* achieve the 
hold time on the other side of the clock, too.

Happy reading!
- John_H


"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message 
news:12ildtntondf782@corp.supernews.com...
> Greetings comp.arch.fpga group,
>
> I am having some trouble implementing
> a ZBT or NoBL SRAM interface. I am
> using a Xilinx ML402 board but my
> trouble is generic in nature.
>
> I am trying to divide the interface into
> four ports, each port having a particular
> time slice to read or write to the SRAM.
> In my case I am trying to do one write
> slice and three read slices, however, my
> issue happens with any write followed by
> a read.
>
> The design is synchronous lets say at 50MHz
> to make the numbers easier. So a 20nS period.
>
> Let's say at t=0nS the FPGA issues a write
> enable along with the write address.
>
> I have a separate DCM clocking the SRAM and
> say for setup purpose I delay this clock by
> 4 ns. So at t=4nS, the SRAM has a write command
> and the write address.
>
> At t=20nS, the FPGA does a read at a specified
> read address. This gets clocked into the SRAM
> at t=24ns.
>
> At t=40ns the FPGA issues the write data,
> according to the staggered data delivery
> architecture of the ZBT or NoBL SRAMs.
>
> At t=44 the SRAM gets another clock. Let's
> say it's another write enable and address,
> although it doesn't matter.
>
> After Tco(time clock to output) about 3ns,
> or at about t=47ns, the SRAM is outputing data
> for the read clock at 24ns.
>
> There's the issue. The FPGA is outputing data
> from t=40ns to t=60ns and the SRAM is outputting
> data from 47 ns to perhaps 67ns creating a
> collision on the bidirectional lines.
>
> I have thought of minimizing this affect by
> using a clock pin that is negatively delayed
> by the FPGA clock, something of the order
> of Tco, but it doesn't seem right that I should
> have to split hairs like this. Isn't the point
> of the ZBT architecture is so you can have write
> and read effortlessly meshed?
>
> Any insight will be appreciated.
>
> Best Regards,
>
> Brad Smallridge
> aivision dot com
>
> 



Article: 110038
Subject: Re: Quartus II 6.0
From: Mark McDougall <markm@vl.com.au>
Date: Tue, 10 Oct 2006 10:11:52 +1000
Links: << >>  << T >>  << A >>
Henry Wong wrote:

> As far as I know, the only necessary files are:
>   - *.qpf, *.qsf
>   - your source files (and the source files the MegaWizard generates)

And any TCL scripts you may have created...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 110039
Subject: CPLD's and labels
From: "GPE" <See_my_website_for_email@cox.net>
Date: Tue, 10 Oct 2006 00:05:25 -0500
Links: << >>  << T >>  << A >>
OK -- our old label maker is on the fritz and parts are no longer 
available....

Does anybody make a label sized for PALS such as 16V8's in a DIP package 
that can be used in a laser printer?
The size we were using with our old printer was 0.2" x 0.8".  0.25" wide is 
too big for a 0.3" DIP and I'd prefer not to cut each and every one of them.

Thanks,
Ed


Article: 110040
Subject: Re: CPLD's and labels
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 9 Oct 2006 22:22:44 -0700
Links: << >>  << T >>  << A >>
Maybe this is the golden opportunity to collapse multiple PALs into one
CPLD.
Program them on the board, no need for labels...
Peter Alfke, Xilinx

GPE wrote:
> OK -- our old label maker is on the fritz and parts are no longer
> available....
>
> Does anybody make a label sized for PALS such as 16V8's in a DIP package
> that can be used in a laser printer?
> The size we were using with our old printer was 0.2" x 0.8".  0.25" wide is
> too big for a 0.3" DIP and I'd prefer not to cut each and every one of them.
> 
> Thanks,
> Ed


Article: 110041
Subject: Re: BSD indi processor IP compiles at ($13.30)
From: "jacko" <jackokring@gmail.com>
Date: 9 Oct 2006 23:09:39 -0700
Links: << >>  << T >>  << A >>
Hi

Now at version indi16.3.0 fixed logical error and made improvements in
cycle timing. slightly larger, but the older versions will not work due
to the logical error pin held at ground. approx 370 logical elements.
removed interupt facility cos this can be done with 2 indi cores and
correct wait /busfree chaining.

have to work out how to promote clock, 40 pin external bus changes to
test16 top level. compiling for larger chip 1270 series to be able to
get IO devices on.

should work at 60MHz which is 12MIPS. the forth i'm developing will
support device polling, and i have just written the arithmetic words.

cheers

http://indi.joox.net or http://indi.hpsdr.com or
http://indi.microfpga.com


Article: 110042
Subject: Finite State Machine
From: "jajo" <jmunir@gmail.com>
Date: 9 Oct 2006 23:53:49 -0700
Links: << >>  << T >>  << A >>
Hi,

Do you think that it is a good idea to control several blocks of the
design (for example with a 802.11 transceiver) with a finite state
machine? or maybe with a microcontroller? . The idea consists on
implementing everything into a FPGA.

Thanks


Article: 110043
Subject: longest webcase record
From: "colin" <colin_toogood@yahoo.com>
Date: 10 Oct 2006 00:43:31 -0700
Links: << >>  << T >>  << A >>
All

I am wondering what the record is for having the longest Xilinx webcase
open .

All I asked was whether I can do boundary scan in a Coolrunner II using
sstl logic levels, over three weeks ago.

Ten days ago they answered half my question but either bsdlanno has a
serious bug or their answer was wrong.

I am left with polling xilinx every couple of days.

Colin


Article: 110044
Subject: Re: ISE/EDK computer selection
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 10 Oct 2006 09:30:37 +0100
Links: << >>  << T >>  << A >>
"Guru" <ales.gorkic@email.si> writes:

> Hi all,
> 
> I am buying a new for my work. I do a lot of synhesis, map and P&R
> using ISE 8.2 (Windows) in Xilinx EDK with quite complex systems.
> Building a HW for such a system can take a very long time, so selection
> of an appropriate computer is a must.
> 
> Does anyone has any experience or benchmark test for a computer
> selection:

My experience says "get the biggest cache you can", which seems to be
Intel these days...

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

   

Article: 110045
Subject: SDRAM initialisation and MCF5272
From: "KBG" <karthik.balaguru@lntinfotech.com>
Date: 10 Oct 2006 01:57:07 -0700
Links: << >>  << T >>  << A >>
Hi,

According to the MCF5272 datasheet, and the  schematic, the address
line A22 and A23 of ColdFire are to be treated as SDBA0 and SDBA1 and
connected to BA0 and BA1 of the SDRAM respectively. But when the
register value is set according to the above, the SDRAM initialisation
faces problem.

But when i set a value in such a way that the address lines A23 and A24

of ColdFire are connected to BA0 and BA1 of SDRAM then it works fine.
Really strange !

How is this possible ? what & where could be the problem ?

Thx in advanse, 
Karthik Balaguru


Article: 110046
Subject: Re: longest webcase record
From: Symon <symon_brewer@hotmail.com>
Date: 10 Oct 2006 12:28:02 +0200
Links: << >>  << T >>  << A >>
colin wrote:
> All
> 
> I am wondering what the record is for having the longest Xilinx webcase
> open .
> 
> All I asked was whether I can do boundary scan in a Coolrunner II using
> sstl logic levels, over three weeks ago.
> 
> Ten days ago they answered half my question but either bsdlanno has a
> serious bug or their answer was wrong.
> 
> I am left with polling xilinx every couple of days.
> 
> Colin
> 
I suggest you open a webcase to find the answer to your question.
HTH, Syms.

Article: 110047
Subject: Re: Quartus II 6.0
From: "KJ" <kkjennings@sbcglobal.net>
Date: Tue, 10 Oct 2006 10:44:53 GMT
Links: << >>  << T >>  << A >>

"Frank van Eijkelenburg" <frank.van.eijkelenburg@technolution.nl> wrote in 
message news:452a03fd$0$17352$bf4948fe@news.tele2.nl...
> How can I do a "clean up project" with Quartus II 6.0?
>
> TIA,
> Frank

Use some form of source control (SubVersion, CVS, SourceSafe, etc.).  Then 
simply delete the entire directory and then do a 'get' to get your source 
files back out of the vault.

KJ 



Article: 110048
Subject: Re: longest webcase record
From: "KJ" <kkjennings@sbcglobal.net>
Date: Tue, 10 Oct 2006 10:53:18 GMT
Links: << >>  << T >>  << A >>
"colin" <colin_toogood@yahoo.com> wrote in message 
news:1160466211.076872.226570@i42g2000cwa.googlegroups.com...
> All
>
> I am wondering what the record is for having the longest Xilinx webcase
> open .
>
> All I asked was whether I can do boundary scan in a Coolrunner II using
> sstl logic levels, over three weeks ago.
>
> Ten days ago they answered half my question but either bsdlanno has a
> serious bug or their answer was wrong.
>

I've got a couple with Altera that have been open for well over a year 
now....the clock is still running.

KJ 



Article: 110049
Subject: Re: CPLD's and labels
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Tue, 10 Oct 2006 11:55:20 +0100
Links: << >>  << T >>  << A >>
On Tue, 10 Oct 2006 00:05:25 -0500, "GPE"
<See_my_website_for_email@cox.net> wrote:

>OK -- our old label maker is on the fritz and parts are no longer 
>available....
>
>Does anybody make a label sized for PALS such as 16V8's in a DIP package 
>that can be used in a laser printer?
>The size we were using with our old printer was 0.2" x 0.8".  0.25" wide is 
>too big for a 0.3" DIP and I'd prefer not to cut each and every one of them.
>
>Thanks,
>Ed

http://uk.farnell.com/jsp/endecaSearch/partDetail.jsp?SKU=463802

Should also be available from Newark in the US.

- Brian




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