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lancepickens@gmail.com wrote: > Hi, > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks by designing a > special > purpose chips ala FPGA to run your code? Does anyone have any > experience > with this? Yes. TommyArticle: 111426
Will Dean wrote: > "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > news:454a42f8$1@clear.net.nz... > > > > yes, but I'm really interested to see how you design with discrete > > logic, and still get 40% reserve capacity - I know, use a > > HEF4894, when a HEF4794 would do ! :) > > And I was interested in the 'eight or so' chips which fit into the space of > the TQFP-100... > > Will Three dual 4 input muxes (analog switch based), a 4 bit counter, a dual tri-state buffer, a dual NAND gate and a dual FF. Together with two 8 bit SPI port relay drivers, they all fit in a 10 x 20 mm area. The smallest CPLD I can easily use is a 128 macrocell part in a 100 pin TQFP at 16 mm sq package and still requires the two relay drivers plus a JTAG header. There is one package we can use that is smaller at 12 mm sq, but only one part is available in this package and it is still a very tight fit in the available space that is only 14 mm wide. This will be under a metal shield and 1 mm on each side may not be enough clearance with the manufacturing tolerances.Article: 111427
lancepickens@gmail.com wrote: > Hi, > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks by designing a > special > purpose chips ala FPGA to run your code? Does anyone have any > experience > with this? Bioinformatics, specifically Timelogic used FPGAs in the DeCypher engine many years ago, Timelogic recently changed hands. Also recently we saw product introductions from two vendors for Opteron coprocessors for the 2nd socket using Altera and Xilinx FPGAs, no doubt these will be used to hardwire some interesting algorithms. Also Cray computer bought out a small Opteron server company (Octiga Bay) with FPGAs on board rather than in the socket. We had Mersenne primes on FPGA v highend PCs, FPGAs don't always win on cost, usually a matter of managing bandwidth, FPGAs sometimes better, sometimes not. For the hardware shy, there are quite a few C based products to map software to hardware, even Fortran has been used (I'm told). Google fpga with any scientific term and see what pops up. John JaksonArticle: 111428
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:1162518836.420552.259710@h48g2000cwc.googlegroups.com... > lancepickens@gmail.com wrote: >> Hi, >> Coming from a scientific computing standpoint (with no hardware >> experience). >> I was wondering if you can improve any dedicated tasks by designing a >> special >> purpose chips ala FPGA to run your code? Does anyone have any >> experience >> with this? > > Yes. > > Tommy > :-) Google this. fpga scientific computing Guess what? Nearly half a million hits! So, I added 'lumberjack' to the search and got it down to 44 hits. HTH, Syms.Article: 111429
Will Dean wrote: > "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > news:454a42f8$1@clear.net.nz... > >>yes, but I'm really interested to see how you design with discrete >>logic, and still get 40% reserve capacity - I know, use a >>HEF4894, when a HEF4794 would do ! :) > > > And I was interested in the 'eight or so' chips which fit into the space of > the TQFP-100... > > Will > > I was wondering the same thing. Wafer scale?Article: 111430
There are many ways to do this--here's one idea: You can use the conf_done pin to trigger a reset chip (maxim/dallas has plenty of choices) and tie it to the appropriate pin on the FPGA, probably the DEV_CLRn (device wide asynchronous reset). <martstev@gmail.com> wrote in message news:1162498322.376240.187270@e3g2000cwe.googlegroups.com... >I am using Altera Stratix II FPGA and also power supervisor circuit > which generates reset which it tied to nCONFIG for configuration of > the FPGA. Now, I'd like to generate RESET for the FPGA after the > configuration and Initialization is complete everytime. I can't find a > part that can do that..any suggetions? >Article: 111431
bronzefury wrote: > Personally, I would avoid code generators to generate RTL for design. There are different levels of generated code. e.g. 1> Schematic to code generation e.g. FSM, block diagram,module integration. 2> Translating code from one format to another. 3> Template based code generators etc. While some are simple (have <10x improvement in total coding time) others are complex and can result in saving days or even weeks of coding time. While I personally wont care for the first case the second case is what interests me. > Coding RTL is not a bottleneck for me, even on multi-million gate designs. > Some IP is provided by 3rd-party, other IP our developers code. It is > fairly easy to write Verilog once you have tried and true coding style. Why > would I want to learn a proprietary language to generate a standard > language? (and get locked-in?). Applying the 80-20 rule, I would say that 80% of any code is bug free but identifying the other 20% can take up 80% of my development time. so would it not be in my interest to reduce the amount of hand written code by generating code wherever possible? Also quite a few bugs are because of copy, paste, modify errors whihc a template based code generator can easily fix. > In addition, I know exactly what hardware > I'll generate when I code. For logic circuits that are used often, the HDL > addresses that by allowing designers to create modules or primitives. Who > knows what a code generator will output. I also wouldn't want to be locked > in to a proprietary. If we are generating RTL the generated code will be verilog or VHDL and if it is a testcase it will be e,c,SystemVerilog or SystemC and if at any time we want to "break out" of the code generator "lock-in" we can always take the generated code and continue from there. Note: I dont have a code generator to sell. But have seen various reusable code generators written by my team mates which have saved weeks and weeks of coding+debugging effort and was wondering what will it cost in the market. Regards Thomas. > > System Verilog addresses many of the my department's needs. > > Even if a big name EDA company were to come out with one, I doubt this type > of tool would be purchased. > > I think if you want to attack something in the area of chip design, you've > got to address the parts in the design flow that addresses a company's > development bottlenecks such as verification or physical design. > > > "Thomas" <dtsi.india@gmail.com> wrote in message > news:1162397407.320469.86740@h48g2000cwc.googlegroups.com... > > Generalising the question of this discussion I would like to know what > > does the group here think that code generators are worth? > > > > Say Someone comes out with a code generator which requires some input > > data say, D_in and generates a bunch of output code say, C_out. > > > > Given that C_out is something that you already write for your design > > wether the code generator exists or not, when will the code generator > > look like a fesible option? > > > > Given the following man days(Including coding, verfying and debugging > > time) for writing D_in and generating C_out VS manual writing of > > C_out, what is the price you will be willing to pay for the code > > generator in each case? > > --------------------------------------------- > > Development time in Mandays > > --------------------------------------------- > > D_in : Manual C_out > > --------------------------------------------- > > 1 : 10 > > 1 : 100 > > 1 : 1000 > > > > If such a code generator appears on the market will your management > > wait until a bigname EDA comes out with a me too product or will they > > buy it from a noname developer? > > Regards > > Thomas > > > > Andy wrote: > >> Evan Lavelle wrote: > >> > Ok, is it worth any more than $0 now? :) > >> > >> In a word, no. > >> > >> Why go to the trouble of learning a new language to try to do things > >> like macros, loops, random stimulus, etc. when you have the power of > >> the VHDL language at your disposal in a VHDL testbench? Now, if you > >> have vectors from an external model/simulation, those can be applied > >> with text-io relatively easily from within a vhdl testbench that will > >> run on any vhdl simulator. > >> > >> My "unit level tests" are usually at a high enough level that I need a > >> lot more capability than is available in any vector based scripting > >> language. > >> > >> Andy > >Article: 111432
rickman wrote: >>>I could split it into two chips which would fit better, but I still am >>>not sure I would have the required 40% reserve capacitiy and would have >>>to add a JTAG connector to allow updates and factory programming. >>> >>>So discrete logic is not quite yet dead... >> >>yes, but I'm really interested to see how you design with discrete >>logic, and still get 40% reserve capacity - I know, use a >>HEF4894, when a HEF4794 would do ! :) > > > My point has been that it will not provide any less *useful* > reconfigurability. I had the "big" presentation today and the two > senior people who will have to "OK" the decision didn't even come. The > guy who is our contact with the FPGA/CPLD department started kibizing > at the end of the presentation saying that the discrete logic approach > was not "clean". I had to call him on that BS. When faced with these 'edicts' you need to get creative :) In a PLD vs full hardware implementation, then pin resource does not need 40% headroom, as clearly the connectors etc do not have that. So, you can look at the product-terms and that should come better than 40% spare. The fuse-blow count on loading into a programmer is also another yardstick, and that will also usually be < 60% (often slightly lower than PT usage) If that fails, you can spec Cross-point usage, and in any CPLD design, that will be << 60%, so give them that number, or quote the mean of Fuse-Blow and Cross-Point usage ? -jgArticle: 111433
Hi, This is a question about digilent spartan-3 starter board , which has a simple 10ns sram and 20ns clock. I am using a simple controller to access the sram. During a read operation, the address is stored into a register and oe is activated at the first rising edge of the clock and data is retrieved at the next edge. The 20 ns period seems not large enough to accommodate the pad delay and external loading. A simple testing circuit shows that about 0.2% read errors. There is no error if the reading period is extended to 2 clocks. Is it possible to put some timing or other constraints in the ucf file to help timing? Thanks.Article: 111434
i have a doubt regarding the coding style in vhdl
if ( reset = '1' ) then
data_temp <= 0;
elsif (clock'event and clock = '1') then
data <= data_temp;
data_out <= data_temp and not data;
end if;
end if;
1. when i am giving clock data temp data is loaded into data at
present clock cycle or at next clock cycle.
2. when i am taking data_out output as given above it is
getting data_out at next clock cycle not at the present clock cycle
where data_temp is high and data is low. why this is happening
i need to get the data_out (high for one clock cycle at the
instant data_temp is high not at the next clock cycle .)
is this problem will be solved during synthesis since i am
facing the problem during simulation but does it behave the same way
during synthesis also. since it is a signal assignment signal " <= " a
minimum of delta delay will be there but will it take the entire clock
cycle delay.........
regards
kil
Article: 111435ekavirsrikanth@gmail.com wrote: > is this problem will be solved during synthesis since i am > facing the problem during simulation but does it behave the same way > during synthesis also. since it is a signal assignment signal " <= " a > minimum of delta delay will be there but will it take the entire clock > cycle delay......... To get a better feel for what's actually happening, during simulation add delays to the assignments to simulate propagation delays through the flip-flops... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111436
Good mornign, All Post-PAR simulation need to set SIMULATION_P generic to 1. But this is not single problem in this project.... I still looking for any mension about using aurora core on V4FX.... ThanksArticle: 111437
Hello experts, I got succesfull in using this core. Thanks for your help. But one question. What am I supposed to do if I want to just read (obviously I am not going to write) configuration space of of other PCI card, in the PC ENVIRONMENT, with open core PCI bridge CONFIGURED AS GUEST. Actually I cannot use open core pci bridge in WINXP environment in host mode. regards AdnanArticle: 111438
Adnan wrote: > I got succesfull in using this core. Thanks for your help. But one > question. What am I supposed to do if I want to just read (obviously I > am not going to write) configuration space of of other PCI card, in the > PC ENVIRONMENT, with open core PCI bridge CONFIGURED AS GUEST. Actually > I cannot use open core pci bridge in WINXP environment in host mode. Let me get this right - you want to read another target's config space from the wishbone bus side of the PCI bridge?!? Well, you need to do exactly what a PC host would do - probe the bus for the card in question and then map the base address of the card's config space into the WISHBONE image BAR. Obviously if you can arrange for the host PC application to supply you with the config base address then it's a little easier... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111439
Hi,
I need help for solving the following problem.I am trying to
connect to ML461 JTAG port from PC parallel port by using XILINX
parallel cable through chipscope.But it couldn't connect properly.It
gives the following error.
ERROR: Socket Open Failed. localhost/127.0.0.1:50001
localhost
java.net.ConnectException: Connection refused: connect
ERROR: Failed to open Xilinx Parallel Cable. See message(s) above.
And the same cable setup works properly with the another same board.
I really appreciate your help.
Thanks,
-Ramesh
Article: 111440On 2006-11-03, Mark McDougall <markm@vl.com.au> wrote: > Adnan wrote: > >> I got succesfull in using this core. Thanks for your help. But one >> question. What am I supposed to do if I want to just read (obviously I >> am not going to write) configuration space of of other PCI card, in the >> PC ENVIRONMENT, with open core PCI bridge CONFIGURED AS GUEST. Actually >> I cannot use open core pci bridge in WINXP environment in host mode. > > Let me get this right - you want to read another target's config space > from the wishbone bus side of the PCI bridge?!? > > Well, you need to do exactly what a PC host would do - probe the bus for > the card in question and then map the base address of the card's config > space into the WISHBONE image BAR. Obviously if you can arrange for the > host PC application to supply you with the config base address then it's > a little easier... This is a bit more complicated because a PCI unit will only answer a config request if its IDSEL pin is activated. In practice I understand that IDSEL is almost always wired to some of the high bits of AD. As for opencore's PCI core, I guess that you will have to modify it if you truly have a genuine need for reading the config space of other cards and can guarantee that you can actually make it work reliably for your design in all cases. But wouldn't it be easier to just read the config space of other cards from your device driver and then tell your card whatever it wants to know? Why do you even need to read the config space of other cards? /AndreasArticle: 111441
Hi, I guess maybe they want to seperate property(data) with class/interface/function/task (data and routine). property(data) -> reference class/interface/function/task -> virtual Any comments are welcome! Davy sharp@cadence.com wrote: > Davy wrote: > > > > When studying SystemVerilog, some book said 'virtual' is used to get > > the reference of the interface. But why the language not use 'ref' to > > get interface reference? > > I agree that it is a strange choice. However, 'ref' generally means a > pass-by-reference argument. So what would you use for a virtual > interface variable passed by reference, 'ref ref interface'?Article: 111442
We also had some inhouse people working on these kinds of tools. Some issues we ran into are that code would be written incorrectly or a bug found, then not only would the RTL have to change, the code generator would have to change as well. Which means you're debugging two things and requiring more people and time to develop a product. To make a long story short, for us, it was a big waste of time because the time they spent on it would have been better spent verifying the 20% that you speak of, understanding performance bottlenecks, planning for future product, training, or fine tuning an architecture. I really think code generators are a tough sell. I can't see the value proposition. Coding just isn't on the top ten list of headaches for me or any of the designers that I work with. Again, verifying takes up most of the development effort. From your response, it sounds like you've benefited. Maybe you know more than I do and your experience was much more enjoyable. If you believe in it... put it on the market "Thomas" <dtsi.india@gmail.com> wrote in message news:1162524718.254750.261820@f16g2000cwb.googlegroups.com... > bronzefury wrote: >> Personally, I would avoid code generators to generate RTL for design. > There are different levels of generated code. e.g. > 1> Schematic to code generation e.g. FSM, block diagram,module > integration. > 2> Translating code from one format to another. > 3> Template based code generators etc. > While some are simple (have <10x improvement in total coding time) > others are complex and can result in saving days or even weeks of > coding time. While I personally wont care for the first case the second > case is what interests me. >> Coding RTL is not a bottleneck for me, even on multi-million gate >> designs. >> Some IP is provided by 3rd-party, other IP our developers code. It is >> fairly easy to write Verilog once you have tried and true coding style. >> Why >> would I want to learn a proprietary language to generate a standard >> language? (and get locked-in?). > Applying the 80-20 rule, I would say that 80% of any code is bug free > but identifying the other 20% can take up 80% of my development time. > so would it not be in my interest to reduce the amount of hand written > code by generating code wherever possible? Also quite a few bugs are > because of copy, paste, modify errors whihc a template based code > generator can easily fix. >> In addition, I know exactly what hardware >> I'll generate when I code. For logic circuits that are used often, the >> HDL >> addresses that by allowing designers to create modules or primitives. >> Who >> knows what a code generator will output. I also wouldn't want to be >> locked >> in to a proprietary. > If we are generating RTL the generated code will be verilog or VHDL and > if it is a testcase it will be e,c,SystemVerilog or SystemC and if at > any time we want to "break out" of the code generator "lock-in" we can > always take the generated code and continue from there. > > Note: I dont have a code generator to sell. But have seen various > reusable code generators written by my team mates which have saved > weeks and weeks of coding+debugging effort and was wondering what will > it cost in the market. > Regards > Thomas. >> >> System Verilog addresses many of the my department's needs. >> >> Even if a big name EDA company were to come out with one, I doubt this >> type >> of tool would be purchased. >> >> I think if you want to attack something in the area of chip design, >> you've >> got to address the parts in the design flow that addresses a company's >> development bottlenecks such as verification or physical design. >> >> >> "Thomas" <dtsi.india@gmail.com> wrote in message >> news:1162397407.320469.86740@h48g2000cwc.googlegroups.com... >> > Generalising the question of this discussion I would like to know what >> > does the group here think that code generators are worth? >> > >> > Say Someone comes out with a code generator which requires some input >> > data say, D_in and generates a bunch of output code say, C_out. >> > >> > Given that C_out is something that you already write for your design >> > wether the code generator exists or not, when will the code generator >> > look like a fesible option? >> > >> > Given the following man days(Including coding, verfying and debugging >> > time) for writing D_in and generating C_out VS manual writing of >> > C_out, what is the price you will be willing to pay for the code >> > generator in each case? >> > --------------------------------------------- >> > Development time in Mandays >> > --------------------------------------------- >> > D_in : Manual C_out >> > --------------------------------------------- >> > 1 : 10 >> > 1 : 100 >> > 1 : 1000 >> > >> > If such a code generator appears on the market will your management >> > wait until a bigname EDA comes out with a me too product or will they >> > buy it from a noname developer? >> > Regards >> > Thomas >> > >> > Andy wrote: >> >> Evan Lavelle wrote: >> >> > Ok, is it worth any more than $0 now? :) >> >> >> >> In a word, no. >> >> >> >> Why go to the trouble of learning a new language to try to do things >> >> like macros, loops, random stimulus, etc. when you have the power of >> >> the VHDL language at your disposal in a VHDL testbench? Now, if you >> >> have vectors from an external model/simulation, those can be applied >> >> with text-io relatively easily from within a vhdl testbench that will >> >> run on any vhdl simulator. >> >> >> >> My "unit level tests" are usually at a high enough level that I need a >> >> lot more capability than is available in any vector based scripting >> >> language. >> >> >> >> Andy >> > >Article: 111443
Everything what can parallelize is possibly running faster in Hardware than in Software. lancepickens@gmail.com wrote: > Hi, > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks by designing a > special > purpose chips ala FPGA to run your code? Does anyone have any > experience > with this?Article: 111444
Hi all, I was told that transaction layer communication is the very important thing in SystemVerilog testbench construction. And in VMM and AVM, they use queue (VMM) or virtual interface (AVM) to mimic the Mail-box idea. Mail-box is defined in standard SystemVerilog standard. Why they don't use Mail-box directly? Or is there any disadvantage to use Mail-box? Best regards, DavyArticle: 111445
Hi Kil.
If your code snippet is part of a larger process it is written in a very
strange manner. In general reset and Clock are only examined once at the
beginning of a process.
If the Code is all what's in your Process, then it won't do nothing
useful att all, when used correctly. Why?...
Your Process has three drivers for output signals (data_temp, data,
data_out) There are no inputs to the process, other than its own output
signals.
If you are going to assign values for one of these signals in another
process you have created a multiple driver problem (That's similar to
shortening outputs in real hardware) .
Or maybe you just typed it wrong....
Lokk at this snipppet:
process(reset,clk)
begin
if ( reset = '1' ) then
data_temp <= 0;
data_out <= 0;
elsif (clock'event and clock = '1') then
data_temp <= data;
data_out <= data_temp and not data;
end if;
end process;
here you have two outputs (data_temp and data_out) and one input (data).
You can drive the input from any other process, and both outputs have a
clean reset.
Now you can look for yourself how processes work with readers, drivers,
and delta_cycles inside the simulator.
If you are using Modelsim take a look at your signals in the list
window. There you can see the delta_cycles. Also, note that delta
cycles create no delay. A delta cycle is infinitesimal short (lim -> 0)
and therfore N * 0 will always be 0.
Also try a synthesis run and examine the result (e.g. an RTL-Schematic
generated by your synthesis tool). This may also help to understand
what's going on in your circuit.
have a nice simulation
Eilert
ekavirsrikanth@gmail.com schrieb:
>
> i have a doubt regarding the coding style in vhdl
>
>
> if ( reset = '1' ) then
>
> data_temp <= 0;
>
> elsif (clock'event and clock = '1') then
>
> data <= data_temp;
> data_out <= data_temp and not data;
>
> end if;
> end if;
>
> 1. when i am giving clock data temp data is loaded into data at
> present clock cycle or at next clock cycle.
>
> 2. when i am taking data_out output as given above it is
> getting data_out at next clock cycle not at the present clock cycle
> where data_temp is high and data is low. why this is happening
>
> i need to get the data_out (high for one clock cycle at the
> instant data_temp is high not at the next clock cycle .)
>
> is this problem will be solved during synthesis since i am
> facing the problem during simulation but does it behave the same way
> during synthesis also. since it is a signal assignment signal " <= " a
> minimum of delta delay will be there but will it take the entire clock
> cycle delay.........
>
>
> regards
> kil
>
Article: 111446Hi all, I use conformal to compare logic with netlist and RTL. But some logic is synthesized by retiming. Can I set some constraints to compare retiming netlist and RTL? And is set Black-box means just compare the input and output logic of the Black-box? Best regards, DavyArticle: 111447
"Symon" <symon_brewer@hotmail.com> wrote in message
news:454aa716$1_3@x-privat.org...
> "Tommy Thorn" <tommy.thorn@gmail.com> wrote in message
> news:1162518836.420552.259710@h48g2000cwc.googlegroups.com...
>> lancepickens@gmail.com wrote:
>>> I was wondering if you can improve any dedicated tasks by designing a
>>> special purpose chips ala FPGA to run your code? Does anyone have any
>>> experience with this?
>> Yes.
>
> :-)
>
> Google this.
>
> fpga scientific computing
>
> Guess what? Nearly half a million hits! So, I added 'lumberjack' to the
> search and got it down to 44 hits.
Very good.
Here are some other useful qualifiers and their respective scores:
FPGA scientific computing mongoose 49
FPGA scientific computing pokemon 142
FPGA scientific computing stradivarius 9
FPGA scientific computing zoroastrianism 95,600
FPGA scientific computing paragliding 936
FPGA scientific computing OMG ponies 15
FPGA scientific computing Kellogg's 285
FPGA scientific computing jello 16,200
FPGA scientific computing sefirot 1
FPGA scientific computing boring 103,000
FPGA scientific computing interesting 231,000
Hope that helps,
-Ben-
Article: 111448Laurent Pinchart wrote: > Hi everybody, > > I need to simulate VHDL code using the ISE 8.2i Webpack on Linux. After some > investigation, I found out that two simulators were available: > > - ModelSim, which I have some experience with, would cover all my needs, but > the ModelSim Xilinx Starter edition only runs under Windows. > > - ISE Simulator, which is pretty much unusable from what I've seen so far. > The simulation is not interactive (although I could live with that), but I > haven't been able to watch internal signal values. It seems only the entity > ports can be displayed, which makes debugging much more difficult. > > Is there any proper simulation solution for the Linux platform ? I know > ModelSim has a Linux version, but that's way too expensive for personal > projects. Is there any way to run ModelSim Xilinx Starter edition under > Linux ? I tried running it in Wine, but it complained about not being able > to checkout a valid license, even though the flexlm diagnosis tool reports > no problem at all. > > Any help would be appreciated. Developing VHDL code without a simulator is > near to impossible. > > Best regards, > > Laurent Pinchart > > I haven't used it myself but other posters have commented favourably on Simili (http://www.symphonyeda.com/products.htm). It has a Linux version. It's not free but it's also not that expensive. Hope that helps, AlanArticle: 111449
Logaras, I recommend you to use the new Multi Port Memory Controller (MPMC2) if you can afford (substantial logic consumption). This way you gain maximum preformance, reconfigurability (GUI core configuration to all possible Xilinx supported busses) and a simple user bus - NPI. This way I think you will get the best solution. Cheers Guru Logaras Evangelos wrote: > I want to use the MCH OPB DDR controller (mch_opb_ddr) provided in EDK, to connect a DDR memory module to a custom processor design, which does not support the OPB (On-chip Peripheral Bus). I' going to implement the design in a Virtex-II Pro device (XUP board) Are there any modifications that I have to do to the controller produced by the EDK in order to attach it to my design? Is this usage possible, or the controller can only be attached to a Microblaze processor?
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