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Davy wrote:
> Hi all,
>
> I was told that transaction layer communication is the very important
> thing in SystemVerilog testbench construction.
>
> And in VMM and AVM, they use queue (VMM) or virtual interface (AVM) to
> mimic the Mail-box idea. Mail-box is defined in standard SystemVerilog
> standard.
>
> Why they don't use Mail-box directly? Or is there any disadvantage to
> use Mail-box?
>
> Best regards,
> Davy
Hi Davy
I can't speak for the VMM, but the AVM does use SystemVerilog mailboxes
at the heart of its tlm communication.
The reason this is not obvious to the user is because the AVM channels
(eg tlm_fifo) provide additional functionality over a pure mailbox,
with multiple communication interfaces (put, get, peek, blocking,
non-blocking ...) and analysis ports to send any transaction
written/read to/from the channel to any registered analysis components
(scoreboards, coverage collectors ...)
If you've downloaded the AVM (www.mentor.com/go/cookbook), have a look
at
utilities/systemverilog/avm/tlm/tlm_fifos.svh
for the detailed code and you'll see the mailbox construct.
Also, the AVM's use of virtual interfaces is not related to tlm
communication.
The virtual interface is the mechanism used to link the class based
verification environment to the module based dut.
Generally this is connecting a pin-level transactor (with a virtual
interface) to an actual interface on the dut.
Hope this helps
regards
- Nigel
From laurent.pinchart@skynet.be Fri Nov 03 02:40:57 2006
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Message-Id: <454b1bb6$0$1124$ba620e4c@news.skynet.be>
From: Laurent Pinchart <laurent.pinchart@skynet.be>
Subject: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
Newsgroups: comp.arch.fpga
Date: Fri, 03 Nov 2006 11:40:57 +0100
References: <4549b468$0$21505$ba620e4c@news.skynet.be> <4549baf0$1_1@x-privat.org> <454a1433$0$30044$ba620e4c@news.skynet.be> <454A4F4C.183B4632@xilinx.com>
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Hi Kumar,
Thank you for your quick reply and the information you provided.
Unfortunately, I still haven't been able to get any decent result from the
Xilinx ISE Simulator.
> I would like to provide a bit of information on ISE Simulator that may
> help solve the issue you encountered while using ISE Simulator.
>
> ISE Simulator by default comes up with only the waveform of top level
> signals shown in the Wave Viewer. But, you can add additional signals
> later. Click on the tab named "Sim Hierarchy - <top level unit name>" (you
> will find it adjacent to the "Processes" tab ) in the ISE after you have
> launched ISE Simulator. You
> can then expand hierarchy and see internal structure and signals. Then
> whichever signals you desire to add to Waveform Viewer, you can select
> them and drag them to Wave Viewer. You will see empty Waveform for newly
> added signals if they are not connected to the top, else you would see a
> waveform for the newly added signals.
My problem might come from the fact that I can't seem to launch the
simulator at all. The only option I found to view the waveform is to
double-click on the .tbw file in the Sources tab. The Hierarchy tab then
only shows the top-level signals (ports).
When selecting the test bench file and double-clicking on "Simulate
Behavioral Model" in the Processes tab, ISE starts the simulation process
and outputs the following messages.
Running Fuse ...
WARNING: en_GB.utf8 is not supported as a language. Using usenglish.
WARNING: en_GB.utf8 is not supported as a language. Using usenglish.
WARNING:HDLParsers:3215 - Unit work/pwm_test is now defined in a different
file: was /home/laurent/src/motion/test/sim/pwm_test.ant, now
is /home/laurent/src/motion/test/sim/pwm_test.vhw
WARNING:HDLParsers:3215 - Unit work/pwm_test/testbench_arch is now defined
in a different file: was /home/laurent/src/motion/test/sim/pwm_test.ant, now
is /home/laurent/src/motion/test/sim/pwm_test.vhw
Compiling vhdl file "/home/laurent/src/motion/test/sim/pwm_test.vhw" in
Library work.
Entity <pwm_test> compiled.
Entity <pwm_test> (Architecture <testbench_arch>) compiled.
Parsing "pwm_test_beh.prj": 0.11
Codegen work/pwm_test: 0.00
Codegen work/pwm_test/testbench_arch: 0.01
Building pwm_test_isim_beh.exe
Nothing else happens, no simulator window appears.
> Next, enter "restart" on the tcl console of ISE Simulator ( See tab "Sim
> Console - <top module name>" in the bottom console window) or use Tool bar
> (<-| ) button to restart. Then run for desired length of time (Use Run For
> Tool bar button, or type "run <time> <unit> e.g. run 5000 ns on Sim
> Console) and you would see your newly added signals in the wave viewer.
>
> Also, you can run "step" on tcl console of ISE Simulator to step through
> your code or can open the HDL file and set breakpoints etc. You can type
> "help" on the Sim Console to learn about various other commands you could
> use to interact with the ISE Simulator.
>
> If you have further difficulties using ISE Simulator do let know. The
> documentation on ISE Simulator can be found at :
>
http://toolbox.xilinx.com/docsan/xilinx82/help/iseguide/mergedProjects/xsim/xsim.htm
The link "Launching Xilinx ISE Simulator" in
http://toolbox.xilinx.com/docsan/xilinx82/help/iseguide/mergedProjects/xsim/html/xs_p_launch_pn.htm
leads to a 404 error.
Regards,
Laurent Pinchart
Article: 111451"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:454aba2d$1@clear.net.nz... > > When faced with these 'edicts' you need to get creative :) And I'll give you that...you did get 'creative' suggesting number of unblown fuses as a metric of usage....on a device that probably doesn't have 'fuses' since it's likely EEPROM based, so what you're really suggesting is a metric of how many 'spare' '0's (or '1's) there are to be written into the device....not very useful, but no doubt creative. Would be interesting to try that metric and see how many people nod their head in agreement. I agree with the gist of it, conjure up a metric that can dazzle the easily dazzled if they are the ones holding you back. > > In a PLD vs full hardware implementation, then pin resource does not > need 40% headroom, as clearly the connectors etc do not have that. > > So, you can look at the product-terms and that should come better than 40% > spare. This one actually can be a decent metric. > > The fuse-blow count on loading into a programmer is also another > yardstick, and that will also usually be < 60% (often slightly > lower than PT usage) > > If that fails, you can spec Cross-point usage, and in any CPLD design, > that will be << 60%, so give them that number, or quote the mean of > Fuse-Blow and Cross-Point usage ? > > -jg > KJArticle: 111452
helmut.leonhardt@gmail.com wrote: >Everything what can parallelize is possibly running faster in Hardware >than in Software. And pipelined.Article: 111453
Mark McDougall wrote: > Well, you need to do exactly what a PC host would do - probe the bus for > the card in question and then map the base address of the card's config > space into the WISHBONE image BAR. Obviously if you can arrange for the > host PC application to supply you with the config base address then it's > a little easier... > Sir you are right, I want to read configuration space(only BARS) of another target. But here is the problem. In the implementation of PCI bridge, you can configure it in 2 modes i.e. guest mode and host mode. Now consider test bench of PCI bridge "system.v", IN HOST MODE: whenver it needs to generate configuration cycles it does this from the wishbone side, by writing configuration address register with values like device no, bus no, register no etc. This register is implementation in module config_space. And I can see configuration cycle in waveform. And this register is implemented under `if_def HOST, even the calls of tasks in the system.v is written under if_def host. GUEST MODE: whenever it needs to generate configuration cycle it uses behavioral PCI module to do this. I have tried this by removing if_def host, but it did not work. Your timely reply will certainly help me out. With best regards. AdnanArticle: 111454
Hi NigelE, Thanks a lot! I mis-understand virtual interface. Is there any web seminar or online video talk about AVM? That I want to understand AVM more clearly. Best regards, Davy NigelE wrote: > Davy wrote: > > Hi all, > > > > I was told that transaction layer communication is the very important > > thing in SystemVerilog testbench construction. > > > > And in VMM and AVM, they use queue (VMM) or virtual interface (AVM) to > > mimic the Mail-box idea. Mail-box is defined in standard SystemVerilog > > standard. > > > > Why they don't use Mail-box directly? Or is there any disadvantage to > > use Mail-box? > > > > Best regards, > > Davy > > Hi Davy > > I can't speak for the VMM, but the AVM does use SystemVerilog mailboxes > at the heart of its tlm communication. > > The reason this is not obvious to the user is because the AVM channels > (eg tlm_fifo) provide additional functionality over a pure mailbox, > with multiple communication interfaces (put, get, peek, blocking, > non-blocking ...) and analysis ports to send any transaction > written/read to/from the channel to any registered analysis components > (scoreboards, coverage collectors ...) > > If you've downloaded the AVM (www.mentor.com/go/cookbook), have a look > at > utilities/systemverilog/avm/tlm/tlm_fifos.svh > for the detailed code and you'll see the mailbox construct. > > Also, the AVM's use of virtual interfaces is not related to tlm > communication. > The virtual interface is the mechanism used to link the class based > verification environment to the module based dut. > Generally this is connecting a pin-level transactor (with a virtual > interface) to an actual interface on the dut. > > Hope this helps > > regards > > - NigelArticle: 111455
martstev@gmail.com wrote: > I am using Altera Stratix II FPGA and also power supervisor circuit > which generates reset which it tied to nCONFIG for configuration of > the FPGA. Now, I'd like to generate RESET for the FPGA after the > configuration and Initialization is complete everytime. I can't find a > part that can do that..any suggetions? > or use something like ff_resetn:process(boot_clk) begin if (boot_clk'event and boot_clk='1') then if (reset_cnt/="111") then reset_cnt<=reset_cnt + 1; end if; reset_n<=(reset_cnt(2) AND reset_cnt(1) AND reset_cnt(0)); end if; end process; ff_reset:process(boot_clk) begin if (boot_clk'event and boot_clk='1') then reset<=not reset_n; end if; end process;Article: 111456
If this distanse is 70 mm may I hope that the devise is work correctly? And may I do not connect terminate resistor beetwin Rx- and Rx+ ?Article: 111457
On Fri, 3 Nov 2006 09:35:26 -0000, "Ben Jones" <ben.jones@xilinx.com> wrote: >FPGA scientific computing sefirot 1 A Googlewhackblat! But, you wrecked it. There'll be 2 hits now.Article: 111458
Davy wrote: > Hi NigelE, > > Thanks a lot! I mis-understand virtual interface. > > Is there any web seminar or online video talk about AVM? That I want to > understand AVM more clearly. > > Best regards, > Davy > Hi Davy Try a look at http://www.mentor.com/products/fv/events/ You'll find listed in the online events, our recent 'Hitchhikers Guide to Verification' seminar that covers AVM and other SV verification topics. It's split into 5 sessions so you don't need to watch it all at once ;) Best regards - Nigel From removethisthenleavejea@replacewithcompanyname.co.uk Fri Nov 03 03:57:04 2006 Path: newssvr29.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!npeer.de.kpn-eurorings.net!border2.nntp.ams.giganews.com!nntp.giganews.com!news.astraweb.com!newsrouter-eu.astraweb.com!193.201.147.72.MISMATCH!eweka.nl!hq-usenetpeers.eweka.nl!195.245.201.2.MISMATCH!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!proxy00.news.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1162518049.124275.221090@k70g2000cwa.googlegroups.com> Subject: Re: Scientific Computing on FPGA Date: Fri, 3 Nov 2006 11:57:04 -0000 Lines: 22 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: d3743a13370fc1e0392880e03222d02a23a3302c13e4166060102506454b2e8b NNTP-Posting-Date: Fri, 03 Nov 2006 11:56:59 +0000 Message-Id: <1162555019.16457.0@proxy00.news.clara.net> Xref: prodigy.net comp.arch.fpga:122440 We have a reason number of customers playing with FPGAs on development boards as scientific and maths co-processors. It is happening in a surprising number of applications and markets. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk <lancepickens@gmail.com> wrote in message news:1162518049.124275.221090@k70g2000cwa.googlegroups.com... > Hi, > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks by designing a > special > purpose chips ala FPGA to run your code? Does anyone have any > experience > with this? >Article: 111459
lancepickens@gmail.com wrote: > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks by designing a > special > purpose chips ala FPGA to run your code? Does anyone have any > experience > with this? I think an interesting application are neural networks: http://www.google.com/search?q=neural+network+fpga The speedup compared to normal CPUs should be very high: If you synthize a small network with e.g. 1,000 interconnections on the FPGA, a FPGA clocked with 100 MHz would process the neural network as fast as a normal CPU clocked with over 100 GHz. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 111460
> > or use something like > > ff_resetn:process(boot_clk) > begin > if (boot_clk'event and boot_clk=3D'1') then > if (reset_cnt/=3D"111") then > reset_cnt<=3Dreset_cnt + 1; > end if; > reset_n<=3D(reset_cnt(2) AND reset_cnt(1) AND reset_cnt(0)); > end if; > end process; > > ff_reset:process(boot_clk) > begin > if (boot_clk'event and boot_clk=3D'1') then > reset<=3Dnot reset_n; > end if; > end process; How do you know which value "reset_cnt" will start with after configuration ? Rgds Andr=E9Article: 111461
Anonyma wrote: > Hi, > > This is a question about digilent spartan-3 starter board , > which has a simple 10ns sram and 20ns clock. > I am using a simple controller to access the sram. > During a read operation, the address is stored into > a register and oe is activated at the first rising edge > of the clock and data is retrieved at the next edge. > The 20 ns period seems not large enough to accommodate > the pad delay and external loading. A simple testing > circuit shows that about 0.2% read errors. > There is no error if the reading period > is extended to 2 clocks. > > Is it possible to put some timing or other constraints > in the ucf file to help timing? Thanks. One thing to check is that your final output flops are being mapped to pad registers, and not internal registers. That will eliminate any variability in prop delay due to different paths in the fabric, presenting a stable address more quickly. As a general rule, you should always register outputs at the pad, unless you have some good reason not to, especially for busses. I'm not sure how to do that in ISE, though - I use mostly Altera at the moment.Article: 111462
Dear all, I am new to the EDK and just trying out my first project. I am running EDK 8.2i on Windows XP . I already have an install of cygwin and would prefer to use that rather than the one bundled with the EDK. If I do Hardware->Generate Netlist I get a parse error on the makefile, caused by the line XILINX_EDK_DIR = C:/EDK_82 in system_incl.make. The standard cygwin version of make does not handle the colon in this path. If I substitute XILINX_EDK_DIR = C\:/EDK_82 or XILINX_EDK_DIR = /cygdrive/c/EDK_82 and run the make from the command line it is fine. Unfortunately this file is created by the Platform Studio GUI every time the Generate Netlist command is executed and my modification is overwritten. If I hide my cygwin installation so the Platform Studio uses the bundled install this problem does not occur, but there is a problem later on (when parsing the UCF) that I do not get when running it from the command line. Even if this did work, I really want to use my install of cygwin, as I use it for a great deal more than Platform Studio. I have searched the Xilinx answers and google groups but can't see anything, it could be that I'm just not using the magic words. Any help greatly appreciated! TIA, PeterArticle: 111463
Ray Andraka wrote: > Will Dean wrote: > > > "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > > news:454a42f8$1@clear.net.nz... > > > >>yes, but I'm really interested to see how you design with discrete > >>logic, and still get 40% reserve capacity - I know, use a > >>HEF4894, when a HEF4794 would do ! :) > > > > > > And I was interested in the 'eight or so' chips which fit into the space of > > the TQFP-100... > > > > Will > > > > > > I was wondering the same thing. Wafer scale? Why would it need to be anything esoteric? MSI devices are still in popular use and have migrated to very small packaging. I'm not planning to use the tiniest of packages which are chipscale with 0.5 mm ball pitch. I am planning to use QFN or leaded packages which are all 4 x 4 mm or smaller. I believe the buffer and dual NAND chips are only 2 x 3 mm. I can get a lot of these parts in a 16 x 16 mm space. I guess it has been awhile since you looked at discrete logic? The difference is not because the MSI logic chips have shrunk a lot, but rather that the only small FPGA packages with anything but the smallest of devices are on 0.5 mm pitch. I would love to put a Coolrunner or ispMACH4k on the board. I need 128 MC device and they just don't put them in the smaller packages. I know that Xilinx has lost design wins with us to Altera because of packaging. In this case they all lost to discrete logic because of packaging.Article: 111464
lancepickens@gmail.com wrote: > Hi, > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks by designing a > special > purpose chips ala FPGA to run your code? Does anyone have any > experience > with this? National Instruments do plug-in FPGA cards for their LabView product. DaveArticle: 111465
Sorry, correction. The UCF problem occurs when running the "Generate Bitstream" command. The problem is evident when running the command either using the Xilinx installed cygwin, or using my own (with the XILINX_EDK_DIR correction). This is clearly a new problem altogether, and most probably unrelated to my original cygwin query. Peter Peter Mendham wrote: > Dear all, > > I am new to the EDK and just trying out my first project. I am running > EDK 8.2i on Windows XP . I already have an install of cygwin and would > prefer to use that rather than the one bundled with the EDK. > > If I do Hardware->Generate Netlist I get a parse error on the makefile, > caused by the line > XILINX_EDK_DIR = C:/EDK_82 > in system_incl.make. The standard cygwin version of make does not > handle the colon in this path. If I substitute > XILINX_EDK_DIR = C\:/EDK_82 > or > XILINX_EDK_DIR = /cygdrive/c/EDK_82 > and run the make from the command line it is fine. Unfortunately this > file is created by the Platform Studio GUI every time the Generate > Netlist command is executed and my modification is overwritten. > > If I hide my cygwin installation so the Platform Studio uses the bundled > install this problem does not occur, but there is a problem later on > (when parsing the UCF) that I do not get when running it from the > command line. Even if this did work, I really want to use my install of > cygwin, as I use it for a great deal more than Platform Studio. > > I have searched the Xilinx answers and google groups but can't see > anything, it could be that I'm just not using the magic words. Any help > greatly appreciated! > > TIA, > > PeterArticle: 111466
Thanks to All, it works quite well at 3.125G/duplex lane on -10 speed grade V4FX. Good Luck & nice weekend, ;)Article: 111467
Ben, thanks so much! That is exactly the solution I am searching for ;-) Cheers, Tim Ben Jones schrieb: > Hi Tim, > > "Tim" <gueneysu@crypto.rub.de> wrote in message > news:1162455279.194044.12920@k70g2000cwa.googlegroups.com... > > > > Do you have a good idea how I can pass on the 33rd carry bit (or upper > > bit if sign extended) between the computations and DSP slices without > > using the fabric? It would be so easy, if the P[47]/PCIN[47] carry > > logic wouldn't be inverted...but an inverted carry is probably quite > > useless for my desire. > > Nope, it's pretty easy. > > Take your two 32-bit numbers. Pad one of them out to 48 bits with 0s, and > pad the other out to 48 bits with 1s. Now add them together. > > (*) If there is no carry out of the 32nd stage, then the top 16 bits of the > addition will all work out as 0 + 1 = 1, so P[47] will be 1 (the inverse of > 0, which is what you want). > > (*) If there *is* a carry , it will propagate all the way to the 48th bit > and the output P[47] will be 0 (the inverse of 1, which is what you want). > > Rinse, repeat as required. > > > BTW: what is the reason for the inverted P[47] carry logic? > > Symmetric rounding. It's not described very well in the V4 handbook but it's > sort of hinted at... > > Cheers, > > -Ben-Article: 111468
Evan Lavelle wrote: > On 1 Nov 2006 08:10:07 -0800, "Thomas" <dtsi.india@gmail.com> wrote: > > >If such a code generator appears on the market will your management > >wait until a bigname EDA comes out with a me too product or will they > >buy it from a noname developer? > > I think you may be in even more trouble than me... > > You need to be specific about what you're generating. A human is a > code generator; are you replacing humans? Are you automating something > that's already done? How many people do it? How much time do they > spend on it? Can you do it better than a human? Or just faster? Or > just cheaper? Or is it too difficult for a human to do at all? I am looking at a problem set where We tend to do the same task over and over again for each project. After doing it a few times we know all the possible permutations and combinations and which combination to apply for which problem but it still consumes most of our coding time. Some of the tasks in the problem set may require one person to be dedicated for it throughout the project cycle. The generated code could be similar to what is written by a human and only reduces the development and debug time. For e.g. it may do the same job with the benifit of giving 10X to 1000X improvement in the coding+debugging time. As an example think about writing y=a+b; and using a tool for synthesis and layout. VS using a layout editor to design the ckt one CMOS transistor at a time followed by spice simulations. If this were the 70's will you pay for the current crop of synthesis+layout tools? > > Are you generating IP? If so, you're in trouble. People don't like > buying IP, and they'll only buy it from someone they already trust. While my company is currently working on a set of IP's for its client. My question was more towards the market fesibility of code generators beacause every year EE Times covers a couple of developers who have tried to sell their solution to specific problems in IC design which could be replicated in a a few hundred lines of perl code. > The IP itself is unimportant, anyway: what matters is how well it has > been verified, and whether you can prove it. You're selling a > verification plan and coverage metrics, not HDL code. What I am looking at is a set of tools which help in taking the project from Spec to samples to Product faster than the current manual process would allow. So It could involve 1. The methodology. 2. The code generators to generate verbose codes from a brief high level input. 3. Resolving any other bottlenecks. Going with the Microsoft analogy below. I am looking at something similar to windows apps development using visual C++ where you fireup the relevent wizard click a few buttons and are presented with a template based code framework runnning in a few tens of thousands of lines in which you insert your alogrithm and other code fragments. Note:I know about the code bloat issue for MS VC which a tool for HW design cannot afford. > > Who are you targetting? Is it FPGA users? If so, you're shafted. If > not, you've got no market. Google for anyone who's tried to sell IP > for FPGAs; I can't believe anyone's ever made money doing this. If the > users like it, the FPGA vendors will do it themselves and sell it for > *zero*. Remember, the vendors are selling silicon; they need to bundle > software and IP for free to get market share. If you don't understand > this, think Microsoft and Netscape, WMP, etc. The audience for such tools could be both FPGA and ASIC users. I know about the risk any successful product will have from the established EDA vendors copying it and offering it for free. so my question of wether your manager will buy it from a no name developer or wait for a Known EDA Vendor to come up with a me too product. > > Finally, remember that the EDA market is tiny, and 3 mid-sized fish > are desperately trying to make a living in it, primarily by eating all > the smaller fish. If the FPGA vendors don't get you, then the EDA > vendors will. I dont think any developer will regret beig eaten by a big name EDA vendor if the price is right :) Also I think EDA vendors are currently more interested in me having a bigger code base to verify so that meeting coverage goals will require more run time or more simulators. > The men's underwear market is bigger than EDA. Perhaps > you should be designing a better pair of Y-fronts... > > :) After a decade in the Industry I think I am too old to change professions. I will make sure that my kid keeps his options open ;) Regards Thomas > > EvanArticle: 111469
rickman wrote: > Ray Andraka wrote: > >>Will Dean wrote: >> >> >>>"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message >>>news:454a42f8$1@clear.net.nz... >>> >>> >>>>yes, but I'm really interested to see how you design with discrete >>>>logic, and still get 40% reserve capacity - I know, use a >>>>HEF4894, when a HEF4794 would do ! :) >>> >>> >>>And I was interested in the 'eight or so' chips which fit into the space of >>>the TQFP-100... >>> >>>Will >>> >>> >> >>I was wondering the same thing. Wafer scale? > > > Why would it need to be anything esoteric? MSI devices are still in > popular use and have migrated to very small packaging. I'm not > planning to use the tiniest of packages which are chipscale with 0.5 mm > ball pitch. I am planning to use QFN or leaded packages which are all > 4 x 4 mm or smaller. I believe the buffer and dual NAND chips are only > 2 x 3 mm. I can get a lot of these parts in a 16 x 16 mm space. > > I guess it has been awhile since you looked at discrete logic? > > The difference is not because the MSI logic chips have shrunk a lot, > but rather that the only small FPGA packages with anything but the > smallest of devices are on 0.5 mm pitch. I would love to put a > Coolrunner or ispMACH4k on the board. I need 128 MC device and they > just don't put them in the smaller packages. I know that Xilinx has > lost design wins with us to Altera because of packaging. In this case > they all lost to discrete logic because of packaging. > I admit, I haven't worked with discrete logic much lately. On the other hand, I was considering not just the package, but the board area around the packages for routing. I can see phsyically putting 8 packages in the space taken by the TQFP100, but I still don't see much room to route to those packages. The issue with the smaller packages is insufficient cavity size, and in many cases I guess not enough pins to make it widely appealing.Article: 111470
Well, I solved the UCF problem myself with a bit of RTFM. The project I am using was originally created for EDK 8.1i so uses the old naming convention for DCMs. See answer record 23993. My problem with cygwin and the EDK generated make files still stands though. Peter Peter Mendham wrote: > Sorry, correction. The UCF problem occurs when running the "Generate > Bitstream" command. The problem is evident when running the command > either using the Xilinx installed cygwin, or using my own (with the > XILINX_EDK_DIR correction). This is clearly a new problem altogether, > and most probably unrelated to my original cygwin query. > > PeterArticle: 111471
Ben, thanks so much! This is the kind of solution I am looking for! But just one litte question: I am dealing with a situation which requires me to add several 256bit numbers in a row. Hence, I planned to use a serial design of several interconnected DSP slices each caring for a single 256 addition computing a 32 bit chunk at a time. I intended to pass on the first 32bit chunk from one DSP slice to the next using the PCOUT/PCIN path. Using your proposal I suppose that I still need to know if a carry has been propagated and if the 33..47 bits of PCIN are 1 or 0. I expect that this is necessary to be able to pad the operand of the next DSP fed via the A:B port accordingly (inverse to the last PCIN[33..47]). Am I right with this and do you have a good idea how to manage this? Thanks again in advance for your help ;-) Cheers, Tim Ben Jones schrieb: > Hi Tim, > > "Tim" <gueneysu@crypto.rub.de> wrote in message > news:1162455279.194044.12920@k70g2000cwa.googlegroups.com... > > > > Do you have a good idea how I can pass on the 33rd carry bit (or upper > > bit if sign extended) between the computations and DSP slices without > > using the fabric? It would be so easy, if the P[47]/PCIN[47] carry > > logic wouldn't be inverted...but an inverted carry is probably quite > > useless for my desire. > > Nope, it's pretty easy. > > Take your two 32-bit numbers. Pad one of them out to 48 bits with 0s, and > pad the other out to 48 bits with 1s. Now add them together. > > (*) If there is no carry out of the 32nd stage, then the top 16 bits of the > addition will all work out as 0 + 1 = 1, so P[47] will be 1 (the inverse of > 0, which is what you want). > > (*) If there *is* a carry , it will propagate all the way to the 48th bit > and the output P[47] will be 0 (the inverse of 1, which is what you want). > > Rinse, repeat as required. > > > BTW: what is the reason for the inverted P[47] carry logic? > > Symmetric rounding. It's not described very well in the V4 handbook but it's > sort of hinted at... > > Cheers, > > -Ben-Article: 111472
Ray Andraka wrote: > rickman wrote: > > Ray Andraka wrote: > > > >>Will Dean wrote: > >> > >> > >>>"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > >>>news:454a42f8$1@clear.net.nz... > >>> > >>> > >>>>yes, but I'm really interested to see how you design with discrete > >>>>logic, and still get 40% reserve capacity - I know, use a > >>>>HEF4894, when a HEF4794 would do ! :) > >>> > >>> > >>>And I was interested in the 'eight or so' chips which fit into the space of > >>>the TQFP-100... > >>> > >>>Will > >>> > >>> > >> > >>I was wondering the same thing. Wafer scale? > > > > > > Why would it need to be anything esoteric? MSI devices are still in > > popular use and have migrated to very small packaging. I'm not > > planning to use the tiniest of packages which are chipscale with 0.5 mm > > ball pitch. I am planning to use QFN or leaded packages which are all > > 4 x 4 mm or smaller. I believe the buffer and dual NAND chips are only > > 2 x 3 mm. I can get a lot of these parts in a 16 x 16 mm space. > > > > I guess it has been awhile since you looked at discrete logic? > > > > The difference is not because the MSI logic chips have shrunk a lot, > > but rather that the only small FPGA packages with anything but the > > smallest of devices are on 0.5 mm pitch. I would love to put a > > Coolrunner or ispMACH4k on the board. I need 128 MC device and they > > just don't put them in the smaller packages. I know that Xilinx has > > lost design wins with us to Altera because of packaging. In this case > > they all lost to discrete logic because of packaging. > > > > I admit, I haven't worked with discrete logic much lately. On the other > hand, I was considering not just the package, but the board area around > the packages for routing. I can see phsyically putting 8 packages in > the space taken by the TQFP100, but I still don't see much room to route > to those packages. > > The issue with the smaller packages is insufficient cavity size, and in > many cases I guess not enough pins to make it widely appealing. That is what Xilinx is always saying. But they put the XC2C128 and XC2C256 parts in very fine pitch, small packages (8x8 mm CP132), so clearly the die size vs. package size is not the issue. I just can't use parts with balls on 0.5 mm pitch. I can use a 48 pin QFP which is only 1 mm larger on the board at 9 mm sq or a LFBGA100 with 100 pins and 10 mm sq footprint. I don't need a pin for every macrocell. If Xilinx applied the same logic to the FPGAs with a pin per logic cell, would we need packages with 100,000 pins and up? I wonder if Xilinx would consider their pins to have 12.5% more functionality than their competitor's pins?Article: 111473
If you have kept up your cygwin distribution, it is likely this problem is caused by the newer version of make that gets installed. I don't remember the version numbers for the newer versions, but if you back up to make version 3.80, it will probably work. The problem has to do with supported characters in paths in the version of make. If you are writing your own makefiles, in some cases you can get around the problem by using cygpath to generate compatible paths. Terry Brown On Fri, 03 Nov 2006 14:51:35 +0000, Peter Mendham wrote: > Well, I solved the UCF problem myself with a bit of RTFM. The project I > am using was originally created for EDK 8.1i so uses the old naming > convention for DCMs. See answer record 23993. > > My problem with cygwin and the EDK generated make files still stands though. > > Peter > > Peter Mendham wrote: >> Sorry, correction. The UCF problem occurs when running the "Generate >> Bitstream" command. The problem is evident when running the command >> either using the Xilinx installed cygwin, or using my own (with the >> XILINX_EDK_DIR correction). This is clearly a new problem altogether, >> and most probably unrelated to my original cygwin query. >> >> PeterArticle: 111474
Hi Tim,
"Tim" <gueneysu@crypto.rub.de> wrote in message
news:1162565977.101678.102780@i42g2000cwa.googlegroups.com...
> Ben, thanks so much! This is the kind of solution I am looking for!
>
> But just one litte question: I am dealing with a situation which
> requires me to add several 256bit numbers in a row. Hence, I planned to
> use a serial design of several interconnected DSP slices each caring
> for a single 256 addition computing a 32 bit chunk at a time. I
> intended to pass on the first 32bit chunk from one DSP slice to the
> next using the PCOUT/PCIN path.
I'm not sure I quite understand what you are doing.
Let's simplify and look at a 64-bit addition, done in two halves.
Representing each 32-bit chunk by a letter, you want to do:
BA
+DC
---
=YX
To do this in two stages, first you add A to C and get X and a carry. Then
you add B to D with the carry and get Y (and a final carry which we'll
ignore). So, once you've done the first step, you already have the
least-significant 32 bits of the result (X) - and they play no further part
in the computation. So, why do you need to use the PCOUT path for anything
(other than the carry, if you intend to do the Y=B+D computation in the next
DSP block up)?
Maybe I've misunderstood your algorithm a bit.
Cheers,
-Ben-
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