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Messages from 11175

Article: 11175
Subject: Re: unknown speedgrade question
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 22 Jul 1998 16:36:44 GMT
Links: << >>  << T >>  << A >>
In article <35B5B4FE.66F6@exp2.physik.uni-giessen.de> Erik.Lins@exp2.physik.uni-giessen.de writes:
>The full text on top is:
>XC4020E(TM)

Device type

>HQ208CKM9701

HQ PLCC with heat spreader slug, 208 pins, mfg week 01 of 1997

>A0321A

Batch code. Can be traced to which fab, lot, etc

>some mm below there is a 2C written.

This is what you wanted: -2 speed grade, "C"ommercial temp range

Philip Freidin
( a consultant that doesn't advertise YET :-)
Article: 11176
Subject: Re: FFT in Xilinx FPGA
From: sidhu@halcyon.usc.edu (Reetinder P. S. Sidhu)
Date: 22 Jul 1998 11:52:14 -0700
Links: << >>  << T >>  << A >>

Check out: 
    www.xilinx.com/appnotes/fft.pdf 
for fast FFT on FPGAs using distributed arithemtic. FFT can be speeded up usingCORDIC which is described at: 
    http://users.ids.net/~randraka/pages/supercn.pdf 

Let me know if you need more refs. 

                                                     Reetinder Sidhu 



Jonas Thor wrote: 

  Hello, 

  I'm have an application where I need to perform a 8192 point FFT. The 
  input is only 2 bits (possibly 3 bits). Another option is to implement 
  a 5000 point FFT, but since this is not a power of two I guess the 
  implementation will be tricky.  Now I am considering to implement the 
  FFT in a XC4000 (or a XC6200). 

  Has anyone done this before, or do you know of any suitable 
  references? 

  Jonas Thor 
  Luleå Technical University

Article: 11177
Subject: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Wed, 22 Jul 1998 20:54:54 GMT
Links: << >>  << T >>  << A >>
On Tue, 21 Jul 1998 22:55:51 -0700, "Steven K. Knapp"
<sknapp@optimagic.com> wrote:

>I hate to say this, but without a signature line and from the way that your
>posting is worded, this _could_ be a disguised advertisement written by a
>marketing guy.

Yes, it is strange that somebody would mask their identity completely
in what is usually such an open and friendly group. A quick search up
the tree wrt to anv.net finds associations apparently with eni.net and
hlc.net and even some mention of qsend.com

All said to be spam services of one sort or another.

Is MHB just the really shy, retiring type, or just a desperate plant
from a company that really should know better? We, the people, need to
know.

It does read too good to be true doesn't it? 

Stuart
(Oh, an MTI and Exemplar Distributor amongst other things, OK?)
For Email remove "NOSPAM" from the address
Article: 11178
Subject: Logic Lab Gal Programmer
From: "Jim Hearne" <jimhearne@cix.co.uk>
Date: Thu, 23 Jul 1998 00:09:33 +0100
Links: << >>  << T >>  << A >>
Hi,

I've got a fairly old Lattice GAL programer Called "Logic Lab", it was made
by Programable Logic Tech.
Unfortunatly it seems to be very fussy about the exact type of Lattice 16V8
and 20V10 GALs  it accepts, rejecting most varients with an "incorrect
device" message.
 I suspect this is because the software is too old to know what these
varients are.
I've had a look for info on Programable Logic Tech on the internet but they
seem to have disappeared, certainly the Lattice web sight doesn't list them
as programmer suppliers anymore, they are listed in the old Lattice data
books.

I don't suppose anybody has got a later version of the logic lab PC software
than Rev 2.12, or any idea where i could obtain it.

If there is a more relavant news group than this one then please suggest it.

Many thanks,

JIM Hearne

Email: JIM@Jims-house.cix.co.uk



Article: 11179
Subject: Re: Schematic Symbol Generation
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: 22 Jul 1998 23:41:56 GMT
Links: << >>  << T >>  << A >>
The e-mail address on this particular piece of SPAM is "mbitzko."

Hmmm...the spammer must be an old MAD Magazine reader...Mickey Bitzo
was a generic character that appeared everywhere.

It's still SPAM, tho'.

-andy

-- 
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM

mbitzko@my-dejanews.com wrote in article
<6p2qr3$67p$1@nnrp1.dejanews.com>...
>   Schematic symbol creation is a error prone time consuming effort.
> SymBuilder(tm) automates the creation of heterogeneous schematic
symbol sets
> from fpga compiler reports, from spread sheets, and the content
provided in
> pdf data sheets.  Export interfaces include OrCAD, Protel, and
McCAD for
> SymBuilder Personal and Cadence, Mentor Graphics, and Viewlogic for
> SymBuilder Enterprise. For additional information, refer to
> http://www.ccaes.com.
> 
> -----== Posted via Deja News, The Leader in Internet Discussion
==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member
Forum
> 
Article: 11180
Subject: Re: Any VHDL counter with up & down functions
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Wed, 22 Jul 1998 18:03:44 -0700
Links: << >>  << T >>  << A >>
Use an SR latch to select whether you count up or down.  The clocks are
and'ed together so the inactive one needs to be high.  When the active clock
goes low, it sets/resets the SR latch, then when it goes high it clocks the
counter.   Your clock low width must allow the SR to propagate.

Seems simple enough.

Anding the clocks and setting the SR latch is in one module.  It outputs the
combined clock and up/down control (from the latch).  A second module is a
standard up/down counter.

I won't repeat all the FPGA non-sync/hold time warnings.

Bruce

leslie.yip@asmpt.com wrote in message <6p0sne$gc0$1@nnrp1.dejanews.com>...
>Hello Everybody
>
>I don't know how to implement my previous ASIC-design counter with 2 edge
>triggers -- up and down (up => increment the counter by 1; down [i.e. dn]
=>
>decrement the counter by 1) I used logic gates to implement this function
but
>it seems difficult to describe this with VHDL. I know that another writing
of
>up-down counter is to use a pin to control up/down and another is just a
>clock for incrementing / decrementing the counter.
>
>My 4-bit counter, however, uses four 4-bit counter to connect together by:
>Carry => UP
>('Carry' of lower-bit counter connected to 'UP' of another counter)
>Borrow => DN
>
>Below is a correct but unsynthesizable (by ViewLogic) code of 16-bit
counter.
>Could anyone tell me any idea?
>Thanks a lot in advance.
>
>
>
>-- Leslie Yip, ASM;     July, 17
>
>library ieee;
>use ieee.std_logic_1164.all;
>use ieee.std_logic_unsigned.all;
>
>Entity COUNTER is
>  port( NRST: in std_logic;
>        LOAD: in std_logic;
>        ENABLE: in std_logic;
>        UP,DN: in std_logic;
>        BUSIN: in std_logic_vector(15 downto 0);
>
>        CARRY,BORROW: out std_logic;
>        CNTOUT: out std_logic_vector(15 downto 0)
> );
>end COUNTER;
>
>architecture COUNTER_ARCH of COUNTER is
>signal CNT: std_logic_vector(15 downto 0);
>
>
>begin
>
>
>process(NRST,LOAD,UP,DN)
>begin
>
> if NRST = '0' then
>  CNT <= (others=>'0');
>  CARRY <= '0';
>  BORROW <= '0';
>
> elsif LOAD='1' then
>  CNT <= BUSIN;
>
> elsif UP='1' and UP'event and ENABLE = '1' then
>    if CNT = "1111111111111111" then
>      CARRY <= UP;
>    else
>      CARRY <= '0';
>    end if;
>  CNT <= CNT + 1;
>
> elsif DN='1' and DN'event and ENABLE = '1' then
>   if CNT = "0000000000000000" then
>      BORROW <= DN;
>    else
>      BORROW <= '0';
>    end if;
>  CNT <= CNT - 1;
>
> end if;
>end process;
>
>
>  CNTOUT <= CNT;
>
>
>
>end COUNTER_ARCH;
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum


Article: 11181
Subject: Re: Schematic Symbol Generation
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 22 Jul 1998 21:33:23 -0400
Links: << >>  << T >>  << A >>


Andy Peters wrote:

> Mickey Bitzowas a generic character that appeared everywhere.

sounds kind of like a definition of spam, huh?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11182
Subject: AD: Reading Secured Devices
From: acstran@aol.com (ACS Tran)
Date: 23 Jul 1998 01:49:50 GMT
Links: << >>  << T >>  << A >>
If you have a secured device, such as a GAL, PAL, microcontroller, and FPGA,
with the contents of which you are interested in recovering. Providing the
contents are not copyrighted and/or you are the copyright holder, we may be
able to help you. Please call 1-404-228-1693 for further details.

Article: 11183
Subject: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 22 Jul 1998 23:49:37 -0400
Links: << >>  << T >>  << A >>
MHB wrote:
> 
> Thank you all who responded to my posting of last week asking opinions of
> Active-VHDL.  My original suspicions were confirmed with overwhelming
> enthusiasm, it is a great behavioral simulator with a very intuitive user
> interface.  The hdl editor and State Diag. Editor are a nice touch, this was
> important to me especially when I evaluated Model Tech's Model Sim and
> couldn't believe they don't give you any way to enter text and have the
> nerve to charge $4600, the kicker that I loved about the Aldec tool, was the
> automatic Test Bench generator.....Great feature!!!!!! (there technical
> people were also very helpful).
> 
> I never bothered looking at Orcad as my understanding is they have very good
> layout tools but their simulator basically doesn't work well.  Apparently
> there are some compliancy issues: I.e.. there vhdl simulator is not IEEE
> compliant and I am hearing nightmares or problems simulating its
> code....I'll pass on that eval.
> 
> Well I am a happy camper, I just ordered Active-VHDL and recommend it to
> all.  There demo can be obtained from there web site www.aldec.com  and they
> also sent me two books which I found informative.

For a second opinion on Active-VHDL. I tried "their" demo software and
found that it is not very compatible with Foundation M1.4. If you use
any Logiblox in a schematic, the VHDL component instantiations must be
hand edited into the VHDL code generated from the schematic. At least
this is what Aldec support told me when I asked them why I was getting
errors. 

I would really like to use "their" test bench simulation capabilities.
Does anyone know if I was told wrong. I just don't have a lot of time
right now to play with getting this to work. They did tell me that this
problem will be fixed when Foundation M1.5 comes out next month.


-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 11184
Subject: C- interface
From: bonics@my-dejanews.com
Date: Thu, 23 Jul 1998 07:11:27 GMT
Links: << >>  << T >>  << A >>
Hello ,
I am working on the connection of a hardware prototyping board to the Leapfrog
VHDL simulator of Cadence.

I have found some interfaces on the market ,e.g. logic modeler, by Synopsys
,but would like to hear any other possible solution from you.

I also tried to integrate some C functions on the simulator ,following the
help manual ,but it does not work. Any solutuions ? Thank you very much in
andvanced . Benjamin

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11185
Subject: Re: Schematic Symbol Generation
From: "Gareth Baron" <Gareth.Baron@eng.efi.com>
Date: Thu, 23 Jul 1998 12:12:57 -0700
Links: << >>  << T >>  << A >>
FYI:

I have worked with Mike Bitzko from CCAES.  He's a good guy and the stuff
they do is good.  They will generate symbol definitions from netlists for
you.  They also offer a translation service (across CAD platforms) which may
be useful to some FPGA people here.

It may be a bit of an advertisement but it may also be useful to some
Engineers out there.  I wouldn't go as far as calling it a blatant SPAM.



Andy Peters wrote in message <01bdb5ca$4c8e7e30$4601fc8c@shootingstar>...
>The e-mail address on this particular piece of SPAM is "mbitzko."
>
>Hmmm...the spammer must be an old MAD Magazine reader...Mickey Bitzo
>was a generic character that appeared everywhere.
>
>It's still SPAM, tho'.
>
>-andy
>
>--
>Andy Peters
>Sr. Electrical Engineer
>National Optical Astronomy Observatories
>apeters@noao.edu.NOSPAM
>
>mbitzko@my-dejanews.com wrote in article
><6p2qr3$67p$1@nnrp1.dejanews.com>...
>>   Schematic symbol creation is a error prone time consuming effort.
>> SymBuilder(tm) automates the creation of heterogeneous schematic
>symbol sets
>> from fpga compiler reports, from spread sheets, and the content
>provided in
>> pdf data sheets.  Export interfaces include OrCAD, Protel, and
>McCAD for
>> SymBuilder Personal and Cadence, Mentor Graphics, and Viewlogic for
>> SymBuilder Enterprise. For additional information, refer to
>> http://www.ccaes.com.
>>
>> -----== Posted via Deja News, The Leader in Internet Discussion
>==-----
>> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member
>Forum
>>


Article: 11186
Subject: IT Professionals - Join the NetVital Survey and make a difference
From: "Ed Perez" <ed@netvital.com>
Date: Thu, 23 Jul 1998 13:58:55 -0700
Links: << >>  << T >>  << A >>
Do you ever wonder what your peers are thinking about the IS/IT problems you
face? Would you like to know what they've done to solve those same problems?

Sorry for the intrusion, but the vital information obtained from the ongoing
NetVital commissioned survey of IT Professionals may be of interest to you.
Visit us at: http://www.netvital.com/survey

Join the survey and become a panelist. Or subscribe to receive the survey
results, or visit us online and search our archives. You will agree, the
survey results is an excellent tool to guide you through those critical IT
decisions we all face.

Current Survey in Progress: IP Net Monitorring
Next Survey: Year 2000 Cobol - Sign up now and make your opinions known!

Thank you,

Ed Perez
Ed@netvital.com
The NetVital Survey
“The Ongoing Survey of Enterprise-Grade Network Issues”
http://www.netvital.com/survey/

Past Survey Analysis
http://www.netvital.com/survey/archive
- Controlling Web Development
- Network Security










Article: 11187
Subject: High-radix division
From: Vitit Kantabutra <vkantabu@computer.org>
Date: Thu, 23 Jul 1998 18:16:02 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------2DB20074BC15A49FDF8BFF79
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I would like to implement a high-radix (radix = power of two) divider in
some fpga technology, and would like to know whether there is a need out
there for such a divider.  If so, how many bits should the operands be?
Should it be pipelined?  What sort of performance or cost?

I noticed that neither Xilinx or Atmel's library seems to have dividers
of any sort right now.  Am I right?

--------------2DB20074BC15A49FDF8BFF79
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Vitit Kantabutra
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             Vitit Kantabutra
n:              Kantabutra;Vitit
org:            Idaho State University
email;internet: vkantabu@computer.org
title:          Associate Professor of Computer Science
x-mozilla-cpt:  ;0
x-mozilla-html: TRUE
version:        2.1
end:            vcard


--------------2DB20074BC15A49FDF8BFF79--

Article: 11188
Subject: Silicore VHDL 8-bit RISC uC core for FPGA
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Fri, 24 Jul 1998 01:26:24 GMT
Links: << >>  << T >>  << A >>
Silicore Corporation now has a VHDL 8-bit RISC uC core for FPGA
available.  The processor is compatible with the industry standard
'PIC' processors.  For more information see <www.silicore.net>.


Article: 11189
Subject: Interface
From: benjamin.carrion-schaefer@hl.siemens.de
Date: Fri, 24 Jul 1998 07:00:09 GMT
Links: << >>  << T >>  << A >>
Hi I am working on the interface of an Aptix board(for ASIC prototyping
board)with a VHDL compiler (Leapfrog of Cadance). I would like to know if you
have any suggestion,because a hardware modeler is quit expensive.
Thanks in advanced,
Benjamin

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11190
Subject: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
From: Nicolas Matringe <nicolas.matringe@dot.com.fr>
Date: Fri, 24 Jul 1998 09:15:53 +0200
Links: << >>  << T >>  << A >>
TMItools wrote:
> 
> Dear Eric,
> 
> I just saw your email post about the Altera EPC1 programming problem.

I don't remember the original post.
We bought a DataIO ChipWriter yesterday and had no problem burning EPC1.
We only had to look for a newer version of the software on DataIO Web
site.

Nicolas MATRINGE                   DotCom SA
Conception électronique            16 rue du Moulin des Bruyères
Tel: 00 33 1 46 67 51 00           92400 COURBEVOIE
Fax: 00 33 1 46 67 51 01
mail reply : remove one dot from the address (guess which :-)
Article: 11191
Subject: Altera FPGA/EPLD Downloader that works with any voltage (1.8 - 5 V)
From: Eugene Fleisher <eugenef@jps.net>
Date: Fri, 24 Jul 1998 00:30:02 -0700
Links: << >>  << T >>  << A >>
FPGA Downloader for Altera FPGA/EPLD
Works with any voltage of FPGA I/O pins 1.8 - 5 V

$105.00 QTY 1 - (compare to $150 Altera solution - this one is better)
Replaces Altera ByteBlaster and ByteBlasterMV downloaders

You will never need another downloader

Please visit us at http://www.jps.net/eugenef

Sincerely,

NEF Design, Inc.
e-mail: eugenef@jps.net

Article: 11192
Subject: [***] SRAM Controller
From: "iccra" <iccra@netsgo.com>
Date: Fri, 24 Jul 1998 19:35:09 +0900
Links: << >>  << T >>  << A >>
iccra wrote

i am working on the implement of SRAM Controller for Hardware prototype
board.. with Active VHDL, and Altera

Can anyone offer suggestions on how to implement Controller
in VHDL ?

thanks in advance.



Article: 11193
Subject: Re: Too much advertising in this news group?
From: "Austin Franklin" <darkroo5m@ix.netcom.com>
Date: 24 Jul 1998 13:52:53 GMT
Links: << >>  << T >>  << A >>


Greenwood Systems <greenwoodsys@yahoo.com> wrote in article
<35b4581b.0@nnrp1.news.uk.psi.net>...
> Having recently posted and item this news group with respect to the
interest
> there would be in a contract VHDL/FPGA startup company, I assume I am
partly
> responsible for all this thread.

Partly, yes.

> I never intended any upset and apologise for any caused.
> 
> My belief was that this newsgroup covered all aspects of FPGA technology
and
> development and that my post was not inappropriate

It is hard to tell what is and what isn't appropriate, as when you look in
the news group and see advertising, you assume it is OK.  Also, the charter
has not been posted in this NG in a long time, and probably needs to be
done so on a regular basis so people can read it and understand what the
purpose of this news group is.

I believe this groups charter prohibits the posting of commercial or
advertising posts.  The purpose of this group is technical discussions, NOT
sales, marketing and personnel search.

Austin Franklin
darkroom@ix.netcom.com


Article: 11194
Subject: Re: Schematic Symbol Generation
From: "Austin Franklin" <darkroo5m@ix.netcom.com>
Date: 24 Jul 1998 14:14:35 GMT
Links: << >>  << T >>  << A >>


mbitzko@my-dejanews.com wrote in article
<6p2qr3$67p$1@nnrp1.dejanews.com>...
>   Schematic symbol creation is a error prone time consuming effort.
> SymBuilder(tm) automates the creation of heterogeneous schematic symbol
sets
> from fpga compiler reports, from spread sheets, and the content provided
in
> pdf data sheets.  Export interfaces include OrCAD, Protel, and McCAD for
> SymBuilder Personal and Cadence, Mentor Graphics, and Viewlogic for
> SymBuilder Enterprise. For additional information, refer to
> http://www.ccaes.com.

Along with being sort-of-SPAM, isn't it funny how so many EDA companies
fail to post pricing...either in posts or even on their web sites.  I
really don't want to talk to some sales person (who usually just wants to
get all my particulars and add me to some SPAM data base so they can call,
mail or e-mail me) before they will give me any pricing information.  All I
just want to know if the product is economically feasable.  It really
amazes me.

Austin Franklin
darkroom@ix.netcom.com

Article: 11195
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: "Austin Franklin" <darkroo5m@ix.netcom.com>
Date: 24 Jul 1998 14:21:58 GMT
Links: << >>  << T >>  << A >>
Wade D. Peterson <peter299@maroon.tc.umn.edu> wrote in article
<6p8nqs$2ij$1@news1.tc.umn.edu>...
> Silicore Corporation now has a VHDL 8-bit RISC uC core for FPGA
> available.  The processor is compatible with the industry standard
> 'PIC' processors.  For more information see <www.silicore.net>.

$10,000 for a PIC processor that takes up 80% of an OR2CA15-4 FPGA?  It
would seem more prudent to buy a far less expensive exteral PIC processor
and a smaller/cheaper FPGA to do the same job.

Does anyone else think this is a real step backwards?

Austin Franklin
darkroom@ix.netcom.com

Article: 11196
Subject: ORCAD 3
From: vesta7x@earthling.net
Date: Fri, 24 Jul 1998 15:11:05 GMT
Links: << >>  << T >>  << A >>
THE NEWEST PROGRAMS FOR YOU !!
Price for each CD from 10-20US$

ORCAD 3


 ORCAD
1. ORCAD CAPTURE 7.01
2. ORCAD CAPTURE 7.1
3. ORCAD CAPTURE 7.331
4. ORCAD CAPTURE 7.335
5. ORCAD CAPTURE 7.01
 PCAD
6. PCAD 4.5
7. PCAD 4.5 RUS
8. PCAD 8.5
9. PCAD UTILS
10. PCAD LIBRARIES
11. PSAVE6 1.0B
12. ALI M3135 DRIVERS FOR PCAD
 OTHER
13. ADVANCED ROUTE 3.1
14. AMD MATCHPRO
15. ARRL RADIO DESIGNER 1.50 - AF/RF
16. ATLANTA SIGNAL PROCESSORS FOR MS-DOS
17. ATMEL ATF1500 FILTER 1.01
18. CAM WORKS 97
19. CAM/CAD PRO 2.1.3A
20. CAM/CAD 2.1.2F
21. CAM350 FAMILY 4.5
22. CIMCAD 1.5
23. CIRCUIT MAKER 3.03
24. DESIGNWORKS SUITE 3.2 - SHEMATIC CAPTURE, DIGITAL SIMULATION
25. ELECTRONIC WORKBENCH 4.1
26. ELECTRONIC WORKBENCH 5.0
27. ENERGY PRO 1.0 FOR WIN95/NT
28. FRANCLIN ADVANCED DEVELOPMENT SYSTEM 8.62
29. GERB TOOL 6.2
30. MACHXL 2.0
31. MAX + PLUS II
32. MICROCAL ORIGIN 5.0
33. PALASM 4 1.5
34. PLDSHELL PLUS 3.0.2
35. PRINTGL 1.42
36. PROTEL 2.0
37. PROTEL ADVANCED PCB 2.80
38. SHEILA LOWE’S HANDWRITING ANALYSER 3.1
39. SPECTRA DEMO 5.2
40. SPECTRA PLUS 4.00.5 32BIT FOR WIN95/NT
41. SPECTRALAB 4.32.07 16BIT
42. TABLE CURVE 2D
43. TECHNICAL GRAPHICS & DATA ANALYSIS 5.0
44. TERRAMODEL FOR WIN95/NT
45. TEST BENCHER PRO 3.1D FOR WIN95/NT
46. TRAXMAKER 2.06
47. VERILOG MODELLER, VHDL ANALYSIS AND CPLD DESIGN
48. VIEWSYNTHESIS 5.0.2
49. VINNY GRAPHICS 4.70 16&32BIT
50. WAVE GENERATOR 1.1
51. WINBOARD 3.15 & WINDCRAFT 2.01
52. WINFIT 1.4
53. WORKVIEW OFFICE 7.31

MODERN ORCAD


ORCAD CAPTURE 7.0
ORCAD CAPTURE SUPPLEMENTAL LIBRARIES
MICROSIM DESIGN LAB 7.1
PCAD 4.5
PCAD 4.5 RUS & GUIDE RUS
PCAD 8.5
PCAD UTILITIES
PSAVE6 1.0B PCAD HARDLOCK EMULATOR
ALI M3135 DRIVERS FOR PCAD
CHIPS LIBRARY (SOVIET STANDART)
TRANSLATION UTILITIES FROM PCAD 4.5 TO 7 & 8.5
SIEMENS & SEIKO CHIPS CATALOG
AND MORE . . . .
PROJECTION ORCAD CAPTURE

ORCAD
ORCAD CAPTURE 6.0
ORCAD CAPTURE 6.10H
ORCAD EDA TOOLS 4.02
ORCAD PCB 386+ 2.20H
ORCAD SDT 386+ 1.21AH
ORCAD 4.20EDA TOOLS
ORCAD 4.42(SDT, PCB, PLD 1.10)
PCAD
PCAD 6.02
PCAD 7.0
PCAD 8.5 A
PCAD 6.0/7.0 FINAL 200% CRACK
PCAD UTILITIES
PSAVE6 1.0B PCAD HARDLOCK EMULATOR
MICROSIM
MICROSIM DESIGN CENTER 5.2
MICROSIM DESIGN CENTER 5.3
MICROSIM SCHEMATICS EVOLUTION VERSION
PSPICE 5.1 FOR WIN
PSPICE 5.3 FOR WIN
PSPICE 5.4 FOR WIN
XILINX
XACT 4000 TQ/VQ PACKAGES UPDATE
XACT DS290-PC1 4.15
XACT DS390-PC1 4.15
XACT DS520-PC1 1.30
XACT SUPPLEMENTAL DISK 1.0
OTHERS
1996 NATIONAL ELECTRICAL CODE
ALI M3135 DRIVERS FOR PCAD, ORCAD
AUTOCAD LITE R2.0
AUTOCAD LITE R3.0 FOR WIN95
ELECTRICAL SYMBOLS FOR ACAD LT 2
CIMCAD 2.0
CIRCUIT CAD 2.0
MAXROUTE 3.0
TANGO SERIES 2.0
TANGO PRO 3.0 (NO KEY)
VERSACAD 8.0 ENHANCED
VISIO 3.0
VISIO 4.0
VISIO 4.0 TECHNICAL 16 & 32 BIT
ORCAD AND MICROELECTRONIC


ORCAD CAPTURE 7.0 FOR WIN/WIN95/NT
ORCAD CAPTURE SUPPLEMENTAL LIBRARIES
MICROSIM DESIGN LAB 7.1 FOR WIN
PCAD V4.5
PCAD 4.5 RUS & GUIDE RUS
PCAD 8.5
PCAD UTILITIES
PSAVE6 1.0B PCAD HARDLOCK EMULATOR
ALI M3135 DRIVERS FOR PCAD
CHIPS LIBRARY (SOVIET STANDART)
TRANSLATION UTILITIES FROM PCAD 4.5 TO 7 & 8.5
SIEMENS & SEIKO CHIPS CATALOG
ACTIVE FILTER DESIGN
CCICAP CAD V1.2
CIRCUIT LAYOUT SYSTEM V1.0
CLIPS
DC CAD V1.0 -ELECTRONIC BOARD DESIGNER
DC CIRCUIT ANALYSIS V1.4 ASP
DC CIRCUIT TRAINING SYSTEM V2.0 ASP
DC ELECTRONIC INTRODUCTION
DESIGN CENTER - SYSTEM 3 V.5.2 EVALUTION FOR WIN
DIGITAL CHALLENGE V2.0 ASP
DIGITAL SIMULATOR FOR WIN
DRAFT CHOISE V2.15A
EDIT PCB INTRO VERSION 1.1
EEDRAW ELECTRICAL ENGINEERING DRAWING V2.O
EIRP CHART -ELECTRONIC CALCULATOR FOR WIN
ELECTRIC V9.2
ELECTRICAL & ELECTRONIC FORMULAS V3.0
ELECTRON TUTOR!!!
ELECTRON V3.0A
ELECTRONIC CIRCUIT DESIGNER V3.1
ELECTRONIC TOOLBOX V2.0 -EVALUTION VERSION
ELECTRONICS BASIC CALCULATIONS
ELECTRONICS CALCULATIONS PROGRAMS
ELFTREE V1.E32
ENGINEERING BBS LIST
ETCAI- ELECTRICAL & ELECTRONIC INSTRUCTION
EZ555 V95 -DESIGN PROGRAM FOR POPULAR 555 TIMER
FLASH! CAD V.1.0 ASP DOS DIAGRAMING PROGRAM
INTERACTIVE ENGINEERING MANUAL V3.12 ASP
LEARN ABOUT VARIOUS COMPUTER CPU CHIP
LOGIC CIRCUIT ANALYSIS V1.1 ASP
LOGSIM -LOGICAL SIMULATON PROGRAM V2.1
ME
MICROCAD V4.0 -AUTOCAD * DXF SUPPORT
NOVA 7.0 -CIRCUIT ANALYSIS SYSTEM
PADS-PBS -CIRCUIT DESIGNER SYSTEM
PANEL V2.1 -ELECTRICAL DESIGN PROGRAM
PC DRAFT CAD V3.06A
PC ECAP V3.0 ASP -AC CIRCUIT ANALYSIS PROGRAM
PC SHEMATIC DOCUMENTATION V3.2
PC TECH LEARNING SYSTEM V1.0
PC TRACE V5.0
PCB CAD
PCC & MATCHC
POWER FACTOR -LABORATORIES ELECTRICAL TESTING
RESIDENTAL ELECTRIC REPORTS V1.0
RESISTOR CALSULATIONS
RFAMP- DESIGN SMALL SIGNAL RF USING S-PARAMETRS
SHEMATIC MASTER V 1A
TINY DIGITAL CIRCUIT ANALYSIS V1.1
TRIGGER -ENGINEERING UTILITY FOR WIN


If you should  lost me please send faxmessage to:
Tel/Fax:+441716917580
Tel/fax: +493069088166 Germany
Tel/fax: +18883189841 (USA)
Norman Tel: +370 8969309
ICQ: 9839999   http://wwp.mirabilis.com/9839999    9839999@pager.mirabilis.com
Norman

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11197
Subject: FPGA board interface
From: benjamin.carrion-schaefer@hl.siemens.de
Date: Fri, 24 Jul 1998 15:18:50 GMT
Links: << >>  << T >>  << A >>
Does anyone have an idea howI can connect an Aptix board (FPGA board for fast
prototyping of ASICS) with a VHDL compiler (Leapfrog in my case) A logic model
is too expensive.
Thank you very much in advanced
Benjamin

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11198
Subject: Re: Schematic Symbol Generation
From: Joe Brunsberger <jbruns@no.spam.com>
Date: Fri, 24 Jul 1998 09:46:18 -0700
Links: << >>  << T >>  << A >>
Actually,  this tool has saved me a lot of time. It used to take me about
2 days
to create symbols/package etc.  for our medium sized FPGA's. Now I can do
this
in about 20 minutes. At $400 for the software it is not a bad deal. (I
can't find
any engineers at that price :-).

I don't mind a little bit of advertising for something useful, after all
it is not an invitation
to the latest sex-site or some other junk.

Just my 2 cents.

BTW: I am not affiliated with CCAES at all.

--
Joe Brunsberger
Sr. Design Engineer
MO System Design




Andy Peters wrote:

> It's still SPAM, tho'.
>

..... stuff deleted ....

> > SymBuilder(tm) automates the creation of heterogeneous schematic
> symbol sets
> > from fpga compiler reports, from spread sheets, and the content
> provided in
> > pdf data sheets.  Export interfaces include OrCAD, Protel, and
> McCAD for
> > SymBuilder Personal and Cadence, Mentor Graphics, and Viewlogic for
> > SymBuilder Enterprise. For additional information, refer to
> > http://www.ccaes.com.
> >
>



Article: 11199
Subject: Re: High-radix division
From: Medical Electronics Lab <rosing@physiology.wisc.edu>
Date: Fri, 24 Jul 1998 12:47:54 -0500
Links: << >>  << T >>  << A >>
Vitit Kantabutra wrote:
> 
> I would like to implement a high-radix (radix = power of two) divider in
> some fpga technology, and would like to know whether there is a need out
> there for such a divider.  If so, how many bits should the operands be?
> Should it be pipelined?  What sort of performance or cost?
> 
> I noticed that neither Xilinx or Atmel's library seems to have dividers
> of any sort right now.  Am I right?
> 

don't know about the libraries, but there's a good demand for
modular arithmetic on smart cards for crypto applications.
lowest possible cost is a winner, performance is secondary.
Banks (which have lots of money :-) are *very* interested.

Patience, persistence, truth,
Dr. mike


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