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Messages from 112075

Article: 112075
Subject: Re: Xilinx 2 DCMs with delay on lock
From: "VC" <chopra_vikram@excite.com>
Date: 15 Nov 2006 14:50:35 -0800
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Brad Smallridge wrote:
>
> > Hio folks,
> >
> > I'm trying to find a document that describes adding
> > a delay between the inverted lock signal of one DCM
> > that feeds forward to the reset of the next DCM.
> >
> > I have seen this document before, so I know it exists.
> > Anyone know where I can find this doc?
> >
> > Brad Smallridge
> > aivision
> >
> >
>
> Brad, I believe it is in the old app notes describing the DLLs in Virtex.

I think the following refers to the situation you have described -
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19005
http://direct.xilinx.com/bvdocs/appnotes/xapp132.pdf 

HTH.


Article: 112076
Subject: Re: 8080 FSGA model in an FPGA
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 16 Nov 2006 11:55:15 +1300
Links: << >>  << T >>  << A >>
logjam wrote:
> I would like to eventually make an 8080 out of Field Solderable Gate
> Arrays.  ;)  (trasistors)

Why ?!

> 
> First, I want to design the whole thing in an FPGA for logic proofing
> There will be a LOT of circuit boards required for this and I want to
> limit failure...  My idea was to create small macro blocks that emulate
> standard TTL chips and use those TTL chips (or customized versions) to
> build the processor.
> 
> Any recomendations on how to proceed?  I want to make the core I/O
> compatible with the 8080, which means full status signal support and a
> 2 phase clock.

Do you also want this voltage compatible ?
What is the target of this project ?

-jg



Article: 112077
Subject: Re: how to filter glitches and mutliple transitions?
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 16 Nov 2006 12:02:03 +1300
Links: << >>  << T >>  << A >>
Frank Buss wrote:

> I have built a prototyp board with wires between the FPGA and an external
> component. With the scope I can see glitches (looks like from crosstalk
> when switching other signals) and multiple transitions are detected by the
> FPGA when switching signals. Looks like the noise is < 200 ns. The period
> of the wanted signal is > 3 us. I think with a PCB there would be less
> problems, but there is lots of space left inside the FPGA, so it should be
> possible enhance the signal with logic so that it works even with the noisy
> wired prototype. What do you do normally to solve this kind of problems?
> 
> My idea is to use a low-pass filter: a n bit counter, which is incremented
> with system clock, if the input signal is 1 and decremented otherwise. If
> all n bits are 1, the counter is not incremented and if all bits are 0, it
> is not decremented. If the highest bit is set, then the sampled signal is
> considered as 1, otherwise as 0. I could encapsulate this function within a
> VHDL entity, so it is easy to use it for multiple input signals and maybe a
> generic for specifying n.

Yes, that's a saturating counter.
You have one minor blindspot in your topology, if you merely use the
MSB as the output, it can spin quite quickly if the pattern makes your 
counter go 01111 / 10000 / 01111 / 10000

So, better is to take something like the saturating sense logic
(which has to already be there), and feed a JK FF, or SyncSET/SyncRST

-jg


Article: 112078
Subject: Re: Influence of temperature and manufacturing to propagation delay
From: "Andy" <jonesandy@comcast.net>
Date: 15 Nov 2006 15:23:53 -0800
Links: << >>  << T >>  << A >>
I do not have direct numbers for any supplier (that I can share
anyway), but the "norm" for commercial electronics components is
between 3 and 6, with very few suppliers close to 6. This is from a
military reliability conference a few years ago at which a colleague
attended/presented.

My point is not what the exact quality level of any supplier's
component is, it is that none are at 100.0000%, and you need margin to
account for that. If y'all want to miss the forest for the trees
arguing over exactly what level of quality a specific supplier
delivers, go ahead...

Andy




Austin Lesea wrote:
> John,
>
> I, too, have a problem with people making assumptions about our product
> quality.
>
> If you are interested, we do publish what our criteria are, and the
> probability that a part is a test escape of some sort, or fails upon
> first insertion, etc. is something we do document, and care deeply about.
>
> http://www.xilinx.com/products/quality/
>
> Obviously, we strive like most companies for a '0 defect' goal, and like
> all companies, we somehow are unable to ship only perfect components
> (funny how the real world conspires against perfection).
>
> Since every bitstream is different for each application, and we don't
> know any of them, it makes assuring 100% perfection a daunting task, yet
> one that we willingly accept and strive towards.
>
> In fact, if you really want a component that is absolutely best tested
> for exactly your bitstream (design), then you should be using the
> EasyPath(tm) program, as that program has a customer program for the
> FPGA that exercises the paths and logic that you actually are going to
> depend on (based on your design).
> 
> Austin


Article: 112079
Subject: Problems with Opencores' I2C "READ" function
From: "markus" <markus_1401@yahoo.com>
Date: 15 Nov 2006 15:32:32 -0800
Links: << >>  << T >>  << A >>
Hello,

I am wondering if any of you have encountered a problem in which the
Opencores' I2C "READ" function failed. The problem I am seeing is that
when prior to the data read from the slave device, the master doesn't
write the 7-bits device address and a logic HIGH (to indicate a read),
specifically, the master failed to send the last logic HIGH to indicate
a read. As a result the slave thinks a write operation was sent as
opposed to a read operation. I am wondering if any of you have
encountered something similar to this.

In order to initiate a read sequence, I first sent a write to the
slave, followed by the memory address location of the slave's register,
then I sent the read instruction. I checked whether wb_ack_o pin is
asserted and that the TIP signal have been negated before proceeding
from one command to another. Is there something else that I need to do
prior to executing from one command to another (i.e. more pauses?)? Or
do I need to turn on clock stretching? I thought the clock stretching
is supported automatically.

I used Virtex-II Pro to implement the I2C interface. The device is
communicating to a Finisar XFP. I've seen this problem occuring
specifically to Finisar XFPs. In addition, I have one board that
exhibit this issue regardless of the XFPs used. My goal is trying to
isolate whether this is an XFP issue or how I implement the I2C cores.

Any comments and suggestions are welcomed.

Thanks,
-M


Article: 112080
Subject: USB and AHB
From: "terabits" <tera.bits@gmail.com>
Date: 15 Nov 2006 15:34:17 -0800
Links: << >>  << T >>  << A >>
Hi

I am very new to usb, I have some basic questions reagarding usb with
ahb .

Suppose i have a ahb structure like 2 masters and 2 slaves.
i want to have 2usb devices .....will this usb (usb 2.0 device) sit on
the slave side ?
what will be on the master side ? suppose one dma as a master i have
will the another master be arm processor or can it be some other usb
device ? if so what could it be ?
why at all usb has to interface with ahb ? only to interact with
memories and arm processors ?
can you give me a real time example like take a usb pen drive where
will ahb comes into picture when i am connecting it to the computer ?

regards


Article: 112081
Subject: Re: how to filter glitches and mutliple transitions?
From: "John McGrath" <tails4e@gmail.com>
Date: 15 Nov 2006 15:49:21 -0800
Links: << >>  << T >>  << A >>
I assume, because we are talking about glitches, that changes in Sig
are effectively asynch to the clk - so shouldn't it be synchronised
with a 2 flip-flop synchronizer first, or else the counter could count
incorrectly? (some flip-flops seeing the value as a 1, others seeing it
as a 0 ) perhaps the nature of the system means it can recover from
that, but I think it would make it safer.
(I've had a few glasses of wine too, so the same disclaimer for me!)
Cheers
John

PeteS wrote:
> A small fix :)
>
> PeteS wrote:
> > Frank Buss wrote:
> >> I have built a prototyp board with wires between the FPGA and an external
> >> component. With the scope I can see glitches (looks like from crosstalk
> >> when switching other signals) and multiple transitions are detected by
> >> the
> >> FPGA when switching signals. Looks like the noise is < 200 ns. The period
> >> of the wanted signal is > 3 us. I think with a PCB there would be less
> >> problems, but there is lots of space left inside the FPGA, so it
> >> should be
> >> possible enhance the signal with logic so that it works even with the
> >> noisy
> >> wired prototype. What do you do normally to solve this kind of problems?
> >>
> >> My idea is to use a low-pass filter: a n bit counter, which is
> >> incremented
> >> with system clock, if the input signal is 1 and decremented otherwise. If
> >> all n bits are 1, the counter is not incremented and if all bits are
> >> 0, it
> >> is not decremented. If the highest bit is set, then the sampled signal is
> >> considered as 1, otherwise as 0. I could encapsulate this function
> >> within a
> >> VHDL entity, so it is easy to use it for multiple input signals and
> >> maybe a
> >> generic for specifying n.
> >>
> >
> > Hi Frank
> >
> > You are describing a soft filter.
> >
> > I have a number of them in a current design (it's in a rather noisy
> > environment) and I use a 5 bit counter as part of a state machine.
> >
> > I assume you have an appropriate clock, so simply qualify the signal as
> > continuously present (or perhaps mostly present) for the 3us you state.
> >
> > With a 10MHz clock, for example, a 5 bit counter is almost perfect (and
> > besides, we can always terminate at count = 30 ;)
> >
> > I like your approach, but this is simple and uses pretty limited resources.
> >
> > so, somewhere
> >
> > wire Sig; // the signal we are watching
> > reg SigValid; // valid indicator
> > reg [4:0] SigCount;
> >
> >
> > always @(posedge clk)
> > begin
> > if (!Sig)
> > begin
> >     SigCount <= 5'b00000; // signal disappeared, clear counter
> >     SigValid <= 1'b0;
> > end
> > else if(Sig & SigCount < 28)
> > begin
> >     SigCount <= SigCount+1;
> >
> > end
> // fix the next line
> // was else if (SigCount == 28)
>   else if (Sig & SigCount == 28)
>
> // qualify signal properly
>
> > begin
> >     SigValid <= 1'b1; // Signal has been true for 30
> > consecutive                       // clocks.
> > end
> > end
> >
> > Simple, as I said, and if you find bugs, I state in my defence I have
> > had a couple of glasses of wine :)
> > 
> > 
> > Cheers
> > 
> > PeteS


Article: 112082
Subject: Re: 8080 FSGA model in an FPGA
From: "logjam" <grant@stockly.com>
Date: 15 Nov 2006 15:50:48 -0800
Links: << >>  << T >>  << A >>
> we have 6000 times 5 components (2 diodes, 2 res, one trans) = 30,000
> components.
> Does this still sound practical?

Not practical, but fun!  I have a 88x40 inch display made out of 19,008
T 1 3/4 LEDs for example...  ;)

> Anyway, it should be fairly easy to design the CPU for FPGA implementation.
> I'd forget the TTL component emulation, and use either VHDL or Verilog,
> or maybe
> one of the RTL synthesis tools.  These are able to specify a CPU very
> concisely.

Would there be a simple way of generating some sort of human
understandable information that would help generate a schematic?

Thanks,
Grant


Article: 112083
Subject: Re: 8080 FSGA model in an FPGA
From: "logjam" <grant@stockly.com>
Date: 15 Nov 2006 15:55:58 -0800
Links: << >>  << T >>  << A >>
> Do you also want this voltage compatible ?
> What is the target of this project ?

I want to be able to use it in place of a real 8080.  I don't care
about the 12 and -5v power supply.  The whole project is just for fun.

The reason I thought TTL would be a good place to start is because of
the AMD 2901 9080 emulator book.  Also, if standard TTL devices were
replicated using transistors then each "module" of the processor could
possibly be tested with an IC tester.

I figure it will have a few thousand LEDs too.  Like an LED for every
register, microcode bit, etc.

Grant


Article: 112084
Subject: Re: how to filter glitches and mutliple transitions?
From: Frank Buss <fb@frank-buss.de>
Date: Thu, 16 Nov 2006 01:01:28 +0100
Links: << >>  << T >>  << A >>
PeteS wrote:

> I like your approach, but this is simple and uses pretty limited resources.
> 
> so, somewhere

> if (!Sig)
> begin
> 	SigCount <= 5'b00000; // signal disappeared, clear counter
> 	SigValid <= 1'b0;
> end

maybe this is sufficient, but this solution won't filter negative glitches.
See below for my try, with hysteresis (thanks Jim for the blindspot). I
wonder if it is overkill :-)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity low_pass_filter is
	generic(
		counter_max: positive := 30;
		hysteresis: positive := 5);
	port(
		clock: in std_logic;
		reset: in std_logic;
		input: in std_logic;
		output: out std_logic);
end entity low_pass_filter;

architecture rtl of low_pass_filter is

constant low_limit: natural := (counter_max - hysteresis) / 2;
constant high_limit: natural := low_limit + hysteresis;

signal counter: natural range 0 to counter_max := 0;
type state_type is (low, high);
signal state: state_type := low;

begin

	filter: process(clock)
	begin
		if reset = '1' then
			counter <= 0;
			state <= low;
			output <= '0';
		elsif rising_edge(clock) then
			-- update output with hysteresis
			case state is
				when low =>
					if counter > high_limit then
						output <= '1';
						state <= high;
					else
						output <= '0';
					end if;
				when high =>
					if counter < low_limit then
						output <= '0';
						state <= low;
					else
						output <= '1';
					end if;
			end case;
			
			-- update counter
			if input = '1' then
				if counter < counter_max then
					counter <= counter + 1;
				end if;
			else
				if counter > 0 then
					counter <= counter - 1;
				end if;
			end if;
		end if;
	end process;
	
end architecture rtl;


Test bench:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity low_pass_filter_test is
end entity low_pass_filter_test;

architecture rtl of low_pass_filter_test is

	constant bits: positive := 2;
	signal input: std_logic := '0';
	signal output: std_logic := '0';
	signal clock: std_logic := '1';

begin

  low_pass_filter_test_inst: entity low_pass_filter
    generic map(
		counter_max => 30,
		hysteresis => 5)
    port map(
      clock => clock,
	  reset => '0',
	  input => input,
	  output => output);

	test_it: process
	    procedure do_clock(count: positive) is
	    begin
			for i in 1 to count loop 
				clock <= not clock;
				wait for 10 ns;
				clock <= not clock;
				wait for 10 ns;
			end loop;
		end do_clock;
	begin
		-- startup
		input <= '0';
        do_clock(30);
		
		-- test high hysteresis
		input <= '1';
        do_clock(1);
	    assert output = '0' report "failed 1." severity failure; 
        do_clock(17);
	    assert output = '0' report "failed 2." severity failure; 
        do_clock(1);
	    assert output = '1' report "failed 3." severity failure; 
		input <= '0';
        do_clock(3);
	    assert output = '1' report "failed 4." severity failure; 
		input <= '1';
        do_clock(3);
	    assert output = '1' report "failed 5." severity failure; 
		
		-- test low hysteresis
		input <= '0';
        do_clock(7);
	    assert output = '1' report "failed 6." severity failure; 
        do_clock(1);
	    assert output = '1' report "failed 7." severity failure; 
        do_clock(1);
	    assert output = '0' report "failed 8." severity failure; 
		input <= '1';
        do_clock(1);
	    assert output = '0' report "failed 9." severity failure; 
        do_clock(3);
	    assert output = '0' report "failed 10." severity failure; 
		
		-- test low saturation
		input <= '0';
        do_clock(40);
	    assert output = '0' report "failed 11." severity failure; 

		-- test high saturation
		input <= '1';
        do_clock(40);
	    assert output = '1' report "failed 12." severity failure; 
		
	    assert false report "No failure, simulation was successful." severity
failure; 
	end process;

end architecture rtl;


-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 112085
Subject: Re: 8080 FSGA model in an FPGA
From: "JJ" <johnjakson@gmail.com>
Date: 15 Nov 2006 17:34:55 -0800
Links: << >>  << T >>  << A >>

logjam wrote:
> > Do you also want this voltage compatible ?
> > What is the target of this project ?
>
> I want to be able to use it in place of a real 8080.  I don't care
> about the 12 and -5v power supply.  The whole project is just for fun.
>
> The reason I thought TTL would be a good place to start is because of
> the AMD 2901 9080 emulator book.  Also, if standard TTL devices were
> replicated using transistors then each "module" of the processor could
> possibly be tested with an IC tester.
>
> I figure it will have a few thousand LEDs too.  Like an LED for every
> register, microcode bit, etc.
>
> Grant

Since this is for fun and not practicality you could try and google for
home built computers using TTL or better still CMOS etc. There really
are a few souls out there that have built TTL boxes in this day and
age. I almost contemplated this 20yrs ago for a PDP8 with a real core
stack and transistors but I found some sense.

Also you could actually reverse engineer a real 8080 with a modest
microscope, the details are pretty clear after you remove the
passivation, a dead device will be okay too. It only used IIRC 1 layer
of metal, poly, active area and hidden poly diff contacts. I did some
reverse engineering on this part so its no so bad.

As for circuit design the 8080 was an NMOS design with mostly dynamic
logic and some sparing use of static logic (not sure) so the schematic
could be recovered with some basic knowledge of chip design circa
1975. Adison Wesley had a couple of old 1984 VLSI books that describe
all the basic NMOS tricks used in the day, you would need to follow
gate clocking, bootstrapping, cheap C latches etc. The clocks would
have been used to strobe latches and flops and logic might well have
been merged.

The 8085 might be a whole lot easier being IIRC all static (and 5V) so
you wouldn't find as much mind boggling circuit tricks, just logic.
IIRC it was mostly pin compatible so would be alot easier.

I would atleast stick to TTL compatible CMOS parts to save yourself SI
hell.

John Jakson
transputer guy


Article: 112086
Subject: Re: 8080 FSGA model in an FPGA
From: "Tim" <tim@rockylogiccom.noooospam.com>
Date: Thu, 16 Nov 2006 02:17:03 -0000
Links: << >>  << T >>  << A >>

JJ wrote...
>
> logjam wrote:
>> > Do you also want this voltage compatible ?
>> > What is the target of this project ?
>>
>> I want to be able to use it in place of a real 8080.  I don't care
>> about the 12 and -5v power supply.  The whole project is just for fun.
>>
>> The reason I thought TTL would be a good place to start is because of
>> the AMD 2901 9080 emulator book.  Also, if standard TTL devices were
>> replicated using transistors then each "module" of the processor could
>> possibly be tested with an IC tester.
>>
>> I figure it will have a few thousand LEDs too.  Like an LED for every
>> register, microcode bit, etc.
>>
>> Grant
>
> Since this is for fun and not practicality you could try and google for
> home built computers using TTL or better still CMOS etc. There really
> are a few souls out there that have built TTL boxes in this day and
> age. I almost contemplated this 20yrs ago for a PDP8 with a real core
> stack and transistors but I found some sense.

Many years ago, on a visit to Amdahl I saw a complete 470 built with 
wire-wrapped TTL. How about doing the 8080 with a giant wire-wrap board of 
CMOS PALs. One PAL per "logical chunk," with lots of outputs reserved for 
the LEDs. It might even be possible to buy an old wire-wrap X-Y frame on 
eBay. Maybe cook up a standard module with a little PAL, LEDs, some drivers, 
I/O pins, and JTAG. You would be the defining case for JTAG's ability to 
program hundreds of PALs in series ;-)

And good luck with the clock tree...

Tim 



Article: 112087
Subject: Re: 8080 FSGA model in an FPGA
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 16 Nov 2006 15:50:14 +1300
Links: << >>  << T >>  << A >>
logjam wrote:
>>Do you also want this voltage compatible ?
>>What is the target of this project ?
> 
> 
> I want to be able to use it in place of a real 8080.  I don't care
> about the 12 and -5v power supply.  The whole project is just for fun.

I saw someone did a 4004, as plug-able device.

So do you want to run some real 8080 SW on this ?
Over what memory bus/sizes ?

> 
> The reason I thought TTL would be a good place to start is because of
> the AMD 2901 9080 emulator book.  

Why not follow that line, with a bit-slice emulation of the 8080 ?

A very good starting point there, would be to take something like
the open source Mico8 8 bit CPU from lattice, and tweak/tune it to
allow a SW emulation layer of 8080, as you will have MHz to spare :)

> Also, if standard TTL devices were
> replicated using transistors then each "module" of the processor could
> possibly be tested with an IC tester.

If you have one available. Transistors I'd take as a dead-end,
unless you have a soldering fetish !

Tiny logic maybe, but that's going to be more a PCB design problem, not 
an 8080 design problem, and you will chew $$ on the PCBs

CPLDs, or FPGAs are probably the best level to do this project.
Low enough that you CAN get to every logic element, but still
high enough to be affordable, small and low power.

> 
> I figure it will have a few thousand LEDs too.  Like an LED for every
> register, microcode bit, etc.

Or, a TV/VGA output that emulates such LEDs ?

-jg


Article: 112088
Subject: Re: Microblaze store
From: Murali <vmurali@mit.edu>
Date: Wed, 15 Nov 2006 22:06:46 -0500
Links: << >>  << T >>  << A >>
mk wrote:
> On Wed, 15 Nov 2006 09:06:17 +0100, "Göran Bilski"
> <goran.bilski@xilinx.com> wrote:
> 
>> Hi Murali,
>>
>> It can never proceed until the memory access is finished.
>> MicroBlaze currently don't have an out-of-order exexcution.
>>
>> Göran
>>
>> "Murali" <vmurali@mit.edu> wrote in message 
>> news:455a9e33$0$558$b45e6eb0@senator-bedfellow.mit.edu...
>>> Hi all
>>>
>>> Does Microblaze (v 5.00) stall on store (to a non-BRAM memory) till it 
>>> receives an ack, or can it process other instructions while this store is 
>>> on fly?
> 
> A write buffer is different from OOE. You don't necessarily have to
> wait for the N number of writes to succeed (where N is the size of
> your write buffer) before executing the next instruction(s) perfectly
> in order.

So then, does Microblaze does have a store/write buffer? The reference 
guide doesn't mention about it and I saw somewhere that some older 
version of Microblaze in fact didnt have a store buffer.

Thanks
Murali

Article: 112089
Subject: Re: Microblaze store
From: mk <kal*@dspia.*comdelete>
Date: Thu, 16 Nov 2006 05:12:21 GMT
Links: << >>  << T >>  << A >>
On Wed, 15 Nov 2006 22:06:46 -0500, Murali <vmurali@mit.edu> wrote:

>mk wrote:
>> On Wed, 15 Nov 2006 09:06:17 +0100, "Göran Bilski"
>> <goran.bilski@xilinx.com> wrote:
>> 
>>> Hi Murali,
>>>
>>> It can never proceed until the memory access is finished.
>>> MicroBlaze currently don't have an out-of-order exexcution.
>>>
>>> Göran
>>>
>>> "Murali" <vmurali@mit.edu> wrote in message 
>>> news:455a9e33$0$558$b45e6eb0@senator-bedfellow.mit.edu...
>>>> Hi all
>>>>
>>>> Does Microblaze (v 5.00) stall on store (to a non-BRAM memory) till it 
>>>> receives an ack, or can it process other instructions while this store is 
>>>> on fly?
>> 
>> A write buffer is different from OOE. You don't necessarily have to
>> wait for the N number of writes to succeed (where N is the size of
>> your write buffer) before executing the next instruction(s) perfectly
>> in order.
>
>So then, does Microblaze does have a store/write buffer? The reference 
>guide doesn't mention about it and I saw somewhere that some older 
>version of Microblaze in fact didnt have a store buffer.

This documents http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf
says it's possible to configure the processor with a write-through
datacache but it's not clear if the writes stall the processor or the
cache controller can complete the write on its own. If latter the data
cache can be used as a write buffer with additional features.

Article: 112090
Subject: Re: Xilinx 2 DCMs with delay on lock
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 15 Nov 2006 22:37:18 -0800
Links: << >>  << T >>  << A >>
Yes. Thank you VC. Those did help.

Brad Smallridge
aivision



Article: 112091
Subject: Re: 8080 FSGA model in an FPGA
From: scott moore <nospam@nowhere.com>
Date: Wed, 15 Nov 2006 22:39:17 -0800
Links: << >>  << T >>  << A >>
Jon Elson wrote:

> Anyway, it should be fairly easy to design the CPU for FPGA implementation.
> I'd forget the TTL component emulation, and use either VHDL or Verilog, 
> or maybe
> one of the RTL synthesis tools.  These are able to specify a CPU very 
> concisely.
> 
> Jon
> 

Or use the one that already exists on http://www.opencores.org :-)

Scott Moore

Article: 112092
Subject: ise 7.1
From: "andrew browning" <ahb3@mac.com>
Date: 15 Nov 2006 23:03:21 -0800
Links: << >>  << T >>  << A >>
i'm trying to install ise 7.1 on solaris 10 running on parallels VM.
Setup quits after the following meesages:

/tmp/windu/windu_clientd50: cannot execute
nohup: ./windu_registryd50: no such file or directory

Has anyone ever seen this or have a clue how i might get around it?


Article: 112093
Subject: Re: Microblaze store
From: "Göran Bilski" <goran.bilski@xilinx.com>
Date: Thu, 16 Nov 2006 08:49:13 +0100
Links: << >>  << T >>  << A >>
MicroBlaze don't have a store buffer but some memory controllers has it.
But from MicroBlaze point of view, it will stall until it get an acknowledge 
(doesn't have to be really stored in the memory).
If you using the XCL interface for caches, it has a built-in store buffer.
For MicroBlaze when using XCL a store will take 2 clock cycles if there is 
room in the store buffer independent on when the word actually get written 
into memory.

Göran

"mk" <kal*@dspia.*comdelete> wrote in message 
news:3fsnl2li7tkdeitee4jm24shrakulhcs9s@4ax.com...
> On Wed, 15 Nov 2006 22:06:46 -0500, Murali <vmurali@mit.edu> wrote:
>
>>mk wrote:
>>> On Wed, 15 Nov 2006 09:06:17 +0100, "Göran Bilski"
>>> <goran.bilski@xilinx.com> wrote:
>>>
>>>> Hi Murali,
>>>>
>>>> It can never proceed until the memory access is finished.
>>>> MicroBlaze currently don't have an out-of-order exexcution.
>>>>
>>>> Göran
>>>>
>>>> "Murali" <vmurali@mit.edu> wrote in message
>>>> news:455a9e33$0$558$b45e6eb0@senator-bedfellow.mit.edu...
>>>>> Hi all
>>>>>
>>>>> Does Microblaze (v 5.00) stall on store (to a non-BRAM memory) till it
>>>>> receives an ack, or can it process other instructions while this store 
>>>>> is
>>>>> on fly?
>>>
>>> A write buffer is different from OOE. You don't necessarily have to
>>> wait for the N number of writes to succeed (where N is the size of
>>> your write buffer) before executing the next instruction(s) perfectly
>>> in order.
>>
>>So then, does Microblaze does have a store/write buffer? The reference
>>guide doesn't mention about it and I saw somewhere that some older
>>version of Microblaze in fact didnt have a store buffer.
>
> This documents http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf
> says it's possible to configure the processor with a write-through
> datacache but it's not clear if the writes stall the processor or the
> cache controller can complete the write on its own. If latter the data
> cache can be used as a write buffer with additional features. 



Article: 112094
Subject: Re: USB and AHB
From: "bm" <nospam@nospam.fr>
Date: Thu, 16 Nov 2006 09:01:29 +0100
Links: << >>  << T >>  << A >>
USB Pen drive = USB Device = Slave.
=> you have to control it with a USB HOST IP
=> this IP should be integrated on the AHB Bus as a ....Slave

To do list :
- integrate the USBHOSTSLAVE IP , host part ,  ( available at 
opencores.org ) . This IP  is Wishbone Slave
=> simple WB<-> AHB Bridge to be written (or maybe exists somewhere)
- add a USB PHY on your board (1 PHY IC is advised in the usbhostlave design 
package)
- make some tests (basic USB cmds => look in the USBHOSTSLAVE doc)
- go ahead (SW, driver,etc....)
You should make preliminary tests in simulation with a Slave USB model



"terabits" <tera.bits@gmail.com> wrote in message 
news:1163633657.029718.142070@f16g2000cwb.googlegroups.com...
> Hi
>
> I am very new to usb, I have some basic questions reagarding usb with
> ahb .
>
> Suppose i have a ahb structure like 2 masters and 2 slaves.
> i want to have 2usb devices .....will this usb (usb 2.0 device) sit on
> the slave side ?
> what will be on the master side ? suppose one dma as a master i have
> will the another master be arm processor or can it be some other usb
> device ? if so what could it be ?
> why at all usb has to interface with ahb ? only to interact with
> memories and arm processors ?
> can you give me a real time example like take a usb pen drive where
> will ahb comes into picture when i am connecting it to the computer ?
>
> regards
> 



Article: 112095
Subject: Re: Old Spartan-II, worth prototyping?
From: "John Adair" <g1@enterpoint.co.uk>
Date: 16 Nov 2006 00:03:06 -0800
Links: << >>  << T >>  << A >>
Whilst FPGA families have an average life of 2 years as the lead family
in appropriate sector (low cost sector, or high performance sector),
they usually have a very long lifetimes. I wouldn't be surprised if
most of the Sparatan-II family are still around in 10 years time going
by past history.

For price/performance though it is always hard to beat whatever the
latest family is and unless you need the a special feature like 5V
tolerance (without resistors or bus switches), or less power supply
rails, it is usually worth going to the latest.

John Adair
Enterpoint Ltd.

zwsdotcom@gmail.com wrote:
> John_H wrote:
> > If you inherited a box of the "pocket PCs" mid-2001, would you use those in
> > your systems?
>
> Maybe :) It depends how big the box was.
>
> > If your need is limited to stock on hand and the performance you get from
> > them is sufficient, I'd say "go for it" but if you end up purchasing more of
> > these devices in the long run, you'll probably be MUCH better with a current
>
> I just did a quick price compare vs. Spartan-III and I see what you
> mean. I don't have a specific need for these parts right now; nothing I
> build uses FPGAs. I was planning to lay down some footprints in "spare"
> space and wire the FPGA to the footprint of the 8-bit micro I use in an
> existing design, for experiments. But if I can't be sure of getting
> these parts on an ongoing basis, there's no point.


Article: 112096
Subject: Re: 8080 FSGA model in an FPGA
From: David R Brooks <davebXXX@iinet.net.au>
Date: Thu, 16 Nov 2006 01:30:13 -0800
Links: << >>  << T >>  << A >>
JJ wrote:
> logjam wrote:
>>> Do you also want this voltage compatible ?
>>> What is the target of this project ?
>> I want to be able to use it in place of a real 8080.  I don't care
>> about the 12 and -5v power supply.  The whole project is just for fun.
>>
>> The reason I thought TTL would be a good place to start is because of
>> the AMD 2901 9080 emulator book.  Also, if standard TTL devices were
>> replicated using transistors then each "module" of the processor could
>> possibly be tested with an IC tester.
>>
>> I figure it will have a few thousand LEDs too.  Like an LED for every
>> register, microcode bit, etc.
>>
>> Grant
> 
> Since this is for fun and not practicality you could try and google for
> home built computers using TTL or better still CMOS etc. There really
> are a few souls out there that have built TTL boxes in this day and
> age. I almost contemplated this 20yrs ago for a PDP8 with a real core
> stack and transistors but I found some sense.

See my Simplex page http://members.iinet.com.au/~daveb/simplex/simplex.html
links to a webring of such designs.
> 
> Also you could actually reverse engineer a real 8080 with a modest
> microscope, the details are pretty clear after you remove the
> passivation, a dead device will be okay too. It only used IIRC 1 layer
> of metal, poly, active area and hidden poly diff contacts. I did some
> reverse engineering on this part so its no so bad.
> 
> As for circuit design the 8080 was an NMOS design with mostly dynamic
> logic and some sparing use of static logic (not sure) so the schematic
> could be recovered with some basic knowledge of chip design circa
> 1975. Adison Wesley had a couple of old 1984 VLSI books that describe
> all the basic NMOS tricks used in the day, you would need to follow
> gate clocking, bootstrapping, cheap C latches etc. The clocks would
> have been used to strobe latches and flops and logic might well have
> been merged.
> 
Back in the 70's, all kinds of dirty logic tricks were used: the 
circuitry was not the clean, canonical stuff you are forced to build 
using TTL or other stock logic family.
Dynamic gates for instance: first clock charges the node, then the logic 
optionally discharges it on the next clock.
If you are building with discrete transistors, bear in mind that the 
standard discrete flipflop was a master-slave design, with the master 
implemented in just such dynamic logic (as 2 capacitors).
By transistors, I assume you mean bipolars? This precludes another MOS 
logic dodge: the pass gate. This is a series switch, which exploits the 
symmetry of a basic MOS device (source & drain are interchangeable).

A good reference would be Mead & Conway's "Introduction to VLSI 
Systems", Addison Wesley, 1984.

Article: 112097
Subject: Re: In defence of Austin and Xilinx
From: Thomas Reinemann <tom.reinemann@gmx.net>
Date: Thu, 16 Nov 2006 11:40:47 +0100
Links: << >>  << T >>  << A >>
PeteS schrieb:
> At bottom:
> 
> PeteS wrote:
> 
> You are obviously clocking things from somewhere. A margin of 300 ps or
> so can get lost in the rise/fall times of a hot clock source. Have you
> characterised your clock inputs properly for post-PAR analysis?

Yes, four FPGAs shall work synchronous, therefore an external PLL comes
into operation. The clock frequency has been characterized within the ucf.

I solved the problem, simply by increasing this characterized frequency.

Is there a guide line, to avoid such problems before they emerge? Where
can I specify the jitter of an external clock source?

Tom

Article: 112098
Subject: Compiling Linux Kernel for ML405
From: Peter Mendham <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk>
Date: Thu, 16 Nov 2006 10:57:16 +0000
Links: << >>  << T >>  << A >>
Dear all,

I'm trying to build a straightforward Linux Kernel for the Xilinx ML405 
board and I'm running into one small problem.  The build gets most of 
the way through and fails at link stage, missing a crucial function. 
The function in question is part of the Xilinx OCP BSP in the file 
xpacket_fifo_v2_00_a.c  Tracing make, as best I can, this file never 
gets built.  The only code that uses the function is in a driver and 
hence only "meets up" with the functions at final link time, which is 
where the problem arises.

Now, I'm certainly not a make guru, so I don't really understand how 
make calculates the dependencies during make dep (all these .depend 
files) and I'm not sure how make then uses these to build the required 
output files.  How do I coax make into building the missing file(s)? 
Does anyone have any experience building kernels for the ML405?

I'm building a PPC development 2.4 downloaded using bitkeeper.  I'm 
(mostly) following the instructions here: 
http://splish.ee.byu.edu/projects/LinuxFPGA/configuring.htm which are 
for the ML403, but close enough.

Any help - however small - would be great.

TIA,

-- Peter

Article: 112099
Subject: Re: Problems with Opencores' I2C "READ" function
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 16 Nov 2006 22:15:53 +1100
Links: << >>  << T >>  << A >>
markus wrote:

> I am wondering if any of you have encountered a problem in which the
> Opencores' I2C "READ" function failed. 

I've successfully used the core on 2 different designs...

> In order to initiate a read sequence, I first sent a write to the
> slave, followed by the memory address location of the slave's register,
> then I sent the read instruction. I checked whether wb_ack_o pin is
> asserted and that the TIP signal have been negated before proceeding
> from one command to another. Is there something else that I need to do
> prior to executing from one command to another (i.e. more pauses?)? Or
> do I need to turn on clock stretching? I thought the clock stretching
> is supported automatically.

Here's the sequence I use to read a byte...

// device address and dummy write
WR(TXR,{dev,0})
WR(CR,STA|WR)
wait for not tip and ack
// memory address
WR(TXR,addr)
WR(CR,WR)
wait for not tip and ack
// start reading
WR(TXR,{dev,1})
WR(CR,STA|WR)
wait for not tip and ack
WR(CR,RD|ACK|STO)
wait for not tip
RD(RXR)

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266



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