Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 112650

Article: 112650
Subject: Re: run a counter without a clock
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 27 Nov 2006 09:50:32 -0000
Links: << >>  << T >>  << A >>
"Al" <alessandro.basili@cern.ch> wrote in message 
news:ek9t4f$5n2$1@cernne03.cern.ch...
>
> The datasheet reports derating for Junction Temperature, which is strictly 
> related to the power and is not ambient temperature at all.
Hi Al,
So, I guess by the above statement you don't really mean that the junction 
temperature is independent of the ambient temperature, do you?
Cheers, Syms. 



Article: 112651
Subject: Re: run a counter without a clock
From: "jonas" <jpistor@uni-bremen.de>
Date: 27 Nov 2006 02:03:55 -0800
Links: << >>  << T >>  << A >>
Hi.

I've done some experiments with inverter chain loops on a Virtex 2p.
The frequencies changed about +- 20% from the mean value just depending
on place&route.
If you manage it to get a very fast (but dirty) clock with your
asynchronus logic, with less than 5 ns, I think it should be possible
to measure its frequency onboard with use of a slower stable external
clock. So you could control the pulse length with multiples of the
fundamental frequency of your asynchronus clock.
If you measure a period duration of 3 ns, then you take 2 periods...
Good luck...

Jonas


Article: 112652
Subject: Re: Xilinx WebPACK 8.2.03i + Linux Problem
From: rponsard@gmail.com
Date: 27 Nov 2006 02:26:52 -0800
Links: << >>  << T >>  << A >>
the linux simulator use vsim from www.model.com (no included)
counter_tbw_isim_beh.exe is the simulation .exe for XP edition

On 26 nov, 11:28, Dave <d...@comteck.com> wrote:
> I downloaded the WebPACK and installed it on a SuSE 10.1 system (I know it
> isn't technically supported on this) in preparation for my receipt of a
> Spartan-3E Starter Kit.  Everything seemed to go well on the installation.
> However, when running the tutorial (a simple counter), the behavioral
> simulation returns the following:
>
>       Running Fuse ...
>       Parsing "counter_tbw_beh.prj": 0.01
>       Building counter_tbw_isim_beh.exe
>       ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
>
> I've looked at the Xilinx Answers Database #23037 and haven't been
> able to identify any obvious problem in the code.  This does not give me a
> good feeling for success with the Starter Kit.
>
> Has anyone else running Linux been able to complete this tutorial out of
> the box?  Anyone running Linux run into this problem?  I have tried it on
> a company laptop running XP with no problems, but that is not my desired
> longterm solution.  
> 
> Thanks,
>     ~Dave~


Article: 112653
Subject: tips for P&R in FPGA(quartus)
From: "ram" <vsrpkumar@rediffmail.com>
Date: 27 Nov 2006 02:48:47 -0800
Links: << >>  << T >>  << A >>
Can anyone give tips for Placement and ruoting tips for altera
quartusII.I think it will be helpful for many people in the
forum.Thanking you
kumar


Article: 112654
Subject: Re: MPMC2 DDR2 simulation
From: "Antti" <Antti.Lukats@xilant.com>
Date: 27 Nov 2006 02:51:51 -0800
Links: << >>  << T >>  << A >>
Antti schrieb:

> hi
>
> I think I am close to get it fully working, but some things are still
> messy
>
> MPMC2 has only verilog
> but EDK simulation works better in VHDL, so so far all attempts to get
> the all thing to work on init the onchip memories in simulator still
> fail
>
> when toplevel is VHDL memory init would work, but mpmc2 verilog
> doesnt load properly in simulator, or it loads after manual fix, but
> the it doesnt see the glbl.v :(
>
> when having the toplevel as verilog then the EDK system and MPMC2
> and DDR2 simulation models all load properly in simulator, but then
> I cant init the onchip memories any more.
>
> so what is the proper way to simulate such designs?
> 
> Antti

thanks all, problem solved (at least sims run)

Antti


Article: 112655
Subject: Re: tips for P&R in FPGA(quartus)
From: Frank Buss <fb@frank-buss.de>
Date: Mon, 27 Nov 2006 12:12:56 +0100
Links: << >>  << T >>  << A >>
ram wrote:

> Can anyone give tips for Placement and ruoting tips for altera
> quartusII.

What tips do you need? Usually it does it all automaticly.

> I think it will be helpful for many people in the
> forum.

This is a newsgroup, not a forum. See these articles for the difference:

http://en.wikipedia.org/wiki/Newsgroup
http://en.wikipedia.org/wiki/Internet_forum

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 112656
Subject: Pullups and pulldowns in EDK?
From: "kenm" <kenm@morro.co.uk>
Date: 27 Nov 2006 03:20:19 -0800
Links: << >>  << T >>  << A >>
Anyone know if there is any way to add pullups or pulldowns to IOBs in
EDK other than via the UCF?
My colleague is currently adding them using the UCF, but they then do
not appear my RTL simulation of the board with other FPGAs, and the
behaviour in simulation is not then correct.

Many Thanks for any help,

Ken Morrow


Article: 112657
Subject: Re: Pullups and pulldowns in EDK?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 27 Nov 2006 03:39:47 -0800
Links: << >>  << T >>  << A >>
kenm schrieb:

> Anyone know if there is any way to add pullups or pulldowns to IOBs in
> EDK other than via the UCF?
> My colleague is currently adding them using the UCF, but they then do
> not appear my RTL simulation of the board with other FPGAs, and the
> behaviour in simulation is not then correct.
>
> Many Thanks for any help,
>
> Ken Morrow

add wrapper around system.vhd and add PULLUP PULLDOWN prims there
dont think there is any other way

antti


Article: 112658
Subject: Re: vccaux and vccint
From: "rickman" <gnuarm@gmail.com>
Date: 27 Nov 2006 03:52:52 -0800
Links: << >>  << T >>  << A >>
Symon wrote:
> "Sean Durkin" <news_nov06@durkin.de> wrote in message
> news:456a8e5d$1@news.fhg.de...
> > PeteS wrote:
> >> On the S3, at least, VccAux powers the JTAG chain, part of the init
> >> setup and the DCMs. I don't believe it powers anything else.
> > It usually supplies input and output buffers for LVDS as well (at least
> > it does in Virtex2 Pro and Virtex 4), even if the bank those IOs are in
> > is supplied with i.e. 3.3V.
> >
> > cu,
> > Sean
> >
> ...except for the differential termination bit. That seems to be powered
> from VCCO. Pure genius.

I can't say I understand this.  Can you explain?


Article: 112659
Subject: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: florent.peyrard@gmail.com
Date: 27 Nov 2006 04:10:00 -0800
Links: << >>  << T >>  << A >>
Hi all,

 I'd like to use my SVF files to test the board; I'm trying to use
iMPACT, but it seems that under iMPACT, SVF can only be run to program
devices and not to test it. What to do?
The other possibility could be to use a test software to run my SVF
files but no one seems to be compliant with the Xilinx Platform Cable (
I don't have any parallel port on my PC, that's why I can't use the
Xilinx parallel cable III or IV).

I'm looking forward to your help, because I'm reaching an impasse.

 Thanks in advance, 
Florent


Article: 112660
Subject: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 27 Nov 2006 04:18:10 -0800
Links: << >>  << T >>  << A >>
florent.peyrard@gmail.com schrieb:

> Hi all,
>
>  I'd like to use my SVF files to test the board; I'm trying to use
> iMPACT, but it seems that under iMPACT, SVF can only be run to program
> devices and not to test it. What to do?
> The other possibility could be to use a test software to run my SVF
> files but no one seems to be compliant with the Xilinx Platform Cable (
> I don't have any parallel port on my PC, that's why I can't use the
> Xilinx parallel cable III or IV).
>
> I'm looking forward to your help, because I'm reaching an impasse.
>
>  Thanks in advance,
> Florent

just play back the test SVF files with impact whats wrong with that?

Antti


Article: 112661
Subject: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: florent.peyrard@gmail.com
Date: 27 Nov 2006 04:38:47 -0800
Links: << >>  << T >>  << A >>

Antti a =E9crit :
I must be silly.. how do you do that, please?

> florent.peyrard@gmail.com schrieb:
>
> > Hi all,
> >
> >  I'd like to use my SVF files to test the board; I'm trying to use
> > iMPACT, but it seems that under iMPACT, SVF can only be run to program
> > devices and not to test it. What to do?
> > The other possibility could be to use a test software to run my SVF
> > files but no one seems to be compliant with the Xilinx Platform Cable (
> > I don't have any parallel port on my PC, that's why I can't use the
> > Xilinx parallel cable III or IV).
> >
> > I'm looking forward to your help, because I'm reaching an impasse.
> >
> >  Thanks in advance,
> > Florent
>
> just play back the test SVF files with impact whats wrong with that?
>=20
> Antti


Article: 112662
Subject: Re: run a counter without a clock
From: Al <alessandro.basili@cern.ch>
Date: Mon, 27 Nov 2006 13:42:11 +0100
Links: << >>  << T >>  << A >>
Symon wrote:
> "Al" <alessandro.basili@cern.ch> wrote in message 
> news:ek9t4f$5n2$1@cernne03.cern.ch...
> 
>>The datasheet reports derating for Junction Temperature, which is strictly 
>>related to the power and is not ambient temperature at all.
> 
> Hi Al,
> So, I guess by the above statement you don't really mean that the junction 
> temperature is independent of the ambient temperature, do you?
> Cheers, Syms. 
> 
> 
No, I didn't mean that (don't know if it sounded like!). The junction 
temperature is so defined:

JT = c*P + Tamb

c = junction to ambient coefficient (related to the package)
P = power
Tamb = ambient temperature

But the P term is not so easy to evaluate.
Cheers

Al

-- 
Alessandro Basili
CERN, PH/UGC
Hardware Designer

Article: 112663
Subject: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: florent.peyrard@gmail.com
Date: 27 Nov 2006 04:42:40 -0800
Links: << >>  << T >>  << A >>
I mean: in my case "Operations>Execute XSVF/SVF"  remains grey. what do
I do wrong?



florent.peyr...@gmail.com a =E9crit :

> Antti a =E9crit :
> I must be silly.. how do you do that, please?
>
> > florent.peyrard@gmail.com schrieb:
> >
> > > Hi all,
> > >
> > >  I'd like to use my SVF files to test the board; I'm trying to use
> > > iMPACT, but it seems that under iMPACT, SVF can only be run to program
> > > devices and not to test it. What to do?
> > > The other possibility could be to use a test software to run my SVF
> > > files but no one seems to be compliant with the Xilinx Platform Cable=
 (
> > > I don't have any parallel port on my PC, that's why I can't use the
> > > Xilinx parallel cable III or IV).
> > >
> > > I'm looking forward to your help, because I'm reaching an impasse.
> > >
> > >  Thanks in advance,
> > > Florent
> >
> > just play back the test SVF files with impact whats wrong with that?
> >=20
> > Antti


Article: 112664
Subject: Re: vccaux and vccint
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 27 Nov 2006 13:14:30 -0000
Links: << >>  << T >>  << A >>
"rickman" <gnuarm@gmail.com> wrote in message 
news:1164628372.027773.61250@h54g2000cwb.googlegroups.com...
> Symon wrote:
>> "Sean Durkin" <news_nov06@durkin.de> wrote in message
>> news:456a8e5d$1@news.fhg.de...
>> > PeteS wrote:
>> >> On the S3, at least, VccAux powers the JTAG chain, part of the init
>> >> setup and the DCMs. I don't believe it powers anything else.
>> > It usually supplies input and output buffers for LVDS as well (at least
>> > it does in Virtex2 Pro and Virtex 4), even if the bank those IOs are in
>> > is supplied with i.e. 3.3V.
>> >
>> > cu,
>> > Sean
>> >
>> ...except for the differential termination bit. That seems to be powered
>> from VCCO. Pure genius.
>
> I can't say I understand this.  Can you explain?
>
Hi Rick,
You can use LVDS receivers in a Vcco = 3.3V bank. As Sean says, it appears 
they're powered from Vccaux. However, you can only use LVDS_DT receivers if 
Vcco = 2.5V. Check out the note on Figure 31, DS083. I've posted here a 
couple of times about this, I don't think I ever found out why it is so.
Cheers, Syms. 



Article: 112665
Subject: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 27 Nov 2006 05:29:25 -0800
Links: << >>  << T >>  << A >>
florent.peyrard@gmail.com schrieb:

> I mean: in my case "Operations>Execute XSVF/SVF"  remains grey. what do
> I do wrong?
>
1 double click "Boundary scan"
2 right click, select "xilinx device", select SVF file
3 right click on the svf file icon, select "execute.."

this will execute any valid SVF file.

ready, how easy must it be then?

Antti


Article: 112666
Subject: Altera's USB blaster
From: "hypermodest" <hypermodest@gmail.com>
Date: 27 Nov 2006 05:31:57 -0800
Links: << >>  << T >>  << A >>
Hi.
Just curious - what destination of the second 10-pin connector inside
of %subject% (JS2)? First one used as external JTAG connector..


Article: 112667
Subject: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: florent.peyrard@gmail.com
Date: 27 Nov 2006 05:37:51 -0800
Links: << >>  << T >>  << A >>
Thanks Antti,

i found what is my problem: of course I knew what you just wrote, but
the problem was that my SVF wasn't valid: I created it by myself
(following the pattern of the ones produces by iMPACT) but the right
way to follow seems to be:
1)create the file with iMPACT
2)then edit it and add one's instructions.

Anyway, I don't why, but if it works....

Florent

Antti a =E9crit :

> florent.peyrard@gmail.com schrieb:
>
> > I mean: in my case "Operations>Execute XSVF/SVF"  remains grey. what do
> > I do wrong?
> >
> 1 double click "Boundary scan"
> 2 right click, select "xilinx device", select SVF file
> 3 right click on the svf file icon, select "execute.."
>
> this will execute any valid SVF file.
>=20
> ready, how easy must it be then?
>=20
> Antti


Article: 112668
Subject: edk evaluation
From: "aravind" <aramosfet@gmail.com>
Date: 27 Nov 2006 05:44:38 -0800
Links: << >>  << T >>  << A >>
does xilinx provide an evaluation version of edk 8.1?


Article: 112669
Subject: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
From: florent.peyrard@gmail.com
Date: 27 Nov 2006 05:45:22 -0800
Links: << >>  << T >>  << A >>
what do you think is wrong in this SVF file?:

TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
STATE RESET;
STATE IDLE;
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
//header: prom en bypass

HIR 8 TDI (ff) SMASK (ff);
HDR 1 TDI (00) SMASK (01);



//trailer: aucun circuit avant le fpga dans la chaine

TIR 0;
TDR 0;
//On charge le fpga avec l'instruction sample
SIR 6 TDI (01) SMASK (3f);



//test: M0 =E0 0 ?

SDR 299 TDI(0) TD0(0)
MASK(0400000000000000000000000000000000000000000000000000000000000000000000=
000000);






florent.peyr...@gmail.com a =E9crit :

> Thanks Antti,
>
> i found what is my problem: of course I knew what you just wrote, but
> the problem was that my SVF wasn't valid: I created it by myself
> (following the pattern of the ones produces by iMPACT) but the right
> way to follow seems to be:
> 1)create the file with iMPACT
> 2)then edit it and add one's instructions.
>
> Anyway, I don't why, but if it works....
>
> Florent
>
> Antti a =E9crit :
>
> > florent.peyrard@gmail.com schrieb:
> >
> > > I mean: in my case "Operations>Execute XSVF/SVF"  remains grey. what =
do
> > > I do wrong?
> > >
> > 1 double click "Boundary scan"
> > 2 right click, select "xilinx device", select SVF file
> > 3 right click on the svf file icon, select "execute.."
> >
> > this will execute any valid SVF file.
> >=20
> > ready, how easy must it be then?
> >=20
> > Antti


Article: 112670
Subject: Re: vccaux and vccint
From: Sean Durkin <news_nov06@durkin.de>
Date: Mon, 27 Nov 2006 15:06:48 +0100
Links: << >>  << T >>  << A >>
Symon wrote:
> Hi Rick,
> You can use LVDS receivers in a Vcco = 3.3V bank. As Sean says, it appears 
> they're powered from Vccaux. However, you can only use LVDS_DT receivers if 
> Vcco = 2.5V.
Well, you CAN use them (i.e. the tools don't stop with an error or give
you w warning or anything), but the termination value won't be 100 Ohms.
Xilinx doesn't specify what the actual value might be, since they don't
recommend using the terminations that way.
I've used it successfully on 2 boards with VCCO=3.3V. "Successfully"
meaning that it works and the signal at the balls doesn't look that bad.

-- 
The FROM:-address in this posting is valid until the end of
the month only, after that every e-mail sent to this address
will bounce.

If you want to contact me after that, try figuring out what
the next valid address will be...

Article: 112671
Subject: Re: Altera's USB blaster
From: "Will Dean" <will@nospam.demon.co.uk>
Date: Mon, 27 Nov 2006 14:19:21 -0000
Links: << >>  << T >>  << A >>

"hypermodest" <hypermodest@gmail.com> wrote in message 
news:1164634317.796235.58550@j44g2000cwa.googlegroups.com...
> Hi.
> Just curious - what destination of the second 10-pin connector inside
> of %subject% (JS2)? First one used as external JTAG connector..
>

Is there an EPLD in there?  (ISTR there is) - if so it's probably for 
programming that.

Will




Article: 112672
Subject: Microblaze Code and XMP functions
From: icegray@gmail.com
Date: 27 Nov 2006 06:38:03 -0800
Links: << >>  << T >>  << A >>
I'm searching Microblaze example projects and codes. I think There are
only a few example on the Xilinx web page. Also I can't find a document
about drivers of microblaze. Dou you know any documents about drivers
like as gpio.h or gpio.c etc?


Article: 112673
Subject: Re: Microblaze Code and XMP functions
From: "Antti" <Antti.Lukats@xilant.com>
Date: 27 Nov 2006 06:40:58 -0800
Links: << >>  << T >>  << A >>
iceg...@gmail.com schrieb:

> I'm searching Microblaze example projects and codes. I think There are
> only a few example on the Xilinx web page. Also I can't find a document
> about drivers of microblaze. Dou you know any documents about drivers
> like as gpio.h or gpio.c etc?

those documents are on EDK CD, not on xilinx website.
some of them are website too, but not all

Antti


Article: 112674
Subject: Re: Was: board - T562.jpg, Now: Switched cap voltage regulator
From: Jim Thompson <To-Email-Use-The-Envelope-Icon@My-Web-Site.com>
Date: Mon, 27 Nov 2006 07:42:36 -0700
Links: << >>  << T >>  << A >>
On 26 Nov 2006 19:26:29 -0800, "rickman" <gnuarm@gmail.com> wrote:

>Jim Thompson wrote:
>>                                         ...Jim Thompson
>> --
>> |  James E.Thompson, P.E.                           |    mens     |
>> |  Analog Innovations, Inc.                         |     et      |
>> |  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
>> |  Phoenix, Arizona            Voice:(480)460-2350  |             |
>> |  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
>> |       http://www.analog-innovations.com           |    1962     |
>
>You seem to have some analog credentials.  Maybe you could divert some
>of this thread to answer a question about switched cap voltage
>converters.
>
>Where I am currently working we need to convert a wide battery voltage
>range to typical circuit voltages, such as 5, 3.3, etc. volts.  The
>battery voltage varies from 7 to 17 typically.  We can used inductive
>switchers for this, but it is in a radio and we prefer not to use
>these.  They are also not so efficient when running at low currents, at
>least the ones we can buy as chips.  By low I mean <100 mA.
>
>Remembering a chip I had almost used once, it had occured to me that a
>switched cap regulator could efficiently convert in a variety of exact
>ratios down to a voltage just above the required output and an LDO
>could properly regulate to the final voltage for an overall efficiency
>that could be a lot better than an inductive switcher.  I outlined some
>of the capacitor and switch topology to get the various ratios and
>determined the input voltage ranges and calculated efficiencies.  It
>looked pretty good on paper.  But then I tried to consider the power
>required to drive the various FETs to make the circuit operate and it
>looked like it would require a lot of current to drive the gates.
>
>Am I right in thinking that this is where the circuit looses
>efficiency?  I did my calcs based on the capacitance of the gate.  This
>seemed to be roughly constant over a lot of parts I looked at that
>could handle 100 ma to 1000 ma.  Could this be dealt with better in an
>ASIC with on chip FETs?
>
>The chip I had seen that did this was a part from TI that only worked
>with input voltages up to 5.5 or so.  I have not found anything that
>works with the higher voltages we need.  Any ideas?

I didn't know there was any such thing as an *efficient* switched-cap
regulator.  Their only convenience lies in small size.  They are
particularly nice when there is no load current... such as the bias
for an integrated electret microphone in a hearing aid chip I designed
last year ;-)

However, if you're switching large currents... thus low resistance
switches, driving the gate capacitance *will* be a major contributor
to your losses.

Are you certain you wouldn't be better off with an inductive switcher?

What are your actual I/O requirements.

                                        ...Jim Thompson
-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search