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HI I'm working on an microblaze project and i'm stuck at a problem with a dcm. i generated a new project with the wizard and the i added an additional dcm. i also have an instance of an SPI module in my design. i want to connect the clock_fx output of the dcm with the clock input of the spi module. you can see my project : system.mhs http://193.170.52.132/xilinx/system.mhs system.ucf http://193.170.52.132/xilinx/system.ucf here i connected the opb spi clock input: PORT OPB_Clk = dcm_spi_CLKFX the dcm is set to generate 24MHz output when i try to syntesize i get the timing error for the dcm_spi_CLKFX: http://193.170.52.132/xilinx/xflow.log (scroll almost all the way down) when i connect the OPB_Clk to the normal clock line that feed the dcm and the rest of the curcuit it works fine. could anybody help me or give me a hint here? thanksArticle: 112976
u_stadler@yahoo.de wrote: > I'm working on an microblaze project and i'm stuck at a problem with a > dcm. > i generated a new project with the wizard and the i added an additional > dcm. > i also have an instance of an SPI module in my design. i want to > connect the clock_fx output of the dcm with the clock input of the spi > module. > > you can see my project : > system.mhs http://193.170.52.132/xilinx/system.mhs > system.ucf http://193.170.52.132/xilinx/system.ucf > > here i connected the opb spi clock input: > PORT OPB_Clk = dcm_spi_CLKFX > > the dcm is set to generate 24MHz output > > when i try to syntesize i get the timing error for the dcm_spi_CLKFX: > http://193.170.52.132/xilinx/xflow.log (scroll almost all the way down) > > when i connect the OPB_Clk to the normal clock line that feed the dcm > and the rest of the curcuit it works fine. > > could anybody help me or give me a hint here? > thanks I've never used opb_spi, but I believe the problem is that OPB_Clk for the entire bus must be that same. If you want to run spi at a slower speed you must use the C_OPB_SCK_RATIO parameter to divide the clock. Alan NishiokaArticle: 112977
<u_stadler@yahoo.de> wrote in message news:1165184558.266609.159070@n67g2000cwd.googlegroups.com... > HI > > I'm working on an microblaze project and i'm stuck at a problem with a > dcm. > i generated a new project with the wizard and the i added an additional > dcm. > i also have an instance of an SPI module in my design. i want to > connect the clock_fx output of the dcm with the clock input of the spi > module. > > you can see my project : > system.mhs http://193.170.52.132/xilinx/system.mhs > system.ucf http://193.170.52.132/xilinx/system.ucf > > here i connected the opb spi clock input: > PORT OPB_Clk = dcm_spi_CLKFX > > the dcm is set to generate 24MHz output > > when i try to syntesize i get the timing error for the dcm_spi_CLKFX: > http://193.170.52.132/xilinx/xflow.log (scroll almost all the way down) > > when i connect the OPB_Clk to the normal clock line that feed the dcm > and the rest of the curcuit it works fine. > > could anybody help me or give me a hint here? > thanks > I think I had the same problem when I added a second DCM to a project. The timing report quoted very large periods of negative slack. This is because the tools analyse paths between different clock domains. Look at the source and destination clocks in the verbose timing report. I had taken the necessary precautions where signals passed between domains, and I did not want the tools to try and analyse them, so I added TIG (timing ignore group) constraints to my ucf file: NET clk_foo TNM_NET = clk_grp1; NET clk_bar TNM_NET = clk_grp2; NET clk_xyz TNM_NET = clk_grp3; TIMESPEC TS_tig1 = FROM clk_grp1 TO clk_grp3 TIG; TIMESPEC TS_tig2 = FROM clk_grp2 TO clk_grp3 TIG; TIMESPEC TS_tig3 = FROM clk_grp3 TO clk_grp1 TIG; TIMESPEC TS_tig4 = FROM clk_grp3 TO clk_grp2 TIG; There were 3 clock domains in my project. I did not need TIGs between grp1 and grp2 because there were no direct signal paths.Article: 112978
I've finally managed to solve the problem by opening the pipe
in the foreign subprogram, and by setting the mode to blocking
with the fcntl function.
[...]
rdpipe=open("./rdpipe",O_WRONLY);
flags = fcntl( wrpipe, F_GETFL );
flags &= ~O_NONBLOCK;
fcntl( wrpipe, F_SETFL, flags );
[...]
However it required to use the FLI interface, which impaired portability
of the design.
--
BR, Wojtek
Article: 112979Hi Could you please tell me how did you program the FPGA from the FX2 processor ? I need the flow(ie binary i need to generate for the FPGA), and the FX2 processor code if possible. rgds bijoyArticle: 112980
Hi Interesting topic,,i would like to know the details about the delivery of the project after the project is started. Thanks and Regards BODDU LokeshArticle: 112981
Quesito wrote: > Hi all, > for the picoblaze funs... > you can download the latest version of picoblaze C compiler on my > website > www.poderico.co.uk > the latest version is 1.8.4 > In this version you have the optimizer (just started) > I've got an example how to use the LCD IF on the Spartan3E starter > kit... if you want to have a try.. please send me an email for any > suggestions... or improvement... Suggestions : Release a linux version ;) Improvement : It's possible to change the microblaze source to add an offseting capability to fetch/store So image sF is your stack pointer, you can save regs on the stack: sub sF, 4 store s0, 0(sF) store s1, 1(sF) store s2, 2(sF) store s3, 3(sF) That should allow for some codesize reduction I think. Also, theses modification to the microblaze don't require more resources. (just some LUT3 changed in LUT4). SylvainArticle: 112982
On 2006-12-04, bijoy <pbijoy@rediffmail.com> wrote: > Hi Could you please tell me how did you program the FPGA from the FX2 processor ? > > I need the flow(ie binary i need to generate for the FPGA), and the FX2 processor code if possible. Hi. Take a look at http://inisyn.org/src/xup/ if you want to configure a Xilinx FPGA from the FX2 processor. /AndreasArticle: 112983
"dh2006" <davidhughes330@hotmail.com> wrote in message
news:1164472037.666314.196580@f16g2000cwb.googlegroups.com...
> I've read much about Double Buffering, especially that it is good
> practice (on Xilinx devices) to double buffer data signals (such as ADC
> inputs), and place the double buffer in the IOB associated with the
> pin.
> Can someone explain to me, what double buffering is and why you would
> use it? Any links to reference information would be appreciated.
"Double buffering" is a very vague term and means different things in
different contexts. Here are a few things it might mean in FPGA terms:
* Double-registering - as a previous poster pointed out, it is very common
to use two ranks of synchronizing flip-flops when moving from one clock
domain to another. This is a favourite topic in these parts so you'll have
no difficulty in finding an abundance of information about that. :-)
* Double data rate - many FPGAs nowadays have a special configuration
flip-flops to cater for DDR SDRAM and the like. These allow data to be clock
in and out to the external device on both edges of the reference clock,
while still permitting a single-clock design inside the FPGA itself. Refer
to your device datasheet to find out how these can be used.
* Double-buffering - say this to a designer of DSP or graphics processing
hardware and they will immediately think of a pair of RAM blocks being used
as a buffer between two processing elements in a so-called "ping pong"
configuration. This is a method for increasing the throughput of a system,
by allowing the data source to write a block of data to memory 'A' while the
data processing unit is reading the previous block from memory 'B'. When
both operations are done, A and B are swapped and the processing continues.
Judging from your use of the phrase "good practice", I think you are
probably refering to double-registering for synchronization. In which case,
do listen to the many experts who inhabit this group and you will likely
save yourself much pain and suffering!
Cheers,
-Ben-
Article: 112984hi thanks for the answers. well i changed my ucf file now to this : ## System level constraints Net sys_rst_pin TIG; Net sys_clk_pin TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 19000 ps; NET dcm_spi_CLKFX TNM_NET = clk_grp_spi; TIMESPEC TS_tig1 = FROM sys_clk_pin TO clk_grp_spi TIG; TIMESPEC TS_tig2 = FROM clk_grp_spi TO sys_clk_pin TIG; #TIMESPEC TS_spi_clk_pin = PERIOD clk_grp_spi 25000 ps; #NET dcm_spi_CLKFX TIG; but when i try to run xflo i get the following error message: Checking timing specifications ... WARNING:XdmHelpers:793 - The TNM "sys_clk_pin" drives the CLKIN pin of DCM "dcm_0/dcm_0/DCM_INST". This TNM cannot be traced through the DCM because it is not used exclusively by one PERIOD specification. This TNM is used in the following user groups and/or specifications: TS_tig1=FROM sys_clk_pin TO clk_grp_spi TIG TS_tig2=FROM clk_grp_spi TO sys_clk_pin TIG WARNING:XdmHelpers:625 - No instances driven from the following signals or pins are valid for inclusion in TNM group "sys_clk_pin". A TNM property on a pin or signal marks only the flip-flops, latches and/or RAMs which are directly or indirectly driven by that pin or signal. signal "sys_clk_pin" WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM group "sys_clk_pin". This group has been removed from the design. ERROR:XdmHelpers:648 - The specification "TS_tig1" is invalid because its FROM group (sys_clk_pin) was removed. ERROR:XdmHelpers:648 - The specification "TS_tig2" is invalid because its TO group (sys_clk_pin) was removed. what am i doing wrong? why is "sys_clk_pin" removed? thanksArticle: 112985
u_stadler@yahoo.de schrieb: > hi > > thanks for the answers. > > well i changed my ucf file now to this : > > ## System level constraints > Net sys_rst_pin TIG; > > Net sys_clk_pin TNM_NET = sys_clk_pin; > #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 19000 ps; > > NET dcm_spi_CLKFX TNM_NET = clk_grp_spi; what are you doing?? The OPB_SPI has __no__ SPI master clock input port !! the OPB_Clk must have default connection to system clock and the SPI clock is generated from it, but you can not feed the OPB_Clock of the OPB_SPI with some other clock. its of course stupid that the OPB_SPI can only have SPI clock as 2n divided OPB clock but so it is AnttiArticle: 112986
oh... thanks a lot for pointing that out Antti! so this means i can't have an spi output clock of 12 MHz? (because my obp clock is 50) is there any other way to do it?? i have seen that in edk 8.2 the only possible clock div for the spi is 16. this means i can only get a max of 3.125 MHz for the spi clock? are there workarounds for that? thanks urbanArticle: 112987
u_stadler@yahoo.de schrieb: > oh... > thanks a lot for pointing that out Antti! > > so this means i can't have an spi output clock of 12 MHz? (because my > obp clock is 50) the min divide is less than 16, but i think there is some mess with documentation and/or parameter validation divison factor below 16 is possible for sure, but you cant have arbitraty SPI clock, that also sure AnttiArticle: 112988
"fpgabuilder" <fpgabuilder-groups@yahoo.com> wrote in message news:1165172277.246220.21570@73g2000cwn.googlegroups.com... > The project sounds interesting but why send raw video? Isn't it easier > if it is compressed and then sent over a low bandwidth wifi network? > > > lubot77 wrote: >> I do have a interesting project. I am planing to wire my house with >> duplex >> multimode fiber. I would like to send from a central location of the >> house >> multiple broadcast video and audio signals. The video should be either 10 >> or >> 12bit digital stream. >> With the help of a FPGA we should multiplex I would say up to 5 digital >> parallel video streams(each around 200Mbs, with 16M clk and 3Mbs for four >> audio channels). The mux out should be 16 or 20bit data stream. > Indeed, MPEG-4 HDTV is 20 Mbps tops. www.videolan.org & Cat-5e would very easy and cheap. HTH, Syms.Article: 112989
"John_H" <newsgroup@johnhandwork.com> wrote in message news:Tvqch.341$R_1.62@trndny08... > When I was trying to lock down only 2 pins out of 4, I had no problems for > a while, then I couldn't get them to work; it might have been a software > change. For this delay-matching circuit (to a first order approximation) > I had to use the LOCK_PINS:ALL constraint to map I0-I3 to A1-A4... all 4 > pins even though only 2 were critical. > > There are very few applications that benefit from locking down the pins, > but they do exist. > > Yep, and normally you also need to lock your routing for these rare apps. Why not enter the twilight zone of 'directed routing'? :-) http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0043_7.html HTH, Syms.Article: 112990
oh thats interesting. below 16 would work. what do you mean with an arbitraty SPI clock? generate a clock frequency with a dcm and connect the dcm output to an external fpga pin and use that as the spi clock? thanksArticle: 112991
u_stadler@yahoo.de schrieb: > oh thats interesting. below 16 would work. > what do you mean with an arbitraty SPI clock? > generate a clock frequency with a dcm and connect the dcm output to an > external fpga pin and use that as the spi clock? > > thanks I did mean that arbitrary clock is NOT possible with the OPB_SPI core eg you would need to either modify it or develop your own core AnttiArticle: 112992
I have a Virtex-II oro Partial Reconfiguration design which contains several modules such as PPC,PLB.OPB,DCM,DDR and so on. The EDK tool automaticly generate the modules and then I add two accelerators which attach to the OPB through the IPIF.I generate the bitstream in the EDK,and it create the .ngc files,then I modify the top.vhd file and add the busmacros between the OPB bus and the accelerators.After that I systhesis the top.vhd file separately. And then I begin to implement the modular design.there is an error in the active implementation phase of the DCM module when I map the top.ngd file(map top.ngd): ERROR:LIT:144 - Only STATUS0, STATUS1 and STATUS2 can be used in DCM symbol "dcm_0/dcm_0/DCM_INST" (output signal=dcm_0/dcm_0/CLK0_BUF). how can I solve this problem?Article: 112993
sorry. should read more carefully. thanks Antti schrieb: > u_stadler@yahoo.de schrieb: > > > oh thats interesting. below 16 would work. > > what do you mean with an arbitraty SPI clock? > > generate a clock frequency with a dcm and connect the dcm output to an > > external fpga pin and use that as the spi clock? > > > > thanks > I did mean that arbitrary clock is NOT possible with the OPB_SPI core > > eg you would need to either modify it or develop your own core > > AnttiArticle: 112994
Many thanks! I now have the Platform USB cable working with a 2.6.17 kernel (32-bit) using this firmware and the latest version of WinDriver (811). I will get back to Xilinx support and see if they will change the link to point to this archive! Rob On Dec 2, 8:42 pm, mark.jar...@gmail.com wrote: > Sorry, that should have beenftp://ftp.xilinx.com/pub/utilities/fpga/install_drivers.tar.gz > > Incidentally, that tarball also has 32- & 64-bit cable drivers.Article: 112995
JSalk wrote: > Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally > Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 > lane PCIe digitiser card with the National 500MSPS ADC and the ECP2M > FPGA. The ADC output 32 pair LVDS and I have read the FPGA datasheet > but there is no mention of DCI?? > > Thanks > slkjas I'm pretty sure that the general purpose I/O pins do not have DCI, but the SERDES receivers have selectable 50 Ohm or 2K ohm differential termination. Look for ZRX-TERM in the data sheet.Article: 112996
Has anyone heard of digital design technique, method or theory called "coherent logic" design?Article: 112997
Sadly, my USB cable still doesn't work. iMPACT keeps trying to
reprogram the CPLD when it notices that "CPLD version = FFFFh". If
anyone has suggestions, I'm all ears. Frankly, I think the cable's
hooped.
> I now have the Platform USB cable working with a 2.6.17 kernel (32-bit)
> using this firmware and the latest version of WinDriver (811).
I thought the WinDriver in the Xilinx tarball was 802. Did you grab
the latest from Jungo (for anyone who's reading --
http://www.jungo.com/download/WD811LN.tgz or
http://www.jungo.com/download/WD811LNX86_64.tgz)? I found that I had
to patch the configure script included in the Xilinx tarball to get 802
to build with 2.6.17 (on Xubuntu Edgy).
--- configure.dist 2006-12-02 17:29:08.000000000 -0500
+++ configure 2006-12-04 09:52:44.000000000 -0500
@@ -886,6 +886,9 @@ if test ${VER:0:3} = "2.6" ; then
else
CFLAGS="$CFLAGS -DKBUILD_MODNAME=$MODULE_NAME"
fi
+ if test $VER_SUBMINOR -ge 17 ; then
+ CFLAGS="$CFLAGS -include $KERNEL_DIR/include/linux/autoconf.h"
+ fi
fi
SHARED_OBJECT=libwdapi$dist_version
Article: 112998Hi, A part of my project needs the FPGA spartan3 ( XC3S100) to be interfaced with the USB via FIFO. I made the FIFO using logic core's FIFO generator v 2.3. I am intending to make a asynchronous FIFO. The FIFO has full, almost full, read , write signals. Would XEM3010 be the right choice for it? Please advice! Regards JohnArticle: 112999
wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. ... I used a Verilog Micron model to develop my DDR/DDR2 controller and was very happy with the model. I had to set a couple of `defparams to make the model match my hardware, and it was very helpful in reporting all timing errors, such as violations in write recovery time, etc. There is a "Debug" parameter you can switch on to report all data transactions as well. Before you write your own controller, though, I warn you that it is much more difficult than you anticipate. -Kevin
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z