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Messages from 113000

Article: 113000
Subject: Re: Picoblaze C compiler 1.8.4
From: nico@puntnl.niks (Nico Coesel)
Date: Mon, 04 Dec 2006 18:40:57 GMT
Links: << >>  << T >>  << A >>
"Quesito" <francesco_poderico@yahoo.com> wrote:

>Hi all,
>for the picoblaze funs...
>you can download the latest version of picoblaze C compiler  on my
>website
>www.poderico.co.uk
>the latest version is 1.8.4
>In this version you have the optimizer (just started)
>I've got an example how to use the LCD IF on the Spartan3E starter
>kit... if you want to have a try.. please send me an email for any
>suggestions... or improvement...

The examples seem a bit like a macro based C compiler. The code for
reading/writing I/O is huge. Maybe it is better to introduce some
language extensions that will map variables into the I/O space. Most
8051 C compilers do this.


-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 113001
Subject: Can you configure an Altera Stratix without the nStatus line?
From: "radarman" <jshamlet@gmail.com>
Date: 4 Dec 2006 12:02:52 -0800
Links: << >>  << T >>  << A >>
Hello all,
I recently bought one of the Parallax Stratix "SmartPack" boards on
eBay. It was a good deal, and the FPGA works fine, but I've run into a
bit of trouble with the PX loader program.

I'm not clear whether it is a problem with the loader itself, the
serial port. I don't suspect the PIC microcontroller, as the initial
default configuration loads. The trouble is, I don't understand the
failure, or the protocol. I know from the docs that the binary data is
RLE compressed, but I don't understand the handshaking stuff. I'm
working on finding a workable configuration, but so far it hasn't gone
too well.

In the event that I can't get the PX stuff working, I thought about
just depopulating the PIC, and dead-bugging an appropriate
configuration memory to the board. The problem is that the nStatus line
may not be available. I do have access to nCONFIG, DEV_CLRn, CONF_DONE,
DCLK, and DATA0.

I'm curious to know what would happen if one wired in, say, an EPCx
device, and left the nCS line tied active. In theory, if you don't
reuse the bit in the design, shouldn't it be harmless? Will this
confuse the EPCx?

Thanks!


Article: 113002
Subject: Re: Opencores DDR SDRAM controller
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 4 Dec 2006 12:03:28 -0800
Links: << >>  << T >>  << A >>
cippalippa wrote:
> thanks for the answer.
> However I already see the Xilinx reference design but I have a bad
> experience with this kind of design.
> I don't need particular performace; 100 MHz speed and burst 2 for me is
> enaught.
> I see that opencores IP seems simple and Xilinx IP with MIG seems
> complicate; I ask to Xilinx Field Application engineer if this IP
> generated from Xilinx MIG works and they ask me: "I don't know"; so if
> I'm not sure that this controller work I prefer to use Opencore IP.
> Sameone have already use the Opencore DDR sdram controller? If so how I
> must modify the design for the sintesis?

Maybe I misunderstood, but it already does synthesize. David Ashley, as
posted here earlier, did the needed modification to get it running on
the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on
Digilent's Spartan 3E1600 board.

That said, the Opencore DDR controller is not perfect, but it's a good
starting point for verifying that the basic .ucf constaints are set up
(mostly) correctly.

Tommy


Article: 113003
Subject: Re: Can you configure an Altera Stratix without the nStatus line?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 4 Dec 2006 12:11:08 -0800
Links: << >>  << T >>  << A >>
radarman schrieb:

> Hello all,
> I recently bought one of the Parallax Stratix "SmartPack" boards on
> eBay. It was a good deal, and the FPGA works fine, but I've run into a
> bit of trouble with the PX loader program.

http://forums.parallax.com/forums/default.aspx?f=15&m=103540

?help?

Antti


Article: 113004
Subject: Xilinx EDK/XPS 8.2 freezes XP desktop when launching XMD
From: "mpthompson@gmail.com" <mpthompson@gmail.com>
Date: 4 Dec 2006 13:01:53 -0800
Links: << >>  << T >>  << A >>
Hi everyone,

When I launch an external application such as XMD, the Software
Debugger or Platform Studio SDK from the Xilinx Platform Studio 8.2 my
Window XP desktop will freeze for an indefinite amount of time.  The
mouse can be moved, but all mouse clicks and keyboard input seems to be
dead.  The only way for me to recover control of my PC is to hit
Ctrl-Alt-Delete which seems to wake the PC up from whatever state it's
in and I can then continue to use the application that was launched.

When I first installed EDK 8.2 a few months ago it worked fine, but
this problem seemed to come from out of the blue a few weeks ago.
Applying the latest EDK updates to bring things up 8.2.02i did not seem
to fix anything.  Also, no other applications on my PC suffer from the
same problems so I'm fairly certain it's a problem with the Xilinx
applications themselves.

Has anyone seen such an issue?  Any clues on where I can look to see
what might be misconfigured on my system?

Thanks,

Mike Thompson


Article: 113005
Subject: Re: Can you configure an Altera Stratix without the nStatus line?
From: "radarman" <jshamlet@gmail.com>
Date: 4 Dec 2006 13:28:56 -0800
Links: << >>  << T >>  << A >>

Antti wrote:
> radarman schrieb:
>
> > Hello all,
> > I recently bought one of the Parallax Stratix "SmartPack" boards on
> > eBay. It was a good deal, and the FPGA works fine, but I've run into a
> > bit of trouble with the PX loader program.
>
> http://forums.parallax.com/forums/default.aspx?f=15&m=103540
>
> ?help?
>
> Antti

That's a good link, but not applicable. I can download designs over the
JTAG port, and they work just fine, which implies that the problem
isn't in the configuration bitstream. Note, I used the supplied sample
.qsf file as a reference, so I see the "ES" part in the device
selection page.

The problem is that when I use one of the onboard com ports, the PX
loader  "hangs" midway through the transfer, requiring me to kill the
process. It seems to always occur at 76 bytes, which is curious.

I've also tried it with a USB serial adapter, and the transfer does
seem to complete; but the same design that worked just fine when loaded
via JTAG fails when loaded via PX. I've been nervous about supplying
the /P parameter, to program the onboard EEPROM.

I'm still trying various things, but right now I don't suspect an error
in generating the programming file. It also occurred to me that this
could be why the board was returned in the first place...


Article: 113006
Subject: Re: LUT input order
From: Mr.B <bharadwaj.sr@gmail.com>
Date: Mon, 4 Dec 2006 15:32:31 -0800
Links: << >>  << T >>  << A >>
thank u folks....

John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this....

thank u

Mr.B

Article: 113007
Subject: Re: LUT input order
From: "Peter Alfke" <peter@xilinx.com>
Date: 4 Dec 2006 16:26:01 -0800
Links: << >>  << T >>  << A >>
Mr B., could you please tell us why the LUT-address bit-order is
important for you.
Everybody knows that it is irrelevant in most cases. Yours must be
special...
Peter Alfke, Xilinx

Mr.B wrote:
> thank u folks....
>
> John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this....
> 
> thank u
> 
> Mr.B


Article: 113008
Subject: Re: LUT input order
From: bharadwaj.sr@gmail.com
Date: 4 Dec 2006 16:31:17 -0800
Links: << >>  << T >>  << A >>
Hi Pete

I am tryin to permute the input order for that I need to fix the inputs
in a certain fashion.

Mr.B

Peter Alfke wrote:
> Mr B., could you please tell us why the LUT-address bit-order is
> important for you.
> Everybody knows that it is irrelevant in most cases. Yours must be
> special...
> Peter Alfke, Xilinx
>
> Mr.B wrote:
> > thank u folks....
> >
> > John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this....
> > 
> > thank u
> > 
> > Mr.B


Article: 113009
Subject: Re: Opencores DDR SDRAM controller
From: Frank Buss <fb@frank-buss.de>
Date: Tue, 5 Dec 2006 01:34:53 +0100
Links: << >>  << T >>  << A >>
Tommy Thorn wrote:

> Maybe I misunderstood, but it already does synthesize. David Ashley, as
> posted here earlier, did the needed modification to get it running on
> the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on
> Digilent's Spartan 3E1600 board.

Do you have a link to a working project or the ucf file? I would like to
use the DDR SDRAM, too, but I can't find the posting.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 113010
Subject: Re: LUT input order
From: "Peter Alfke" <peter@xilinx.com>
Date: 4 Dec 2006 16:38:56 -0800
Links: << >>  << T >>  << A >>
I suppose you know already that you can achieve the same result by
changing the content of the LUT, either by reconfiguration or even
dynamically by shifting in the new pattern serially.(SRL16)
Peter Alfke, Xilinx

On Dec 4, 4:31 pm, bharadwaj...@gmail.com wrote:
> Hi Pete
>
> I am tryin to permute the input order for that I need to fix the inputs
> in a certain fashion.
>
> Mr.B
>
> Peter Alfke wrote:
> > Mr B., could you please tell us why the LUT-address bit-order is
> > important for you.
> > Everybody knows that it is irrelevant in most cases. Yours must be
> > special...
> > Peter Alfke, Xilinx
>
> > Mr.B wrote:
> > > thank u folks....
>
> > > John, which version of xilinx wer u working on? I am currently working on 8.1 and was trying to use the lock pins constraint, INST "lut_name" LOCK_PINS = "I0:A1, I1:A2, I2:A3, I3:A4"; it pops up with a syntax error in da UCF file. I dont know wer I am goin wrong. could u suggest me smthin on this....
> 
> > > thank u
> 
> > > Mr.B


Article: 113011
Subject: Re: XEM3010
From: "Andrew FPGA" <andrew.newsgroup@gmail.com>
Date: 4 Dec 2006 16:57:07 -0800
Links: << >>  << T >>  << A >>

john wrote:
> Hi,
>
> A part of my project needs the FPGA spartan3 ( XC3S100) to be
> interfaced with the USB via FIFO. I made the FIFO using logic core's
> FIFO generator v 2.3. I am intending to make a asynchronous FIFO. The
> FIFO has full, almost full, read , write signals. Would XEM3010 be the
> right choice for it? Please advice!

What is XEM3010?
Why do you need a FIFO, and why does it need to be asynchronous?


Article: 113012
Subject: Re: Opencores DDR SDRAM controller
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 4 Dec 2006 17:13:44 -0800
Links: << >>  << T >>  << A >>
Frank Buss wrote:
> Tommy Thorn wrote:
>
> > Maybe I misunderstood, but it already does synthesize. David Ashley, as
> > posted here earlier, did the needed modification to get it running on
> > the Spartan 3E Start Kit. With just a .ucf adjustment, it worked on
> > Digilent's Spartan 3E1600 board.
>
> Do you have a link to a working project or the ucf file? I would like to
> use the DDR SDRAM, too, but I can't find the posting.

Sorry, it was a bit tricky to find. The original thread:
http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/a58600c317356edb/27f9d22a4590952b?rnum=11&q=david+ashley+ddr&_done=%2Fgroup%2Fcomp.arch.fpga%2Fbrowse_frm%2Fthread%2Fa58600c317356edb%2F979d5e1695dc1710%3Flnk%3Dst%26q%3Ddavid+ashley+ddr%26rnum%3D2%26#doc_27f9d22a4590952b

For your convienience, the source (quoting David: "It's a pretty much
identical copy of the open cores ddr controller, except I removed one
DCM, and I wrapped it all in a synthesizable tester targeted to the
spartan-3e starter board."): http://www.xdr.com/dash/fpga/

My humble contribution: a complete constraints file for the Digilent
Spartan 3E-1600 Development Board (aka. Spartan 3E starter kit in the
XC3S1600E edition): http://not.meko.dk/spe1600e-1.1.ucf

Please share any improvements or suggestions.

Tommy


Article: 113013
Subject: Spartan3 IBIS / Simulation questions
From: "ee_ether" <xjjzdv402@sneakemail.com>
Date: 5 Dec 2006 00:13:57 -0800
Links: << >>  << T >>  << A >>
Hi,

I have a design with a Spartan3E driving some PCI logic.  I'm trying to
simulate part of the design using HyperLynx 7.5 and the Spartan3e IBIS
model from Xilinx.

1.  When I set the I/O standard for the pin(s) in question, the
steady-state output high voltage is 3V, not 3.3V .  I know Xilinx only
claims PCI 3.3V compatability if the I/Os are run at 3V -- is this
output voltage hard coded in the IBIS model?

I think all the power supplies in HyperLynx are correctly set,
including the 3.3V supply.

2.  In HyperLynx, when I change the I/O standard for the pin (i.e.
LVCMOS, SSTL, etc) the "pin number" for the selected pin seems to
change.  Is this "pin number" just refering to an I/O standard the IBIS
file supports?

3.  Xilinx XAP653 has some guidelines for PCI and clamp diode /
resistor calculations.  Page 2 seems to be a bit circular when it comes
to computing the resistance to limit the current, and more specifically
the foward voltage for the didoe .  Where does the knowledge of using
1V for the diode's Vf come from?  It seems the assumption is made that
Vf is 1V, current is calculated, and then the Vf is re-referenced based
on the foward current and it is "confirmed" Vf is 1V...

Your help is welcome.

/\/\/\/\/\/\/\/\/\/\/\/\/\_____
Into the EE Ether we go!


Article: 113014
Subject: Re: Hi
From: "ram" <vsrpkumar@rediffmail.com>
Date: 5 Dec 2006 00:48:33 -0800
Links: << >>  << T >>  << A >>

Hi
I have to simulate a gate level netlist file with test bench and dummy
host model in modelsim SE in quartus s/w.Can you give hint.
sorry for the disturbance
kumar

Subroto Datta wrote:

> The details can be found in the Quartus Handbook at
> http://www.altera.com/literature/hb/qts/qts_qii53001.pdf
>
> Hope this helps,
> Subroto Datta
> Altera Corp.
>
> "ram" <vsrpkumar@rediffmail.com> wrote in message
> news:1165028275.314021.115460@j44g2000cwa.googlegroups.com...
> > Hi
> > I am using modelsim for simulation and quartus 6.0 for remaining.I have
> > generated custom netlist ffrom quartus.I want to simulate in modelsim
> > .How to link library of cyclone device.How to do that.Can anybody help
> > me.Thanking you
> >


Article: 113015
Subject: Re: Picoblaze C compiler 1.8.4
From: "Quesito" <francesco_poderico@yahoo.com>
Date: 5 Dec 2006 01:31:42 -0800
Links: << >>  << T >>  << A >>
Good Idea,
OK I will do!

Nico Coesel wrote:
> "Quesito" <francesco_poderico@yahoo.com> wrote:
>
> >Hi all,
> >for the picoblaze funs...
> >you can download the latest version of picoblaze C compiler  on my
> >website
> >www.poderico.co.uk
> >the latest version is 1.8.4
> >In this version you have the optimizer (just started)
> >I've got an example how to use the LCD IF on the Spartan3E starter
> >kit... if you want to have a try.. please send me an email for any
> >suggestions... or improvement...
>
> The examples seem a bit like a macro based C compiler. The code for
> reading/writing I/O is huge. Maybe it is better to introduce some
> language extensions that will map variables into the I/O space. Most
> 8051 C compilers do this.
>
>
> --
> Reply to nico@nctdevpuntnl (punt=.)
> Bedrijven en winkels vindt U op www.adresboekje.nl


Article: 113016
Subject: Readback Jtag Problem
From: "phoenix" <happy_pippo81@yahoo.it>
Date: 5 Dec 2006 02:13:37 -0800
Links: << >>  << T >>  << A >>
When I make the readback on the Spartan II concerning a configuration's
bitstream which changes the state of some flip flop, the returned
bitstream is not the current one but starting bitstream whitout changes.


Article: 113017
Subject: Using quartus "In system memory editor" from command line
From: Steven Derrien <sderrienREMOVE@irisa.fr>
Date: Tue, 05 Dec 2006 11:35:52 +0100
Links: << >>  << T >>  << A >>
Hi folks,

Does anyone know wether it is possible to use the quartus "In system 
memory editor" feature from command line ?

I have been searching Altera documentation with little success...

Thanks in advance,

Steven

Article: 113018
Subject: Re: XEM3010
From: "Guru" <ales.gorkic@email.si>
Date: 5 Dec 2006 03:00:38 -0800
Links: << >>  << T >>  << A >>
OpalKelly XEMs are a very simple interface to USB2.0. The FrontPanel
software and cores include pipeline transfer triggered by PC for
connection to spartan3 FIFOs.
If you don't need aditional SDRAM or nonvolatile PROM to store FPGA
program, then XEM3001 is enough.

Cheers,

Ales


john wrote:
> Hi,
>
> A part of my project needs the FPGA spartan3 ( XC3S100) to be
> interfaced with the USB via FIFO. I made the FIFO using logic core's
> FIFO generator v 2.3. I am intending to make a asynchronous FIFO. The
> FIFO has full, almost full, read , write signals. Would XEM3010 be the
> right choice for it? Please advice!
> 
> Regards
> John


Article: 113019
Subject: Spartan-3A launched
From: "Antti" <Antti.Lukats@xilant.com>
Date: 5 Dec 2006 03:12:55 -0800
Links: << >>  << T >>  << A >>
as Xilinx PR ES samples are available, and tools support for S3A also,
well this is not so true because data2mem does not support S3A, those
Microblaze designs with EDK flow will fail on NGBUILD, the same applies
to Virtex-5 all devices except 50(T) - so as of today the latest
ISE/EDK supports

Virtex-5 ---> LX50(T) only ! DATA2MEM fails for all other devices
Spartan3A ---> no devices, DATA2MEM is not supporting S3a

of course designs that dont use softcore processors can be implemented
with current tools as well, also for S3A and V5 other than LX50(T).

I wonder why there is no date on ISE 8.2 SP4 release? WebCase allows
SP4 to be selected already.

Antti


Article: 113020
Subject: Re: Spartan-3A launched
From: "Antti" <Antti.Lukats@xilant.com>
Date: 5 Dec 2006 03:36:35 -0800
Links: << >>  << T >>  << A >>
Antti schrieb:

> as Xilinx PR ES samples are available, and tools support for S3A also,

as usual - the documentation is not complete :(

the DNA featured (unique ID) is only mentioned and not described at all

and, I really really wonder how Xilinx has managed to get
a MicroBlaze to fit into 75% of Spartan-3A !!!

IMHO none of Xilinx MicroBlaze released versions would fit into 75% of
S3-50A never!

maybe MicroBlaze 6 has special options to be 'ultra lite' like NIOS
has, then it might be possible, but otherwise I have hard times
believing MicroBlaze fits into 50A

Antti


Article: 113021
Subject: Re: Spartan-3A launched
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 5 Dec 2006 11:59:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@xilant.com> wrote:
> Antti schrieb:

> > as Xilinx PR ES samples are available, and tools support for S3A also,

> as usual - the documentation is not complete :(

> the DNA featured (unique ID) is only mentioned and not described at all

> and, I really really wonder how Xilinx has managed to get
> a MicroBlaze to fit into 75% of Spartan-3A !!!

> IMHO none of Xilinx MicroBlaze released versions would fit into 75% of
> S3-50A never!

> maybe MicroBlaze 6 has special options to be 'ultra lite' like NIOS
> has, then it might be possible, but otherwise I have hard times
> believing MicroBlaze fits into 50A

It's a pity that the datasheet doesn't mention the xc3s1400a_pq208 that the
ISE 8.2 BSDL file made us hope for.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 113022
Subject: Re: Spartan-3A launched
From: "Antti" <Antti.Lukats@xilant.com>
Date: 5 Dec 2006 03:59:57 -0800
Links: << >>  << T >>  << A >>
Antti schrieb:

> Antti schrieb:
>
> > as Xilinx PR ES samples are available, and tools support for S3A also,
>
> as usual - the documentation is not complete :(
>
> the DNA featured (unique ID) is only mentioned and not described at all

uups (I should RTFM) it is described fully

Antti
PS the biggest news is possible extended VCCAUX range!
now S3a can be used similar to Altera FPGAs with only 2 voltages
eg separate VCCAUX is no longer required!


Article: 113023
Subject: Re: Spartan-3A launched
From: "Jon Beniston" <jon@beniston.com>
Date: 5 Dec 2006 04:17:58 -0800
Links: << >>  << T >>  << A >>

Antti wrote:
> Antti schrieb:
>
> > as Xilinx PR ES samples are available, and tools support for S3A also,
>
> as usual - the documentation is not complete :(
>
> the DNA featured (unique ID) is only mentioned and not described at all
>
> and, I really really wonder how Xilinx has managed to get
> a MicroBlaze to fit into 75% of Spartan-3A !!!
>
> IMHO none of Xilinx MicroBlaze released versions would fit into 75% of
> S3-50A never!
>
> maybe MicroBlaze 6 has special options to be 'ultra lite' like NIOS
> has, then it might be possible, but otherwise I have hard times
> believing MicroBlaze fits into 50A

Save yourself some trouble. Give it 12 months after the PR before you
try to use them.

Cheers,
Jon


Article: 113024
Subject: Re: Spartan-3A launched
From: "Antti" <Antti.Lukats@xilant.com>
Date: 5 Dec 2006 04:24:54 -0800
Links: << >>  << T >>  << A >>
Jon Beniston schrieb:

> Antti wrote:
> > Antti schrieb:
> >
[]
> Save yourself some trouble. Give it 12 months after the PR before you
> try to use them.
>
> Cheers,
> Jon
Jon,

12 Month's ? They will be obsolete by then - Cyclone-III is coming out
in late February(or March) and Altera has promised IMMEDIATE
availability
of both silicon and development boards, starting from PR launch date.

Antti




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1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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