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Vitaliy wrote: > In to_integer(signed(My_slv)), does signed relate to integer or to > arithmetic (I think integer, but just checking)? Because there are two > libraries: > > ieee.numeric_std.signed and ieee.std_logic_arith.signed > > So, when I specify the complete name of the library (i.e > ieee.numeric_std.signed), the compiler is happy. > > > Vitaliy > > KJ wrote: > >>"Vitaliy" <m.vitaliy@gmail.com> wrote in message >>news:1165773211.677889.327250@73g2000cwn.googlegroups.com... >> >>>The writing is working now (I shrinked the input file too much, so >>>there was nothing to be processed. Still have question about converting >>>two's complement to integer. >>> >>> >>>>2) The output of the core is two's complement. Is there a standard >>>>procedure in VHDL to transform the data from two's complement to >>>>integer? >>>> >> >>To convert a std_logic_vector (ex. My_slv) that is being interpreted as >>'twos complement' to an integer use... >> >>to_integer(signed(My_slv)) >> >>KJ > > Don't use both numeric_std and std_logic_arith. They have different definitions for the same function names. If you do use both, then you have to specify which one each library call belongs to.Article: 113301
Steve wrote: > Hi all, > > I want to add an Ethernet interface to my FPGA board for data transmission. > But I'm not sure which scheme I should use. > > A) There's a PHY on the FPGA board, but I don't have much knowledge or > experience on MAC. The protocol seems complicated and not easy to implement > in a short time. Is it possible to develop a small and simple MAC? My idea > is packing data to form a standard TCP or UDP packet and using the PHY to > send out or receive it. Another reason I don't want using a full MAC is it > costs too much resources (~2000 slices). If I use MicroBlaze+OPB MAC, I > can't afford the license fee. > > B) Using another external Ethernet micro-controller, such as Rabbit > microprocessor. I can develop an interface between FPGA and uC for data > transmission. But I'm wondering how fast the speed is? > > C) Using micro-controller + (MAC+PHY Ethernet single chip). Then porting > uClinux or lwip to the uC and hanging FPGA to the address/data bus of the > uC. > > Any suggestions? Thank you. > > JJ If you have a modest cpu onboard, you might also want to look at the very light software TCP stacks by Adam Dunkels. These get widely mentioned in some software sites with an interest in this sort of thing. Should work on most of the FPGA softcores but some google work needed. www.sics.se/~adam/lwip the other JJ John Jakson transputer guyArticle: 113302
Hi, What does a statement like @(posedge clk) synthesise to? if i write:- input b; output c; a=b; @(posedge clk); c=a;Article: 113303
On 8 Dec 2006 21:26:35 -0800, beagle197@hotmail.com wrote: >Folks, > >I have an EDK(*1) based project that utilizes the Microblaze, along >with several peripherals connected via OPB (on-chip peripheral bus) for >use with a Spartan3(*2). The project is set to use VHDL. I would like >to develop a custom data encoder(*3) Verilog module that can be >accessed via C, and I am trying to determine if developing the module >as device that attaches to the OPB would be a good choice of >implementation. Probably I am missing some important technical >considerations about the verilog module's interfaces, etc. However, it >appears that if I try to develop the lzw_opb in this fashion, it will >require that I write a device driver similar to the other OPB >components. Also since the project is set for VHDL, I am not certain >how to develop the Verilog project along side. Wondering if anyone else >has had a similar issue and can perhaps shed some light on how to >approach this kind of problem? You may develop your OPB device without giving a monet thoguht to driver: if you don't provide one, EDK will use "generic" for it. You may use OPB_IPIF as base design, but I have had no problem in designing my own devices directly connected to OPB, and they usually are more efficient. I don´t remember if MB in EDK 6.3 had FSL links, they are a nice alternative for some applications. Best regards, ZaraArticle: 113304
Nevo wrote: > I have a board designed around the EP1C6 Cyclone device. The Quartus > programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able to > initiate programming the device over the JTAG port, but Quartus gives me an > error CONF_DONE failed to go high on device 1. Interesting that you have these problems... I have very recently inherited a board which I am using for a very different purpose to that for which it was originally intended. The board is based on an EP2C35 and has options for both passive and active serial configuration, as well as JTAG. The former options require configuration devices to be plugged into DIP sockets on the board. Not needing auto-configuration, I dispatched with the config devices (I actually don't *own* any) but was met with "CONF_DONE not going high" when attempting to configure via JTAG. After scratching my head for some time, I eventually tried it with the config device plugged in - and it worked! Now I can't for the life of me understand why this device must be present for JTAG programming? There's a pullup on CONF_DONE (10k)and nSTATUS (10k). What's more, at one stage I configured the FPGA then removed the config device whilst still powered - and I'm pretty sure a subsequent attempt to configure the FPGA via JTAG actually succeeded!?! Ultimately I need a solution because eventually I probably won't have access to the config device (it's on a small daughterboard) and I just don't like not knowing *why* it doesn't work!?! So any suggestions/insight/wild guesses would be most welcome here too! I guess I should add that CONF_DONE is being routed to an empty header (for ASM programming) and also an empty socket. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 113305
On 2006-12-11, vittal <vittal.patil@gmail.com> wrote: > Hi, > What does a statement like @(posedge clk) synthesise to? > if i write:- > > input b; > output c; > a=b; > @(posedge clk); > c=a; Verilog introductions are TERRIBLE about clarifying what's synthesizable and what's not. Verilog is two languages in one -- one procedural language that is useful for controlling simulations, and one hardware description language which can be synthesized. Your sequence of instructions might be useful for an input stimulus file, but not for describing hardware. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 113306
vittal wrote: > Hi, > What does a statement like @(posedge clk) synthesise to? > if i write:- > > input b; > output c; > a=b; > @(posedge clk); > c=a; Assuming your 'a' is a reg it will systhesize to one DFF with input b and ouput c.Article: 113307
Ray Andraka wrote: > googlinggoogler@hotmail.com wrote: > >> I don't wish to hijack your thread, but what would you use recursive >> component instantiation for? are you instantiating within an >> instantiation? >> >> Cheers >> >> david >> > > Sometimes a parameterized component is easiest to generate with > recursion. For example an adder tree can be generated by recursively > calling a component that adds two vectors. > > Thank you all for the answers. The example with a parameterized component is exactly what I have designed. I have a generic component that implement the looping algorithm used to calculate the configuration bits for a Benés network with a generic number of ports. The lowest level is for a 4-port Benés network. For each hierarchal level the number of ports are doubled. I have simulated my code in modelsim and it have the correct behavior but in synthesis I get a width mismatch for one of the output ports. Unfortunately no figures of the different widths are printed by synplify so I can't know at which level the error occurs. But from your answers I now know that synplify should fix this. Maybe it could be a problem with how generics are handled (global or local?) Thanks again! Cheers PatrikArticle: 113308
"Have you tried using A9 and A11, but not A10?" I have only tried all A9, A10 and A11 together and not A9,A11 seperately. Thanks Mohni. > > The one thing that comes to mind is that A10 has more than one > function. > So if you are not generating the "AutoPrecharge" function properly > during > Read and Write cycles, or "SelectAllBanks" function during refresh, you > can run into problems. Have you tried using A9 and A11, but not A10? > > HTH, > GaborArticle: 113309
can someone tell me what these pins do? I'm trying to build a module with system ace on board, and trying to program the Virtex4 using the JTAG connections (tck, tdo, tdi, tms). can i live without PROG_B and INIT? I'm not an expert, i'm just trying to build something that works. Thxx tejoArticle: 113310
What do you mean? if you are talking about preventing the board to configure the FPGA on power-up, you can remove the jumper JP1 from the board (or put it into disable flash read position) or from impact, you can erase the PROM tejo florent.peyrard@gmail.com wrote: > Hi all, > > in other words, is there an easy way to avoid FPGA attempt to > configure? > > thanks > florentArticle: 113311
If you planning to do some SW acceleration I would advice to use the FSL interface on MicroBlaze instead. There are drivers for handling FSL communication with EDK and you will most likely have a more performance by using FSL instead of OPB. Göran <beagle197@hotmail.com> wrote in message news:1165641995.350599.236560@79g2000cws.googlegroups.com... > Folks, > > I have an EDK(*1) based project that utilizes the Microblaze, along > with several peripherals connected via OPB (on-chip peripheral bus) for > use with a Spartan3(*2). The project is set to use VHDL. I would like > to develop a custom data encoder(*3) Verilog module that can be > accessed via C, and I am trying to determine if developing the module > as device that attaches to the OPB would be a good choice of > implementation. Probably I am missing some important technical > considerations about the verilog module's interfaces, etc. However, it > appears that if I try to develop the lzw_opb in this fashion, it will > require that I write a device driver similar to the other OPB > components. Also since the project is set for VHDL, I am not certain > how to develop the Verilog project along side. Wondering if anyone else > has had a similar issue and can perhaps shed some light on how to > approach this kind of problem? > > The basic design I have in mind is as follows: > > Data Input => UART => C code running on uBlaze => updates state of > lzw_opb => UART => Data out > > Thanks, > BEA > > *1 Using Xilinx EDK 6.3 Build EDK_Gmm.12.3+1 > *2 Spartan3 xc3s400 > *3 LZW compression algo >Article: 113312
lubot77 schrieb: > I do have a interesting project. I am planing to wire my house with duplex > multimode fiber. I would like to send from a central location of the house > multiple broadcast video and audio signals. The video should be either 10 or > 12bit digital stream. > With the help of a FPGA we should multiplex I would say up to 5 digital > parallel video streams(each around 200Mbs, with 16M clk and 3Mbs for four > audio channels). The mux out should be 16 or 20bit data stream. Sounds like a Version of our GLINK for SDI-Video and without Keyboard ;-) http://www.bgmbh.de/cnt/produkte/GLINK2.htm ChristianArticle: 113313
burn.sir@gmail.com schrieb: > In an interview from 97, Bob Yannes the designer of MOS 6581 (aka > "SID") said the following aboud the chips ASDR enveloper: > > "In order to more closely model the exponential decay of sounds, > another look-up table on the output of the Envelope Generator would > sequentially divide the clock to the Envelope Generator by two at > specific counts in the Decay and Release cycles. This created a > piece-wise linear approximation of an exponential. I was particularly > happy how well this worked considering the simplicity of the circuitry. > The Attack, however, was linear, but this sounded fine." > > In short, he was using an down-counter to count down from 255 down to > some number, but he somehow made the counter to move > pseudo-exponentially instead of linearly. > > Does anyone know how this works? Well, he explains it, doesn't he? "sequentially divide the clock to the Envelope Generator by two at specific counts in the Decay and Release cycles" So there is a linear down counter, with a clock divider in front. Based on the counter value the clock devider value is increased. In an FPGA you would want to control a clock enable instead of the clock. Kolja SulimmaArticle: 113314
ok I will put it like this.. always @(*) begin a=b; @(posedge clk); c=a; end What does it mean. Neo wrote: > vittal wrote: > > Hi, > > What does a statement like @(posedge clk) synthesise to? > > if i write:- > > > > input b; > > output c; > > a=b; > > @(posedge clk); > > c=a; > > Assuming your 'a' is a reg it will systhesize to one DFF with input b > and ouput c.Article: 113315
Hi, kypilop schrieb: > Libero version is 7.2 > FlashPro Program version is 4.2 > Synflify version is 8.1 for Actel Do you use the same synthesis software for the Altera device? For some "broken" [1] code, you will see different tools generating functional different output There are several reasons why your design won't work in a actual device even if you allready had your design successful running on another device. Even valid code and usage of the the same tool may result in different functionality, if you had timing problems or forget to set needed timing constraints. bye Thomas [1] Some code has to be considered broken, if it is legal vhdl, but wrong supported, more often you have nonstandard code which is accepted by some tools, but may result in different functionality on different tools.Article: 113316
Burns, I am not the OP and I agree regarding your netiquette statement. Alan burn.sir@gmail.com wrote: > Alan, > > first of all, if you want to ask questions, please respect the > newsgroup "netiquette". there are already way too many "plz help!!! > design doesnt work!!!" posts on this NG. > > that being said, lets take a look at your problem. i am not an expert, > hopefully i can do some helping anyway :) > > >>The board is A3PE-A3P-EVAL-BRD1 REV3 which is manufactured by Actel Co. >>This board has expantion port for I/O, some LEDs, 1 LCD and regulators, >>just simple design. >> > > A very simple board, rock solid FPGA. Ive never had any problems with > that one. but as far as i know, they come with a A3P250, not a > A3P-1000... > > >>The tested VHDL source has function of serial communication(UART). >> > > but there are no UART connectors on this board? > > > >>And always, LED blink correctly in VHDL source >>But serial communication function operates unregular >>Sometimes Reciever operates well, But Transmitter is not. >>Sometimes Transmitter operates well, But Reciever is not. >> > > Either your board or FPGA is borken, or its your VHDL design. I would > bet on the latter. > > >>X-tal is 11.0592MHz and operates correctly. >> > > the default board clock is 40. are you using a PLL? some of the PLLs > are not powered on some actel boards, and sometimes Designer chooses to > use one of them. check your boards documentation! > > > >>Supply voltage is 3.3V for I/O which supplied by Application board from >>Actel >>As I know, TTL level can adapt CMOS 3.3V >>Power ground was one point. >>And I use RS232 to USB converter, but they operate well. Self test >>passed. >> > > that doesnt prove anything. find a scope and check the TX signal > manually. > and I wouldnt add extra sources of failure when things arent working, > connect the UART directly to your PC! > > >>I don't know well about timing constraints which is default option. >>But palce&router of Actel said satisfying the timing constraint. >> > > do you actually _have_ any? > in any case, i dont think something as simple as an UART could have > timing problems. > > >>I can't understand about this situation.... >>I use same source(VHDL), same program tool(Libero), same >>device(A3P1000) and same programmer(FlashPro3)....But the device >>operation is not regular.... >>I test some functions using StartKit from Actel Co. >>Many times, parts of function are un-operation.... >>The un-operated functions are not fixed !!! Malfunctions are >>irregular..................... >> > > I usually get this kind of behavior when i forget to synchronize > external signals before reading them. google for "Peter Alfke" and > "Metastability" for more info. > > >>Also, the source of VHDL had been verified in Altera device >>(EPF10K100ARC240) >>In Altera, all functions are operated correctly........... >> > > I dont think it has anything to do with the FPGA vendor. I have had the > same quick'n-dirty UART design running on actel, xilinx, altera and > lattice boards without any problems. > > your problem could of course have something to do with the different > clocks on each board, maybe in some cases the _derived_ uart clock > differs a few percent too much against the ideal UART clock?? > > >>Always, Actel's programmer said "Verifying Passed"....Is that true???? >> > > that means that flash pro writes your program to FPGA, then reads it > back to make sure there were to communication errors. > note that some actel FPGAs cant do readback, so the flash pro tool > sometimes says Verifying Passed" without really checking. > > > >>Plz, help me.... I lost self control using Actel's device.... Help me, >>Help me >> >>Are U want any informations? Plz, let me know.. I'm beginner of FPGA.. >>:-) >>Are there some options or parameters to consider for palce&route ? >> > > no, the default options are usually ok. > > one last thing, the Libero tool comes with a _superb_ beginner tutorial > (there are also videos on their web site), which explains everything > from creating a project to post-layout simulation. have a good look at > those document, then do a post-synthesis simulation to find those nasty > bugs. > > > > burns > >Article: 113317
"Vitaliy" <m.vitaliy@gmail.com> wrote in message
news:1165779955.314942.70530@l12g2000cwl.googlegroups.com...
> In to_integer(signed(My_slv)), does signed relate to integer or to
> arithmetic (I think integer, but just checking)?
'signed' relates to how the std_logic_vector is supposed to be interpreted.
All by itself std_logic_vectors have no implicit 'sign' bit or any sort of
numerical interpretation so, for example, "10000000" could mean either 128
(decimal) or a negative number or just a collection of 8 bits of 'stuff'.
signed("10000000") means that the bit on the left is to be interpreted as a
sign bit and the vector is a twos complement representation of a number,
which means that in this case we're talking about a negative number, 8 bit
numbers can represent anything from -128 to +127.
There is also the function unsigned() which says that there is no sign bit
in the std_logic_vector argument so unsigned("10000000") is a positive
number, in this case 128. If you're only dealing with things that cannot be
negative there is no value in the 'sign' bit, 8 bit numbers can represent
anything from 0 to 255.
To convert the std_logic_vector to an integer via the to_integer() function
you need to supply it with an argument that has a specific interpretation
which is what the signed() and unsigned() functions provide.
> Because there are two libraries:
> ieee.numeric_std.signed and ieee.std_logic_arith.signed
Don't use std_logic_arith, it has problems and it is not a standard.
> So, when I specify the complete name of the library (i.e
> ieee.numeric_std.signed), the compiler is happy.
Since both libraries have a 'signed' function and the compiler can't tell
the difference between the two of them by their usage, specifying the full
path name to the function that you want is the work around. Sometimes this
is handy but in this particular instance you'd be better off getting rid of
std_logic_arith.
By the way, since the title of the thread is ''Writing output signals to
text file (VHDL)" I'm guessing that you actually want to write out this
integer as text in which case you'll probably be needing to convert that
integer to a text string in order to write it to a text file. This can be
done with
integer'image(My_integer)
or combining with the conversion of the std_logic_vector to an integer....
integer'image(to_integer(signed(My_slv))
KJ
Article: 113318Hello all, This is the first time i am working with Flash. Has anyone experienced with reading data from intel strata flash p30. I read the flash data-sheet and it says that in order to read array i need to write 0xFF to device base address. I didn't find the place where I insert the desire address to read from. can anyone explain me in simeple words what is the read or write sequence of the Flash. My next step is to write a C code that impliments the procedures of reading and writing. I have an OPB_EMC. I have talked with xilinx support and the guy there told me not to use xio_in16 or xio_out16 with the opb_emc base address + offset. Does anyone know what instead?? so, thanks alot in advance. GuyArticle: 113319
On Sun, 10 Dec 2006 22:39:35 -0500, Ray Andraka <ray@andraka.com> wrote: >..Getting the data back into natural order requires an additional memory buffer >which adds to the latency and increases the hardware complexity. Well, it does add latency, but the bit-reversal transformation can be done in place with no additional buffer. Robert Scott Ypsilanti, MichiganArticle: 113320
Guy_FPGA wrote: > Hello all, > This is the first time i am working with Flash. > Has anyone experienced with reading data from intel strata flash p30. I > read the flash data-sheet and it says that in order to read array i > need to write 0xFF to device base address. I didn't find the place > where I insert the desire address to read from. can anyone explain me > in simeple words what is the read or write sequence of the Flash. > > My next step is to write a C code that impliments the procedures of > reading and writing. I have an OPB_EMC. I have talked with xilinx > support and the guy there told me not to use xio_in16 or xio_out16 with > the opb_emc base address + offset. Does anyone know what instead?? > > > so, thanks alot in advance. > > Guy Once the device is in read array mode (which it defaults to on power up or reset) simply assert the address you want to read on the address bus and read the data on the data bus (i.e. it's a normal memory device). Cheers PeteSArticle: 113321
Hi, I am trying to integrate a ps2 core (for Keyboard) to Microblaze with the Create/Import Wizard. I cannot get this integration since an error occur from "Sys_clk_pin". The question is the following? How can I incorporate VHDL code to a design with MIcroblaze, because I have a Microblaze system with a program.c and a vhdl core and I want to download both to the Spartan 3E. Thanks, and sorry for my English.Article: 113322
ok, say i have managed to program it.Do I read it using the emc as if it is a regular sram ? can i use the xio_in? thanks PeteS wrote: > Guy_FPGA wrote: > > Hello all, > > This is the first time i am working with Flash. > > Has anyone experienced with reading data from intel strata flash p30. I > > read the flash data-sheet and it says that in order to read array i > > need to write 0xFF to device base address. I didn't find the place > > where I insert the desire address to read from. can anyone explain me > > in simeple words what is the read or write sequence of the Flash. > > > > My next step is to write a C code that impliments the procedures of > > reading and writing. I have an OPB_EMC. I have talked with xilinx > > support and the guy there told me not to use xio_in16 or xio_out16 with > > the opb_emc base address + offset. Does anyone know what instead?? > > > > > > so, thanks alot in advance. > > > > Guy > > Once the device is in read array mode (which it defaults to on power up > or reset) simply assert the address you want to read on the address bus > and read the data on the data bus (i.e. it's a normal memory device). > > Cheers > > PeteSArticle: 113323
Guy_FPGA wrote: > ok, > say i have managed to program it.Do I read it using the emc as if it > is a regular sram ? > can i use the xio_in? > > thanks > > > PeteS wrote: > > Guy_FPGA wrote: > > > Hello all, > > > This is the first time i am working with Flash. > > > Has anyone experienced with reading data from intel strata flash p30. I > > > read the flash data-sheet and it says that in order to read array i > > > need to write 0xFF to device base address. I didn't find the place > > > where I insert the desire address to read from. can anyone explain me > > > in simeple words what is the read or write sequence of the Flash. > > > > > > My next step is to write a C code that impliments the procedures of > > > reading and writing. I have an OPB_EMC. I have talked with xilinx > > > support and the guy there told me not to use xio_in16 or xio_out16 with > > > the opb_emc base address + offset. Does anyone know what instead?? > > > > > > > > > so, thanks alot in advance. > > > > > > Guy > > > > Once the device is in read array mode (which it defaults to on power up > > or reset) simply assert the address you want to read on the address bus > > and read the data on the data bus (i.e. it's a normal memory device). > > > > Cheers > > > > PeteS Assuming you have successfully programmed the device, it's readable as a standard memory device. Check the timings; flash and sram are not quite the same although in most cases the same timings are adequate. As to using your core, I can give you no advice without looking at the details. If this is a standard core, then no doubt others here who may have used it might be able to help. Cheers PeteSArticle: 113324
Robert Scott skrev: > On Sun, 10 Dec 2006 22:39:35 -0500, Ray Andraka <ray@andraka.com> wrote: > > >..Getting the data back into natural order requires an additional memory buffer > >which adds to the latency and increases the hardware complexity. > > Well, it does add latency, but the bit-reversal transformation can be done in > place with no additional buffer. In an FPGA you still need specific hardware to implement the bit-reverse reordering of the data. Rune
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