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Messages from 11425

Article: 11425
Subject: Re: Negative pulse form Altera FPGA's ? - to: Tullio Grassi
From: Botond Kardos <Kardos.Botond@hu.innomed.NOSPAM>
Date: Wed, 12 Aug 1998 11:41:13 -0400
Links: << >>  << T >>  << A >>
Hi Tullio,
  I don't see your post on my news server so I had to reply to mine.
  The reason I asked this trivial-looking question is: the I/O cell
register in Altera Flex devices doesn't have an ASET input. Or am I
missing something ?

   Botond

-- 
Botond Kardos  -  at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
      To get my real address just put the domain
      name in reverse order and remove 'nospam'.
      x@1.2.3 -> x@2.1
Article: 11426
Subject: Re: FFT-Speed
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 12 Aug 1998 09:10:23 -0700
Links: << >>  << T >>  << A >>
Xilinx has a document, now about 18 months old, that has some FFT
comparisons.  It's an Acrobat document at
http://www.xilinx.com/appnotes/fft.pdf.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Thomas Focke wrote in message <35D1AFFE.F6371A4E@himh1.hi.bosch.de>...
>I'm looking for a comparison regarding achievable FFT-speed between
>FPGA vs. DSP-solutions.
>For instance: DSP TMS C6x can manage a 1024 point-FFT in 104 s.
>Which FPGA can achieve which speed?
>Is there a comprehensive table in the web?
>
>Who can help me?
>
>Thomas


Article: 11427
Subject: Re: Combinatoric Divide-by-3 Algorithm
From: jsavard@tenMAPSONeerf.edmonton.ab.ca (John Savard)
Date: Wed, 12 Aug 1998 16:11:41 GMT
Links: << >>  << T >>  << A >>
"Kenneth W. Wagner" <Kenneth.W.Wagner.1@gsfc.nasa.gov> wrote, in part:

>I need to implement in an fpga an algorithm that will divide an integer
>by 3.  The dividend length is still to be determined but will be
>somewhere between 20 and 30 bits, and the divisor is always the number
>3.

1/3 in binary notation, as other respondents have noted, is

.010101010101....

There isn't an algorithm I know of for scaling numbers that is
essentially different from either multiplication or long division. All
you can do to increase the speed of the operation is to decrease the
number of steps by operating on larger chunks of the number at a time.
So I'd suggest a table-driven approach, but that isn't that suitable
to an FPGA.

However, at least there's a pattern to the expression for 1/3.

First, multiply your number by .0101 ...

then multiply it by 1.0001, 1.00000001, 1.0000000000000001, and so on.
Thus, you obtain a multiplication by

.01010101

in three (instead of four) additions, and a multiplication by

.0101010101010101

in four (instead of eight) additions.

This is the same idea that is used in "Russian Peasant
Multiplication", or in fast exponentiation.

John Savard
http://www.freenet.edmonton.ab.ca/~jsavard/index.html
Article: 11428
Subject: Re: Gray code counter in ABEL HDL?
From: "Mark Purcell" <map@NOSPAM_transtech-DSP.com>
Date: 12 Aug 1998 20:35:50 GMT
Links: << >>  << T >>  << A >>


Marc Heuler <marc@aargh.franken.de> wrote in article
<+-pMC*BFo@aargh.franken.de>...
> I want to implement a Gray code counter (16 bit) in ABEL HDL for the
> Lattice 1016 device.
> 
> Are there gray-code-counter examples on the net?
> 

Here's a 4 bit gray counter in ABEL that can be expanded to however many
bits you like. This uses 'equation substitution'; I'll explain all this as
I go along.
First, let's assume you want a 4 bit gray counter that is a Moore type
counter, i.e. the count bits are the outputs of flip flops, and the gray
code state is fed back and decoded to form the next gray state. Call this
count output vector [g3,g2,g1,g0]. These bits are the outputs of the flip
flops forming the counter.

Next, let's define a binary vector, [b3,b2,b1,b0], which don't actually
exist as signals but can be decoded so that each binary state maps onto one
of the gray states. Finally let's define a 'next binary' vector
[nb3,nb2,nb1,nb0] which again don't actually exist but defines the next
binary state.

There is a well known logical transformation that we can do to map binary
states to gray states so that a binary sequence will result in a gray coded
sequence (these equations are in ABEL parlance whereby '$' represents XOR):

g3  =  b3;
g2  =  b3 $ b2; 
g1  =  b2 $ b1;
g0  =  b1 $ b0;

and the inverse operations:

b3  =   g3;
b2  =   g3 $ g2;
b1  =   g3 $ g2 $ g1;
b0  =   g3 $ g2 $ g1 $ g0;

These equations can obviously be extended for as many bits as is needed. 

We can use these to produce a gray coded counter. The method goes like
this:

Use the [g3,g2,g1,g0] gray state, and decode an intermediate binary value
from this [b3,b2,b1,b0]. Then decode the next binary state
([nb3,nb2,nb1,nb0]) from this which is just adding 1 to the [b3,b2,b1,b0]
vector, then convert back to gray and feed into the 'd' inputs of the
[g3,g2,g1,g0] flip flops.

Now all we need to do is write some ABEL to do it. ABEL has the ability to
do 'equation substitution', i.e. if you define an equation in the
DECLARATIONS section but before the
EQUATIONS section, it will substitute the string in the source before
compiling (almost like a '# define' in C). Moreover, ABEL can substitute
into a substitution, which basically allows multi-level decoding without
needing intermediate nodes. 

Here's a finished ABEL file that defines a 4 bit gray counter using
multi-level substitution:

module gray4;
                                   
gray4 device 'mach230a';

declarations

"inputs
clk     pin     ;   
reset   pin     ;

"outputs
g3      pin     istype 'reg,buffer';   
g2      pin     istype 'reg,buffer';  
g1      pin     istype 'reg,buffer';   
g0      pin     istype 'reg,buffer';  


"definitions
H, L, X, Z, C = 1, 0, .X., .Z., .C.;

g   =  [g3,g2,g1,g0];

"binary decoded bits from the gray state. Note the braces are important!
b3  =   (g3); 
b2  =   (g3 $ g2);
b1  =   (g3 $ g2 $ g1);
b0  =   (g3 $ g2 $ g1 $ g0);

"calculate the next binary value from above, i.e. add 1
nb3 =   (b3 $ (b2 & b1 & b0));
nb2 =   (b2 $ (b1 & b0));
nb1 =   (b1 $ (b0));
nb0 =   (b0 $ 1);

equations

g.c  = clk;
g.ar = reset;

"convert next binary state back to gray code
g3  :=  nb3;
g2  :=  nb3 $ nb2;
g1  :=  nb2 $ nb1;
g0  :=  nb1 $ nb0;


"test_vectors
test_vectors 'Gray counter'
([reset, clk] -> [g3, g2, g1, g0])
 [  1  ,  C]  -> [ 0,  0,  0,  0 ];
 [  0  ,  C]  -> [ 0,  0,  0,  1 ];
 [  0  ,  C]  -> [ 0,  0,  1,  1 ];
 [  0  ,  C]  -> [ 0,  0,  1,  0 ];
 [  0  ,  C]  -> [ 0,  1,  1,  0 ];
 [  0  ,  C]  -> [ 0,  1,  1,  1 ];
 [  0  ,  C]  -> [ 0,  1,  0,  1 ];
 [  0  ,  C]  -> [ 0,  1,  0,  0 ];
 [  0  ,  C]  -> [ 1,  1,  0,  0 ];
 [  0  ,  C]  -> [ 1,  1,  0,  1 ];
 [  0  ,  C]  -> [ 1,  1,  1,  1 ];
 [  0  ,  C]  -> [ 1,  1,  1,  0 ];
 [  0  ,  C]  -> [ 1,  0,  1,  0 ];
 [  0  ,  C]  -> [ 1,  0,  1,  1 ];
 [  0  ,  C]  -> [ 1,  0,  0,  1 ];
 [  0  ,  C]  -> [ 1,  0,  0,  0 ];

end gray4;

Hope this helps.

Mark.

Remove NOSPAM_ from email address








Article: 11429
Subject: Re: Security
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 12 Aug 1998 17:08:53 -0400
Links: << >>  << T >>  << A >>
Peter Gutmann wrote:
> 
> It depends on what level of sophistication you're expecting from your
> attackers.  DRAM contents can be recovered hours after power is removed, even
> longer if you store it at low temperatures.  SRAM is even worse, in extreme
> cases it's possible to recover the state months later.  I touch on this
> briefly towards the end of
> http://www.cs.auckland.ac.nz/~pgut001/pubs/secure_del.html, one day I'll
> finally get around to extending this section a bit.
> 
> Peter.

I am curious about this. To recover the data, do you power up the chip?
Or do you recover the data in a passive manner that requires you to open
the package? 

I think that any recovery method that requires you to open the chip
package will be robust enough to preclude any commercial copying. I
would think that powering up the chip would cause many random errors in
any data that was written to the chip before power down. 

I remember testing CPU boards and seeing the same data in memory every
time I powered up the board, as if the chip had a personal poweron
default just by virtue of its fabrication. This pattern was different
for each chip, but pretty consistent if power was off for long enough to
drain the supplies completely (> 30 secs). These were pretty old memory
chips, 2114 1K x 4 if I remember. Are newer chips different? Or does it
depend on the chip details such as manufacturer, chip type, phase of
moon?


-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 11430
Subject: Fixed Division by 3, 5, 7, 9, 15, 17 ...
From: tronsmith@my-dejanews.com
Date: Wed, 12 Aug 1998 21:32:45 GMT
Links: << >>  << T >>  << A >>
Divisor   1st Approx(A1)     2nd Approx(A2)    3rd Approx(A3) .....
   3       N/4 + N/16         A1+A1/2^4         A2+A2/2^8
   5       N/4 - N/16         A1+A1/2^4         A2+A2/2^8
   7       N/8 + N/64         A1+A1/2^6         A2+A2/2^12
   9       N/8 - N/64         A1+A1/2^6         A2+A2/2^12

This pattern works for all divisors = 2^k - 1 (3,7,15...)
or divisors = 2^k + 1  (5,9,17...)

It is more efficient in FPGA than the KCM I posted about earlier,
having area (ignoring routing) of order O(n log n). n for size
of adders, log n for number of adders.

Apologies for the jpgs in earlier posts.
- John L. Smith

In article <35d1bccb.4617156@news.prosurfr.com>,
  jsavard@tenMAPSONeerf.edmonton.ab.ca (John Savard) wrote:
> "Kenneth W. Wagner" <Kenneth.W.Wagner.1@gsfc.nasa.gov> wrote, in part:
>
> >I need to implement in an fpga an algorithm that will divide an integer
> >by 3.  The dividend length is still to be determined but will be
> >somewhere between 20 and 30 bits, and the divisor is always the number
> >3.
>
> 1/3 in binary notation, as other respondents have noted, is
>
> .010101010101....
>
> There isn't an algorithm I know of for scaling numbers that is
> essentially different from either multiplication or long division. All
> you can do to increase the speed of the operation is to decrease the
> number of steps by operating on larger chunks of the number at a time.
> So I'd suggest a table-driven approach, but that isn't that suitable
> to an FPGA.
>
> However, at least there's a pattern to the expression for 1/3.
>
> First, multiply your number by .0101 ...
>
> then multiply it by 1.0001, 1.00000001, 1.0000000000000001, and so on.
> Thus, you obtain a multiplication by
>
> .01010101
>
> in three (instead of four) additions, and a multiplication by
>
> .0101010101010101
>
> in four (instead of eight) additions.
>
> This is the same idea that is used in "Russian Peasant
> Multiplication", or in fast exponentiation.
>
> John Savard
> http://www.freenet.edmonton.ab.ca/~jsavard/index.html
>

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11431
Subject: Newbie seeks cheap fun w/FPGAs
From: mail83870@pop.net
Date: Thu, 13 Aug 1998 02:26:03 GMT
Links: << >>  << T >>  << A >>


Can anyone recommend a little tinkertoy kit ( no less than oh, say, 10K
gates, tho' ) that I can slap into my intel box ( linux/win* ) and play
with.  Bonus points for neat graphical interface.  I am hoping to spend
darn little.....

Thanks in advance for any help....

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11432
Subject: Re: Newbie seeks cheap fun w/FPGAs
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 12 Aug 1998 23:58:41 -0400
Links: << >>  << T >>  << A >>
Try Virtual Computer.  They've got several low cost PCI FPGA boards and the
package them with their hotworks hardware object software.
http://www.vcc.com

mail83870@pop.net wrote:

> Can anyone recommend a little tinkertoy kit ( no less than oh, say, 10K
> gates, tho' ) that I can slap into my intel box ( linux/win* ) and play
> with.  Bonus points for neat graphical interface.  I am hoping to spend
> darn little.....
>
> Thanks in advance for any help....
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11433
Subject: How to do FFT
From: nospammlankenau@yahoo.com (Marcus Lankenau)
Date: Thu, 13 Aug 1998 09:09:44 GMT
Links: << >>  << T >>  << A >>
Hi!


Is there any document on the web how fft works and how it is
implemented in logic or programming language (like c)?



Marcus Lankenau
Remove nospam from my email address to contact me
Article: 11434
Subject: Re: FFT-Speed
From: ems@nospam.riverside-machines.com (ems)
Date: Thu, 13 Aug 1998 13:10:55 GMT
Links: << >>  << T >>  << A >>
On Wed, 12 Aug 1998 17:08:46 +0200, Thomas Focke
<thomas.focke@himh1.hi.bosch.de> wrote:

>I'm looking for a comparison regarding achievable FFT-speed between
>FPGA vs. DSP-solutions. 
>For instance: DSP TMS C6x can manage a 1024 point-FFT in 104 s.
>Which FPGA can achieve which speed?

Forget it - this is way out of the league of an FPGA. I'm guessing
that the C6x time is for a 32-bit floating point complex FFT, without
bit-reversal.

First of all, you need a pipelined 32-bit FP adder, *and* a pipelined
32-bit FP multiplier (ie. you need an ASIC). For a 1K complex
transform, you also need a fast 8Kbyte data cache, with an access time
equal to the cycle time of the multiplier and adder.

There are a number of ways to do FFTs, but a straightforward radix-2
butterfly will require 6 cycles, with the adder producing a new result
on every cycle, and the multiplier producing 4 new results. You also
have to get a lot of data in and out of this mess on every cycle.

For a 1K transform, you repeat the butterfly 5120 times, giving a
total of 30,720 cycles, or 614us for a 20ns cycle. You then double
this for complex data, giving over 1.2ms, without bit-reversal,
compared to TI's time of approx. 100us (and, in practice, there will
probably be additional overhead related to getting data in and out of
cache).

In other words, using only one multiplier and one adder, on a 20ns
cycle time, means you're running at only one-tenth of the speed
already achievable by a commercial device. The only way to
significantly increase speed is to have multiple FP units, which is
what TI does. I looked at doing all this in an ASIC a few years ago,
but the costs were prohibitive, and the performance wasn't up to it.

Evan

PS - anyone out there need someone to do an FFT ASIC? Mail me at the
address above, minus the 'nospam'... :)

Article: 11435
Subject: ADPCM G.726 encoder/decoder
From: matthias werner <matthias_werner@latticesemi.com>
Date: Thu, 13 Aug 1998 16:30:08 +0200
Links: << >>  << T >>  << A >>
I am looking for the ADPCM G.726 spec. or better has somebody experience
with  a ADPCM G.726 implementation in a FPGA/CPLD ?

Thx in advance.

Matthias  Werner
Lattice Semiconductor
matthias_werner@latticesemi.com

Article: 11436
Subject: Re: Newbie seeks cheap fun w/FPGAs
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Thu, 13 Aug 1998 07:56:07 -0700
Links: << >>  << T >>  << A >>
Once you find the right board, you can probably find low-cost software for
the device on The Programmable Logic Jump Station at
http://www.optimagic.com/lowcost.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

mail83870@pop.net wrote in message <6qtirr$ees$1@nnrp1.dejanews.com>...
>
>
>Can anyone recommend a little tinkertoy kit ( no less than oh, say, 10K
>gates, tho' ) that I can slap into my intel box ( linux/win* ) and play
>with.  Bonus points for neat graphical interface.  I am hoping to spend
>darn little.....
>
>Thanks in advance for any help....
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum


Article: 11437
Subject: Re: Fixed Division by 3, 5, 7, 9, 15, 17 ...
From: Stephen Molloy <molloy@ix.netcom.com>
Date: Thu, 13 Aug 1998 11:28:05 -0700
Links: << >>  << T >>  << A >>
tronsmith@my-dejanews.com wrote:
> 
> Divisor   1st Approx(A1)     2nd Approx(A2)    3rd Approx(A3) .....
>    3       N/4 + N/16         A1+A1/2^4         A2+A2/2^8
>    5       N/4 - N/16         A1+A1/2^4         A2+A2/2^8
>    7       N/8 + N/64         A1+A1/2^6         A2+A2/2^12
>    9       N/8 - N/64         A1+A1/2^6         A2+A2/2^12
> 
> This pattern works for all divisors = 2^k - 1 (3,7,15...)
> or divisors = 2^k + 1  (5,9,17...)
> 
> It is more efficient in FPGA than the KCM I posted about earlier,
> having area (ignoring routing) of order O(n log n). n for size
> of adders, log n for number of adders.
> 

This is basically the same as solving y = x + y/4 recursively
(off by a scale factor). Should result in y = 4/3 x.
Combinational feedback loop is avoided if the result is
in redundant carry-save form (use carry-save addition stage
rather than conventional ripple adder, etc.). So if having
an output in carry-save form is ok, it only cost you a 
single stage of 3-2 adders. There is still a ripple involved,
just not the usual ripple.
Article: 11438
Subject: Continuously Charging 9V-battery
From: Erik van Duijn <erikvan.duijn@wxs.nl>
Date: Thu, 13 Aug 1998 21:22:12 +0200
Links: << >>  << T >>  << A >>
Hi,

I want to place a backup battery of 9V (NiCd or NiMh) in my scooter
alarm box as a backup to the scooter's 12V-battery. If a thief cuts the
power lines, I want the 9V-battery to start the sirene. What I am able
to do is design the cicuit that will make the 9V-battery to start the
sirene (about 150mA at 6-12V and 110dB) . What I DON'T KNOW is how to
continuously charge the battery as it is out of uses most of the time
(only when someone cuts those power lines). I.e.: it should be held up
to date until the moment it has to deliver current to the sirene. The
question is: HOW should I charge this battery from the 12V-system:
simply by a resistor? And how do I restrict the max. voltage (and what
is the max. voltage)

CAN SOMEONE HELP ME OUT PLEASE!!!!!!!

Erik van Duijn
Katwijk, Holland
e-mail: erikvan.duijn@wxs.nl


Article: 11439
Subject: Re: Newbie seeks cheap fun w/FPGAs
From: APS <resp@associatedpro.com>
Date: Thu, 13 Aug 1998 16:46:33 -0400
Links: << >>  << T >>  << A >>
check at http://www.associatedpro.com

mail83870@pop.net wrote:

> Can anyone recommend a little tinkertoy kit ( no less than oh, say, 10K
> gates, tho' ) that I can slap into my intel box ( linux/win* ) and play
> with.  Bonus points for neat graphical interface.  I am hoping to spend
> darn little.....
>
> Thanks in advance for any help....
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 11440
Subject: Problem configuring 10K30ATC144 w/ EPC1
From: mozur@my-dejanews.com
Date: Thu, 13 Aug 1998 22:16:26 GMT
Links: << >>  << T >>  << A >>
Has anyone seen problems configuring the 10K30ATC144-3 using an EPC1 OTP
EPROM?

I can program the part using a Byte Blaster, but the EPROM doesn't work. 
I've checked the various programming pins, such as nCE, CS, nCONFIG, etc. 
They all appear to be correct.

The confusing part is that there are no errors indicated by dropping the
nSTATUS line during the configuration.	The config lasts about 100ms, w /
clock & data running, at the end of which time CONFIG_DONE goes high for
about 250ns before going low again to retry.  n STATUS goes low after
CONFIG_DONE goes high.

Thanks

Matt Mozur
Siemens Medical Systems

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11441
Subject: Re: ADPCM G.726 encoder/decoder
From: Ed McCauley <emccauley@bltinc.com>
Date: Thu, 13 Aug 1998 18:36:58 -0400
Links: << >>  << T >>  << A >>
> I am looking for the ADPCM G.726 spec. or better has somebody experience
> with  a ADPCM G.726 implementation in a FPGA/CPLD ?
> 
> Thx in advance.
> 
> Matthias  Werner
> Lattice Semiconductor
> matthias_werner@latticesemi.com


Matthias,

1. Call Omnicom at 703-281-1505.  They're in Vienna, VA.  We do a lot of
telecom work and they've been able to supply us with all the CCITT
recommendations we've needed.

2. Yes, we've done plenty of ADPCM types of applications; however, we
only work with Xilinx.

Best wishes.

-- 
Ed McCauley
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA, (908) 996-0817
FAX:   (908) 996-0817
Article: 11442
Subject: XC6200 Inspector
From: sidhu@halcyon.usc.edu (Reetinder P. S. Sidhu)
Date: 13 Aug 1998 19:29:30 -0700
Links: << >>  << T >>  << A >>

Hi

	I've been working with the XC6200 (using the VCC board) for
the past two years. From the xilinx website I downloaded the XC6200
Inspector sometime back but I've been unable to use it. It gives the
following error:

		Inspector was unable to find the XC6200 device
		driver. You will not be able to execute any
		tests without one.

	But the XC200 PCI board I have works fine (I tested using
Webscope and PCI Test supplied by Hotworks.)

	 Please help!

							Reetinder Sidhu
Article: 11443
Subject: Comp Central
From: gimmemore1@aol.com (Gimmemore1)
Date: 14 Aug 1998 06:50:30 GMT
Links: << >>  << T >>  << A >>
www.compcentral.8m.com is a web site about Computer technology where looking
for writters and we justadded a chat room and a classafieds section. 
Article: 11444
Subject: Re: FFT-Speed
From: Paul van Haren <P.vanHaren@phys.uu.nl>
Date: Fri, 14 Aug 1998 12:07:29 GMT
Links: << >>  << T >>  << A >>
Thomas Focke wrote:
> 
> I'm looking for a comparison regarding achievable FFT-speed between
> FPGA vs. DSP-solutions.
> For instance: DSP TMS C6x can manage a 1024 point-FFT in 104 s.
> Which FPGA can achieve which speed?
> Is there a comprehensive table in the web?
> 
> Who can help me?
> 
> Thomas

There is a pretty survey of FFT implementations on
http://nova.stanford.edu/~bbaas/fftinfo.html
Try for instance also http://www.butterflydsp.com.

Paul van Haren
Article: 11445
Subject: FPGA Designer
From: The Employment Solution <ottreply@tes.net>
Date: Fri, 14 Aug 1998 12:15:23 GMT
Links: << >>  << T >>  << A >>
The Employment Solution

	We are currently seeking an FPGA Designer.  The ideal candidate will
possess the following:

 FPGA design experience
 Verilog experience

Project Description: This is a contract or permanent opportunity within
a large telecommunication organization. You will be responsible for FPGA
implementation with a team approach to define FPGA interfaces. The
successful candidate will be the prime for a hardware development
contract in an ATM group. Specifically the person is responsible for the
design of the FPGA for a PCB.

	For more information on the above opportunity, contact us at (613)
828-7887.  For those who are calling long distance, call toll free at
1-800-818-5469.  Resumes can be forwarded for consideration via email at
ottreply@tes.net, or through fax to (613) 828-2729. Visit our website
http://www.tes.net for more opportunities.
Article: 11446
Subject: BIG MONEY !!!!!!
From: The Employment Solution <ottreply@tes.net>
Date: Fri, 14 Aug 1998 12:16:10 GMT
Links: << >>  << T >>  << A >>
The Employment Solution

We are currently seeking Hardware Designers (2-4 Openings Available).
The ideal candidate will possess the following:

 VHDL
 FPGA and/or some ASIC Design experience
 Simulation and some board design experience

Our client is open to contract or permanent placement for these
positions. They are looking for hardware designers with FPGA and/or some
ASIC design experience, but more for the opening they have in the board
design group. In that area they are looking for design in VHDL, some
simulation, and some board design experience. For all the positions
experience in telecommunications, especially ATM and data switching, is
not required, but would be a very good asset.

For more information on the above opportunity, contact us at (613)
828-7887.  For those who are calling long distance, call toll free at
1-800-818-5469.  Resumes can be forwarded for consideration via email at
ottreply@tes.net, or through fax to (613) 828-2729. Visit our website
http://www.tes.net for more opportunities.
Article: 11447
Subject: Re: XC6200 Inspector
From: Tom Kean <tom@algotronix.com>
Date: Fri, 14 Aug 1998 13:30:32 +0100
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Reetinder P. S. Sidhu wrote:

> Hi
>
>         I've been working with the XC6200 (using the VCC board) for
> the past two years. From the xilinx website I downloaded the XC6200
> Inspector sometime back but I've been unable to use it. It gives the
> following error:
>
>                 Inspector was unable to find the XC6200 device
>                 driver. You will not be able to execute any
>                 tests without one.

The problem is exactly what the error message says: Inspector accesses the
board
via a device driver.  The other programs use a 'backdoor' mechanism which
gets
round the memory protection in Windows to make direct accesses to hardware.

It looks like you have an early version of the board and software: I'd see
if
VCC will supply you with an up to date CD which should have a device
driver.
Or check if the device driver and newer board libraries are also on the
Xilinx website.

Tom.


>
>
>         But the XC200 PCI board I have works fine (I tested using
> Webscope and PCI Test supplied by Hotworks.)
>
>          Please help!
>
>                                                         Reetinder Sidhu



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Article: 11448
Subject: Re: FFT-Speed
From: "John L. Smith" <jsmith@visicom.com>
Date: Fri, 14 Aug 1998 13:49:30 -0400
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ems wrote:

> On Wed, 12 Aug 1998 17:08:46 +0200, Thomas Focke
> <thomas.focke@himh1.hi.bosch.de> wrote:
>
> >I'm looking for a comparison regarding achievable FFT-speed between
> >FPGA vs. DSP-solutions.
> >For instance: DSP TMS C6x can manage a 1024 point-FFT in 104 s.
> >Which FPGA can achieve which speed?
>
> First of all, you need a pipelined 32-bit FP adder, *and* a pipelined
> 32-bit FP multiplier (ie. you need an ASIC). For a 1K complex
> transform, you also need a fast 8Kbyte data cache, with an access time
> equal to the cycle time of the multiplier and adder.
>

snip

> In other words, using only one multiplier and one adder, on a 20ns
> cycle time, means you're running at only one-tenth of the speed
> already achievable by a commercial device. The only way to
> significantly increase speed is to have multiple FP units, which is
> what TI does.

Evan,   Have you looked at any of the papers that discuss doing FFT
in FPGA using Distributed Arithmetic methods? Is an FP multiplier
absolutely necessary, or can some of the multiplications and/or additions
be performed more efficiently in FPGA by using the 4 input LUT
structures? If there is some flaw in the papers that have been written
saying FPGAs can outperform a C80, I'm sure many folks
would like to know.

> I looked at doing all this in an ASIC a few years ago,
> but the costs were prohibitive, and the performance wasn't up to it.
>
> Evan
>
> PS - anyone out there need someone to do an FFT ASIC? Mail me at the
> address above, minus the 'nospam'... :)



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Article: 11449
Subject: Re: Gray code counter in ABEL HDL?
From: lemieux@eecg.toronto.edu (Guy Gerard Lemieux)
Date: 14 Aug 98 18:21:55 GMT
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Marc Heuler wrote:
> 
> I want to implement a Gray code counter (16 bit) in ABEL HDL for the
> Lattice 1016 device.
> 
> Are there gray-code-counter examples on the net?

here's my Gray code counter in AHDL.
it's parameterized so you can make
the counter as long as you want.
the TFF labeled 'P' is the parity
bit.



%
Gray Code Counter
-----------------
        a gray code counter
%


PARAMETERS
(
        L = 16
);


SUBDESIGN graycnt
(
        clk      : INPUT;
        cnt_en   : INPUT;
        aclr     : INPUT = GND; -- asynchronous clear
        sclr     : INPUT = GND; -- synchronous clear
        q[L-1..0]  : OUTPUT;
)


VARIABLE

        P         : TFFE;
        G[L-1..0] : TFFE;

        tin[L-1..0] : NODE;
        cin[L-1..0] : CARRY;

BEGIN
        P.clk    =  clk;
        P.clrn   = !aclr;
        G[].clk  =  clk;
        G[].clrn = !aclr;

        P.t    = !sclr # (sclr & P.q);
        P.ena  = cnt_en # sclr;
        cin[0] =  P.q;
        tin[0] = !P.q;


        FOR I IN 0 TO L-2 GENERATE
                G[I].t   = (!sclr & tin[I]) # (sclr & G[I].q);
                G[I].ena = cnt_en # sclr;
                cin[I+1] = cin[I] & !G[I].q;
                tin[I+1] = cin[I] &  G[I].q;
        END GENERATE;
        G[L-1].t   = (!sclr & (tin[L-1] # cin[L-1])) # (sclr &
G[L-1].q);
        G[L-1].ena = cnt_en # sclr;

        q[] = G[].q;
END;
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%
Gray Code Counter
-----------------
	a gray code counter
%


PARAMETERS
(
	L = 16
);





SUBDESIGN graycnt
(
	clk      : INPUT;
	cnt_en   : INPUT;
	aclr     : INPUT = GND;
	sclr     : INPUT = GND;
	q[L-1..0]  : OUTPUT;
)



VARIABLE

	P         : TFFE;
	G[L-1..0] : TFFE;

	tin[L-1..0] : NODE;
	cin[L-1..0] : CARRY;

BEGIN
	P.clk    =  clk;
	P.clrn   = !aclr;
	G[].clk  =  clk;
	G[].clrn = !aclr;

	P.t    = !sclr # (sclr & P.q);
	P.ena  = cnt_en # sclr;
	cin[0] =  P.q;
	tin[0] = !P.q;

	FOR I IN 0 TO L-2 GENERATE
		G[I].t   = (!sclr & tin[I]) # (sclr & G[I].q);
		G[I].ena = cnt_en # sclr;
		cin[I+1] = cin[I] & !G[I].q;
		tin[I+1] = cin[I] &  G[I].q;
	END GENERATE;
	G[L-1].t   = (!sclr & (tin[L-1] # cin[L-1])) # (sclr & G[L-1].q);
	G[L-1].ena = cnt_en # sclr;

	q[] = G[].q;
END;

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