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Thanks Mike! will try this.Article: 114276
Signal can change on each rising edge or less often. "John_H" <newsgroup@johnhandwork.com> wrote in message news:12qa3g2otrg95e1@corp.supernews.com... > How often does the signal change relative to the two clocks? > > > "Matthieu Cattin" <matthieu.cattin@cern.ch> wrote in message > news:eo30bh$c3j$1@cernne03.cern.ch... >> Hi all, >> >> I have to transfert signals from a clock domain to another. >> First clock domain is fixed, but the second can be faster or slower than >> the first one. >> >> Does somebody can give me some help. >> >> Thanks >> Matthieu > >Article: 114277
Hi all, I have a design which has 15 blocks. Data enters from 1st block and after 60 clocks comes out from 15th block. I control enabling of each block by using a counter which counts till 60 at each clock (same clock as above). So this counter output(say count) goes to every block and every block has statements something like this : Blcok 1: If count >=2 than -----Do something end if; Blcok 2: If count >=4 than -----Do something end if; Blcok 3: If count >=7 than -----Do something end if; Blcok 4: If count >=18 than -----Do something end if; ...............and so on. Blcok 15: If count >=18 than -----Do something end if; My question is that is the data going in block 1 and being processed through all the blocks and than coming out of block 15 will be a Multi-Cycle path ? And why ? Thanks VedArticle: 114278
Has anybody any LWIP example?. I try to connect PC and Board. I try to send some package with tcp_write but I have errors because I can't get it. I don't want to implement a webserver, I only want a little code to transmit ethernet data. ThanksArticle: 114279
I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they 3.3V tolerant? Is there anyway of making this work without having to put down a level shifting buffer? Thanks, DaleArticle: 114280
I wrote a TechXclusives paper a while ago, on this exact subject: You can click on the (ridiculously long) URL: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=pa_clock_bound When the transmit clock is faster than the receive clock, there is of course the danger of "overrunning" the receiver, and thus losing data... Peter Alfke, Xilinx On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote: > Signal can change on each rising edge or less often. > > "John_H" <newsgr...@johnhandwork.com> wrote in messagenews:12qa3g2otrg95e1@corp.supernews.com... > > > How often does the signal change relative to the two clocks? > > > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message > >news:eo30bh$c3j$1@cernne03.cern.ch... > >> Hi all, > > >> I have to transfert signals from a clock domain to another. > >> First clock domain is fixed, but the second can be faster or slower than > >> the first one. > > >> Does somebody can give me some help. > > >> Thanks > >> MatthieuArticle: 114281
Catalyst Enterprise www.getcatalyst.com has their SPX Analyzer/Exerciser Software. With it you can construct any type of TLP packet and it will generate the proper LCRC. "Fred" <fred@nowhere.com> wrote in message news:45a426ef$2$27106$db0fefd9@news.zen.co.uk... >I need to simulate a PCI-E packet stream for a design with a correctly >formed LCRC. I've found some DLLP examples but no TLP examples. I've >Googled for too long and come up with nothing so far. > > Can anyone here help? >Article: 114282
I would like to superimpose some text into a video stream coming from a camera into my fpga. Lets say I would like to print the values of several registers to the screen as simple ascii text. This text would be superimposed over the incoming video stream. Does anyone know if there exists a core, or some free vhdl floating around somewhere to do this kind of thing? I have seen some cores that do VGA timing generation, then insert pixel values values from a look up table (but these dont do text from what I can tell, and must be controlled by a microprocessor). The problem with these is that they dont really do what I want. Really what I want is a function that would convert the value of a register into say, hex or base 10 ascii text, and then count the number of rows/columns of video coming in, and insert black or white pixels into the video stream as appropriate to make those characters appear (superimposed) on the output video stream. Anyone have any ideas or thoughts? thanks.Article: 114283
Dale,
Simplest method is to use resistors to scale the voltage to the correct
levels.
+out ------/\/\/\/\------+in------/\/\/\/\-----gnd
-out ------/\/\/\/\----- -in-----/\/\/\/\/-----gnd
Choose the R's to drop the voltage into the acceptable range desired.
You may also need some resistance from + to - to perform the termination
(or choose all the R's so that proper termination is also accomplished).
For a clock signal, you may also use capacitive coupling, but you still
need to terminate the receive, and then set the correct common mode
level at the receiver.
cap
+out --------||---------+in
|
51 ohms
|
Vcommon
|
51 ohms
|
-out --------||--------- -in
cap
Austin
Dale wrote:
> I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they
> 3.3V tolerant? Is there anyway of making this work without having to
> put down a level shifting buffer?
>
> Thanks,
> Dale
>
Article: 114284"Tom Lucas" wrote: >"Roberto Waltman" wrote: >... >> Go to http://www.maojet.com.tw, then "Products",... >>... >> They mention the 80186 + peripherals, not the '88, but they also >> mention "selectable 8/16 bit bus multiplexing" > >Well they do say it is software compatible with the 80188 which is quite >promising. Even if it is purely 80186 then altering the existing code to >work on that is going to be much much less work than porting it all to >an ARM or similar. The programming models of the 80186 and 80188 are identical, (as were the original 8086 & 8088), so no effort should be required to port software from one to the other. The bus interface unit is different, of course, and this will matter if you want a FPGA implementation packaged as a pin-compatible replacement. If you want to run the bulk of the existing code while allowing for some redesign, as your following paragraph suggests, then there are several 8086 cores available. Just replace the 80188 built-in peripherals (either on-board in the same FPGA or as external chips) >... >Plus I imagine I can throw all the UARTs, buffers and address decoding >latches into the same device and save myself a large amount of board >space. Roberto WaltmanArticle: 114285
Peter, Would your Asynchronous FIFO core handle this situation correctly given a large enough FIFO? ---Matthew Hicks "Peter Alfke" <peter@xilinx.com> wrote in message news:1168449451.035500.190590@p59g2000hsd.googlegroups.com... >I wrote a TechXclusives paper a while ago, on this exact subject: > You can click on the (ridiculously long) URL: > > http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=pa_clock_bound > > When the transmit clock is faster than the receive clock, there is of > course the danger of "overrunning" the receiver, and thus losing > data... > Peter Alfke, Xilinx > > > On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote: >> Signal can change on each rising edge or less often. >> >> "John_H" <newsgr...@johnhandwork.com> wrote in >> messagenews:12qa3g2otrg95e1@corp.supernews.com... >> >> > How often does the signal change relative to the two clocks? >> >> > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message >> >news:eo30bh$c3j$1@cernne03.cern.ch... >> >> Hi all, >> >> >> I have to transfert signals from a clock domain to another. >> >> First clock domain is fixed, but the second can be faster or slower >> >> than >> >> the first one. >> >> >> Does somebody can give me some help. >> >> >> Thanks >> >> Matthieu >Article: 114286
Pablo wrote: > Has anybody any LWIP example?. I try to connect PC and Board. I try to > send some package with tcp_write but I have errors because I can't get > it. I don't want to implement a webserver, I only want a little code to > transmit ethernet data. If you only want to transmit Ethernet frames, then you don't need LWIP. Cheers, JonArticle: 114287
Do you know what "large enough" is given the speeds of your two clock domains? If your downstream clock domain is always slower than your upstream time domain, you cannot get a FIFO large enough. If you can determine the maximum sustained upstream rate (less than or equal to the upstream clock frequency) and know the minimum sustained downstream clock frequency, you can determine the FIFO size that will guarantee a system that communicates all the information. If your output frequency isn't fast enough to keep up - ever - you're hosed from the start. Keep in mind there will be a maximum delay encountered when the FIFO reaches full. "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in message news:eo3h81$id4$1@news.ks.uiuc.edu... > Peter, > > Would your Asynchronous FIFO core handle this situation correctly given a > large enough FIFO? > > > ---Matthew Hicks > > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:1168449451.035500.190590@p59g2000hsd.googlegroups.com... >>I wrote a TechXclusives paper a while ago, on this exact subject: >> You can click on the (ridiculously long) URL: >> >> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=pa_clock_bound >> >> When the transmit clock is faster than the receive clock, there is of >> course the danger of "overrunning" the receiver, and thus losing >> data... >> Peter Alfke, Xilinx >> >> >> On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote: >>> Signal can change on each rising edge or less often. >>> >>> "John_H" <newsgr...@johnhandwork.com> wrote in >>> messagenews:12qa3g2otrg95e1@corp.supernews.com... >>> >>> > How often does the signal change relative to the two clocks? >>> >>> > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message >>> >news:eo30bh$c3j$1@cernne03.cern.ch... >>> >> Hi all, >>> >>> >> I have to transfert signals from a clock domain to another. >>> >> First clock domain is fixed, but the second can be faster or slower >>> >> than >>> >> the first one. >>> >>> >> Does somebody can give me some help. >>> >>> >> Thanks >>> >> Matthieu >> > >Article: 114288
I have read the data sheet and it seems that it should be able to be set but I don't know how. Do you do it the HDL code or in the port map option. I saw something called DELAY when I map the ports in xilinx ISE but it does not allow me to choose a specific time. The DCM do not have the options IBUF_DEALY_VALUE and IFD_DELAY_VALUE when I grab DCM_SP from the spartan3E library so i cannot use those or am i missing something. Thanks Amish Lars wrote: > On Jan 5, 2:17 pm, "axr0284" <axr0...@yahoo.com> wrote: > > It seems that for the spartan3E, you cannot change the delay in the > > input block. > > Amish > > > > > > > > Lars wrote: > > > axr0284 wrote: > > > > Hi I am currently working on a RGMII interface using the SPARTAN 3E > > > > FPGA. > > > > > > I have 1 clock pin (phy_rx_clk) feeding into a DCM and 2 DCM output > > > > clk0 and clk180 being used in my design. > > > > There is also an external module which I have no control over that = will > > > > be sending DDR data and clock with the data have a minimum setup ti= me > > > > of 1.4 ns and minimum hold time of 1.2 ns. > > > > > > I need to measure the setup time of the data when it reaches the fi= rst > > > > flip flop of the DDR which is found in the IOB itself. > > > > > > So I setup the constraint to have 2 ns setup time wrt the input clo= ck > > > > called phy_rx_clk > > > > Now the timing analyzer tells me that it actually needs a setup tim= e of > > > > 3.9 ns and I am wondering why it needs such a long setup time. > > > > > > Wouldn't the DCM introduce some delay in the clock line wrt to the = data > > > > line thus reducing the setup time. > > > > > > Is there anyway to decrease this setup time to what I need. > > > > > > -------------------------------------------------------------------= --------=AD--------------------------- > > > > * COMP "rgmii_rx_ctrl" OFFSET =3D IN 2 ns BEFORE COMP "phy_rx_clk" = HIGH > > > > | Requested | Actual | Logic | Absolute |Number of Levels > > > > | 2.000ns | 3.928ns | 0 | -1.928ns | 2 > > > > -------------------------------------------------------------------= --------=AD--------------------------- > > > > > > Thanks for any answer. > > > > Amish > > > > > If your timing report states a negative value for hold time (and > > > assuming that this is not needed), you can trade (at least some) if > > > this time into less setup time. > > > > > Most likley the tools have inserted some input delay in the IO block = to > > > assert a negative hold time for your input. This is normally not need= ed > > > when working with DCMs. Check IBUF_DEALY_VALUE and IFD_DELAY_VALUE in > > > the constraints guide. A quick check is to open the design in > > > FPGA-editor and have a look inside the IO block to see what values ha= ve > > > been assigned to these parameters. > > > > > /Lars- Hide quoted text -- Show quoted text - > > Yes you can! Have a look in the Spartan-3E data sheet, page 11. The > delay to the interior of the FPGA can be set to the in 250 ps > increments and the delay to the IO-block register in 500 ps increments > from 0 to aprox. 5.8 ns. >=20 > /LarsArticle: 114289
There is a project called display test on www.fpgaarcade.com originally this did exactly what you wanted using a block ram initialised with ascii bitmaps and a second ram holding the text to be displayed. It had a bus which could be attached to a state machine or microprocessor. I used it to display 16 32 bit registers on the screen. have a look, I can't remember how much code I left in. If you don't find anything else ping me and I'll try and did up the original. Away in China for the next 2 weeks however ... /MikeJ "wallge" <wallge@gmail.com> wrote in message news:1168450083.665408.153410@i56g2000hsf.googlegroups.com... >I would like to superimpose some text into a video stream coming from a > camera into my fpga. > Lets say I would like to print the values of several registers to the > screen as simple ascii text. This text would be superimposed over the > incoming video stream. Does anyone know if there exists a core, or some > free vhdl floating around somewhere to do this kind of thing? > I have seen some cores that do VGA timing generation, then insert pixel > values values from a look up table (but these dont do text from what I > can tell, and must be controlled by a microprocessor). > > The problem with these is that they dont really do what I want. Really > what I want is a function that would > convert the value of a register into say, hex or base 10 ascii text, > and then count the number of > rows/columns of video coming in, and insert black or white pixels into > the video stream as appropriate to make those characters appear > (superimposed) on the output video stream. > > Anyone have any ideas or thoughts? > > thanks. >Article: 114290
Agreed. The FIFO behavior is easy to understand. It can smoothe out the rate variations at the input and the output, until it goes either full or empty. When full, it either tells the input to stop sending, or it will "let the bucket overflow", and data gets lost. The easiest case is when the receiver is guaranteed to always be faster than the sender, or when send and receive really occur at the same frequency, but at unknown phase relationships. The telecom guys have lived with these situations for half a century... Peter Alfke, Xilinx On Jan 10, 12:44 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > Do you know what "large enough" is given the speeds of your two clock > domains? If your downstream clock domain is always slower than your > upstream time domain, you cannot get a FIFO large enough. > > If you can determine the maximum sustained upstream rate (less than or equal > to the upstream clock frequency) and know the minimum sustained downstream > clock frequency, you can determine the FIFO size that will guarantee a > system that communicates all the information. If your output frequency > isn't fast enough to keep up - ever - you're hosed from the start. > > Keep in mind there will be a maximum delay encountered when the FIFO reaches > full. > > "Matthew Hicks" <mdhic...@uiuc.edu> wrote in messagenews:eo3h81$id4$1@news.ks.uiuc.edu... > > > Peter, > > > Would your Asynchronous FIFO core handle this situation correctly given a > > large enough FIFO? > > > ---Matthew Hicks > > > "Peter Alfke" <p...@xilinx.com> wrote in message > >news:1168449451.035500.190590@p59g2000hsd.googlegroups.com... > >>I wrote a TechXclusives paper a while ago, on this exact subject: > >> You can click on the (ridiculously long) URL: > > >>http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&cate... > > >> When the transmit clock is faster than the receive clock, there is of > >> course the danger of "overrunning" the receiver, and thus losing > >> data... > >> Peter Alfke, Xilinx > > >> On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote: > >>> Signal can change on each rising edge or less often. > > >>> "John_H" <newsgr...@johnhandwork.com> wrote in > >>> messagenews:12qa3g2otrg95e1@corp.supernews.com... > > >>> > How often does the signal change relative to the two clocks? > > >>> > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message > >>> >news:eo30bh$c3j$1@cernne03.cern.ch... > >>> >> Hi all, > > >>> >> I have to transfert signals from a clock domain to another. > >>> >> First clock domain is fixed, but the second can be faster or slower > >>> >> than > >>> >> the first one. > > >>> >> Does somebody can give me some help. > > >>> >> Thanks > >>> >> MatthieuArticle: 114291
Ved wrote: > Hi all, > I have a design which has 15 blocks. > Data enters from 1st block and after 60 clocks comes out from 15th > block. > I control enabling of each block by using a counter which counts till > 60 at each clock (same clock as above). > So this counter output(say count) goes to every block and every block > has statements something like this : > > Blcok 1: > If count >=2 than > -----Do something > end if; > > Blcok 2: > If count >=4 than > -----Do something > end if; > > Blcok 3: > If count >=7 than > -----Do something > end if; > > Blcok 4: > If count >=18 than > -----Do something > end if; > > ...............and so on. > > Blcok 15: > If count >=18 than > -----Do something > end if; > > > My question is that is the data going in block 1 and being processed > through all the blocks and than coming out of block 15 will be a > Multi-Cycle path ? > And why ? > > > Thanks > Ved You don't show any data flow in the pseudo code, but in general the definition of a multicycle path is when the output of a flip-flop is not sampled on the next active edge of the clock after the signal changes. This would occur for example if data that only transitions while "count" is odd is only sampled while "count" is odd. In this case there would always be 2 clock cycles for data to settle after changing before it is sampled. Also I'm not sure but do you really mean >= (greater or equal) in your comparisons? This would seem to imply you generally don't have Multi-Cycle paths, since each block could run on a number of consecutive clock cycles. HTH, GaborArticle: 114292
"Colin Hankins" <Colin.Hankins@touit.com> wrote in message news:_k9ph.42227$GH1.32497@newsfe06.phx... > "Fred" <fred@nowhere.com> wrote in message > news:45a426ef$2$27106$db0fefd9@news.zen.co.uk... >>I need to simulate a PCI-E packet stream for a design with a correctly >>formed LCRC. I've found some DLLP examples but no TLP examples. I've >>Googled for too long and come up with nothing so far. >> >> Can anyone here help? >> > Catalyst Enterprise www.getcatalyst.com has their SPX Analyzer/Exerciser > Software. With it you can construct any type of TLP packet and it will > generate the proper LCRC. > Many thanks for your post. However all I need is an example and, whilst I haven't checked, I assume this software doesn't come cheap.Article: 114293
Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use inertial delays, so if you have an assignment such as this: assign #4 sig_out = sig_in; then any pulse on sig_in that is less than 4ns will get swallowed. Modeling transport delays prevents this from happening. Modelsim claims to model transport delays using the +transport_int_delay option for vsim, but this just doesn't seems to work. -KevinArticle: 114294
> Many thanks for your post. However all I need is an example and, whilst I > haven't checked, I assume this software doesn't come cheap. The packet generation portion was free to use about eight months ago. Here is a 32-bit addr memory read request packet, seq #0, length 1, from address xA0000000 0000 0000 0001 0000 000F A000 0000 LCRC 50E3 FB09 Hope this helps.Article: 114295
As John stated, make sure you do the analysis and assure yourself you can use a FIFO, and if so, that it is large enough. We ran into the very problem--transmit clock faster than recieve clock--and our FIFO wasn't big enough--ooops! Furthermore, it was an ASIC--double oops!! The solution was to force the transmitter to use a slightly lower clock. We weren't off by much, less than 1%, but it was enough at times to cause problems. Had we not been able to slow the transmitter we would have been screwed!! "John_H" <newsgroup@johnhandwork.com> wrote in message news:12qak264aekr04b@corp.supernews.com... > Do you know what "large enough" is given the speeds of your two clock > domains? If your downstream clock domain is always slower than your > upstream time domain, you cannot get a FIFO large enough. > > If you can determine the maximum sustained upstream rate (less than or > equal to the upstream clock frequency) and know the minimum sustained > downstream clock frequency, you can determine the FIFO size that will > guarantee a system that communicates all the information. If your output > frequency isn't fast enough to keep up - ever - you're hosed from the > start. > > Keep in mind there will be a maximum delay encountered when the FIFO > reaches full. > > > > "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in message > news:eo3h81$id4$1@news.ks.uiuc.edu... >> Peter, >> >> Would your Asynchronous FIFO core handle this situation correctly given a >> large enough FIFO? >> >> >> ---Matthew Hicks >> >> >> "Peter Alfke" <peter@xilinx.com> wrote in message >> news:1168449451.035500.190590@p59g2000hsd.googlegroups.com... >>>I wrote a TechXclusives paper a while ago, on this exact subject: >>> You can click on the (ridiculously long) URL: >>> >>> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=pa_clock_bound >>> >>> When the transmit clock is faster than the receive clock, there is of >>> course the danger of "overrunning" the receiver, and thus losing >>> data... >>> Peter Alfke, Xilinx >>> >>> >>> On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote: >>>> Signal can change on each rising edge or less often. >>>> >>>> "John_H" <newsgr...@johnhandwork.com> wrote in >>>> messagenews:12qa3g2otrg95e1@corp.supernews.com... >>>> >>>> > How often does the signal change relative to the two clocks? >>>> >>>> > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message >>>> >news:eo30bh$c3j$1@cernne03.cern.ch... >>>> >> Hi all, >>>> >>>> >> I have to transfert signals from a clock domain to another. >>>> >> First clock domain is fixed, but the second can be faster or slower >>>> >> than >>>> >> the first one. >>>> >>>> >> Does somebody can give me some help. >>>> >>>> >> Thanks >>>> >> Matthieu >>> >> >> > >Article: 114296
AVNET's website. All you have to do is register with them and you can have access to the schematics and BOM. I'm surprised you kit didn't include a CD with this information. http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D25927%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html "Matthieu Cattin" <matthieu.cattin@cern.ch> wrote in message news:eo30k0$can$1@cernne03.cern.ch... > Hi, > > I just buy a P160 analog module from Memec Design and I'd like to know the > type of the 7 analog connectors. > Because I've never seen this kind of connectors. > > Thanks. > Matthieu >Article: 114297
hi looks like the 40 pin connector on the max II development kit is IDE ATA pin compatable, but is LVTTL or LVCMOS signal levels capable of interfacing to a modern harddisk? does it depend on the manufacturer or can the disk drive be run at a lower voltage 3.3V for example? it would be nice to make a simple HD interface, so any help would be good. cheers.Article: 114298
One solution is to have the transmitter include padding, extra bits or words that the receiver recognizes and can, if necessary, "throw away" = skip over. That way, the receiver does not need a back communication to the transmitter. The price is of course a loss of throughput. There is no free lunch. Peter Alfke On Jan 10, 7:18 pm, "Rob" <robns...@frontiernet.net> wrote: > As John stated, make sure you do the analysis and assure yourself you can > use a FIFO, and if so, that it is large enough. We ran into the very > problem--transmit clock faster than recieve clock--and our FIFO wasn't big > enough--ooops! Furthermore, it was an ASIC--double oops!! The solution was > to force the transmitter to use a slightly lower clock. We weren't off by > much, less than 1%, but it was enough at times to cause problems. Had we > not been able to slow the transmitter we would have been screwed!! > > "John_H" <newsgr...@johnhandwork.com> wrote in messagenews:12qak264aekr04b@corp.supernews.com... > > > Do you know what "large enough" is given the speeds of your two clock > > domains? If your downstream clock domain is always slower than your > > upstream time domain, you cannot get a FIFO large enough. > > > If you can determine the maximum sustained upstream rate (less than or > > equal to the upstream clock frequency) and know the minimum sustained > > downstream clock frequency, you can determine the FIFO size that will > > guarantee a system that communicates all the information. If your output > > frequency isn't fast enough to keep up - ever - you're hosed from the > > start. > > > Keep in mind there will be a maximum delay encountered when the FIFO > > reaches full. > > > "Matthew Hicks" <mdhic...@uiuc.edu> wrote in message > >news:eo3h81$id4$1@news.ks.uiuc.edu... > >> Peter, > > >> Would your Asynchronous FIFO core handle this situation correctly given a > >> large enough FIFO? > > >> ---Matthew Hicks > > >> "Peter Alfke" <p...@xilinx.com> wrote in message > >>news:1168449451.035500.190590@p59g2000hsd.googlegroups.com... > >>>I wrote a TechXclusives paper a while ago, on this exact subject: > >>> You can click on the (ridiculously long) URL: > > >>>http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&cate... > > >>> When the transmit clock is faster than the receive clock, there is of > >>> course the danger of "overrunning" the receiver, and thus losing > >>> data... > >>> Peter Alfke, Xilinx > > >>> On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote: > >>>> Signal can change on each rising edge or less often. > > >>>> "John_H" <newsgr...@johnhandwork.com> wrote in > >>>> messagenews:12qa3g2otrg95e1@corp.supernews.com... > > >>>> > How often does the signal change relative to the two clocks? > > >>>> > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message > >>>> >news:eo30bh$c3j$1@cernne03.cern.ch... > >>>> >> Hi all, > > >>>> >> I have to transfert signals from a clock domain to another. > >>>> >> First clock domain is fixed, but the second can be faster or slower > >>>> >> than > >>>> >> the first one. > > >>>> >> Does somebody can give me some help. > > >>>> >> Thanks > >>>> >> MatthieuArticle: 114299
hi will a simple undolder and remounting at 90 degrees give an angled display or is super glue holding the thing in place :( is the opening in the bezzel on the right of the display for led backlighting, and what colour and ampage are needed if this is so. this info is needed to go for a 1U 19in rackmount case for eventual product. how would i order many dev kits (if used) without the blaster cable and cds if this is a good production option? cheers
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