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Messages from 11575

Article: 11575
Subject: Re: New Evolutionary Electronics Book
From: John Woodgate <jmw@jmwa.demon.co.uk>
Date: Tue, 25 Aug 1998 07:10:59 +0100
Links: << >>  << T >>  << A >>
In article <35e18082.1903959@news.gv.net>, Jim Weir <jim@rst-engr.com>
writes
>
>->Summary
>->^^^^^^^
>->In reconfigurable hardware, the behaviours and interconnections of the
>->constituent electronic primitives can be repeatedly changed. Artificial
>->evolution can automatically derive a configuration causing the system to
>->exhibit a pre-specified desired behaviour. A circuit's evolutionary 
>
>Oh BOY.  If the summary is this readable, I just can't WAIT to curl up with
>this sucker some cold evening when I can't sleep.  {;-)
>
>Jim

Yes. I want to know whether this evolution proceeds only by random
mutations or has electronic sex been developed?
-- 
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. 
OOO - Own Opinions Only. You can fool all of the people some of the time, but 
you can't please some of the people any of the time.
Article: 11576
Subject: Re: professional autorouters
From: marjan@vom.com (AbdulraHman Lomax)
Date: Tue, 25 Aug 1998 06:52:23 GMT
Links: << >>  << T >>  << A >>
"K. Tyler" <tylereng@pacbell.net> wrote:

>AbdulraHman Lomax wrote:
>
>> I've spent a *lot* more money on routers and gotten much worse than
>> Route 98. Yes, it may not do blind vias (I haven't actually checked.)
>> But, then again, I've never used a blind via and don't plan to in the
>> near future: why raise my customers fab cost?
>>
>> AbdulraHman Lomax
>
>  Are you saying Blind vias or intended to say Buried vias ?
>
>K.Tyler

That's easy to answer. Both, but I only mentioned one. Some, but not
necessarily all, of my comments apply to both. Because of layer setup,
there may be a difference between blind and buried vias in terms of
cost and practicality, but, as I said, I haven't used them (either of
them, to be clear), so don't ask *me*.



AbdulraHman Lomax
marjan@vom.com
P.O. Box 423
Sonoma, CA 95476
USA
Article: 11577
Subject: ZSA
From: Joni Dambre <jdambre@elis.rug.ac.be>
Date: Tue, 25 Aug 1998 10:00:57 +0200
Links: << >>  << T >>  << A >>
Hi all,

does anyone know where I might find an implementation of the
ZSA-algorithm (in C or C++)?
It is not meant for commercial purposes, only for my PhD-research.

Thanks,

Joni
-- 
Department of Electronics and Information Systems,
Faculty of Applied Sciences, University of Ghent,  
St. Pietersnieuwstraat 41,               
B-9000 Ghent, Belgium                 99999  
work phone: +32-9-264.34.09          9 o - 9   
email: jdambre@elis.rug.ac.be        9  |  9     
                                       \_/
Article: 11578
Subject: Re: Paul Donachs Thesis
From: dburns <donallb@webforia.com>
Date: Tue, 25 Aug 1998 09:05:41 +0100
Links: << >>  << T >>  << A >>




Cm Heong wrote:

> Anyone knows how I can get a copy of Paul Donach's PhD thesis?
>
> The 1996 URL  posted here http://www.cs.qub.ac.uk/~P.Donachy/thesis/  no
> longer works.

Cm Heong, I just checked that link and it seems to work just dandy!!

Donall

Article: 11579
Subject: Re: PROM alternative
From: david.storrar@gecm.SPAMMENOT.com (Dave Storrar)
Date: Tue, 25 Aug 1998 09:31:30 GMT
Links: << >>  << T >>  << A >>
On Tue, 25 Aug 1998 03:01:01 GMT, jcvilleneuve@hotmail.com wrote:

>
>
>Hello there!!!
>
>Is anybody has used something else than a PROM for the configuration cycle of
>their FPGA (example direct CPU to fpga)?
>

I've configured a Lucent ORCA device from a microcontroller.  It was
pretty simple using the "Asynchronous Peripheral" configuration mode -
the FPGA just looks like another memory location.  I think the Xilinx
parts have a similar configuration mode.

No particular problems with the bitstream format either.  Could handle
tool generated PROM file stored in ROM.  I also included the facility
to transfer the bitstream via a serial link to the micro, which wrote
the bytes to the FPGA.  Bitstream data came from an ASCII file,
generated by the ORCA tools, containing the '1's and '0's. (They
called it a "rawbit" file.

Hope this helps.

Dave.

-- 
REMOVE "spammenot." in address to reply
Dave Storrar
Development Engineer    | e-mail: david.storrar@gecm.com
GEC-Marconi Avionics    | Tel: +44 (0)131 343 4484
RCS                     | Fax: +44 (0)131 343 4091

Article: 11580
Subject: FPGA vendors
From: "Reza Bohrani" <Reza.Bohrani@timespace.se>
Date: Tue, 25 Aug 1998 13:45:31 +0200
Links: << >>  << T >>  << A >>
I am new to to world of FPGA and would like to now which vendor to choose.
We have Actel, Altera, Xilinx, Lucent ... and many more. Can anyone please
tell me which one is the cheapest, the "best"?
Sincerely
Reza


Article: 11581
Subject: SYNTHESIS TOOLS
From: "Reza Bohrani" <Reza.Bohrani@timespace.se>
Date: Tue, 25 Aug 1998 13:47:57 +0200
Links: << >>  << T >>  << A >>
Which pc-based synthesis tool is the best on the market. I have heard of
Synplify; is that a good tool or should I go for Leonardo or are there other
good tools?


Article: 11582
Subject: Re: Porn spamming
From: Guenter Strubinsky <gxstrubi@essvote.com>
Date: Tue, 25 Aug 1998 10:18:00 -0500
Links: << >>  << T >>  << A >>
Why no valid return adress ???

If sending them 10.000 messages that we aren't interesated in their services, do
you think they will sue  -U-S-  for spamming?

Don't forget that the 'normal' reaction of many of us is to reply with some
nasty remarks or not at all. These 'businesspersons' (politically correct ;) )
don't READ the mail. It's just good for OUR soul to bother writing them our
opinion. The problem they get is the MASS of data they receive from us. It makes
providers cranky! Don't worry that they bother writing back 2 U.

guenter


ro wrote:

> do you know how to create a batch file in win95 to flood their email without
> having the return e-mail address on the message?
>
> ac@cd.com wrote in message <35dabad8.7932740@news.dial.pipex.com>...
> <SNIP>

> >
> >Digital Illusions
> >590 Centerville Road Suite 288
> >Lancaster, PA 17601
> >US
> >(+1) 717 898 1443
>

Article: 11583
Subject: Re: Porn spamming
From: Guenter Strubinsky <gxstrubi@essvote.com>
Date: Tue, 25 Aug 1998 10:18:03 -0500
Links: << >>  << T >>  << A >>
Why no valid return adress ???

If sending them 10.000 messages that we aren't interesated in their services, do
you think they will sue  -U-S-  for spamming?

Don't forget that the 'normal' reaction of many of us is to reply with some
nasty remarks or not at all. These 'businesspersons' (politically correct ;) )
don't READ the mail. It's just good for OUR soul to bother writing them our
opinion. The problem they get is the MASS of data they receive from us. It makes
providers cranky! Don't worry that they bother writing back 2 U.

guenter


ro wrote:

> do you know how to create a batch file in win95 to flood their email without
> having the return e-mail address on the message?
>
> ac@cd.com wrote in message <35dabad8.7932740@news.dial.pipex.com>...
> <SNIP>

> >
> >Digital Illusions
> >590 Centerville Road Suite 288
> >Lancaster, PA 17601
> >US
> >(+1) 717 898 1443
>

Article: 11584
Subject: Re: PROM alternative
From: husby@fnal.gov (Don Husby)
Date: Tue, 25 Aug 1998 15:27:24 GMT
Links: << >>  << T >>  << A >>
 jcvilleneuve@hotmail.com wrote:
> Is anybody has used something else than a PROM for the configuration cycle of
> their FPGA (example direct CPU to fpga)?

I use a 1MHz serial link to configure remote (~7meters) FPGAs.
A 22V10 GAL is used to extract configuration bits and control FPGA reset/load.

After the FPGA is configured, the serial link becomes a bi-directional 
control/status link to read/write registers inside the FPGA.  

I have an ISA board with 8 serial links that can control 8 remote modules
at a time.

This is just a prototype for a more general control/status network
that will eventually control ~6,000 devices (FPGA, DSP) and use
USB and cheap microcontrollers for distributing and storing
configuration information.

See:
   http://www-ese.fnal.gov/eseproj/trigger/prototype/sumac.pdf
Article: 11585
Subject: Re: Porn spamming
From: Geir Harris Hedemark <geirhe@hridil.ifi.uio.no>
Date: 25 Aug 1998 18:05:44 +0200
Links: << >>  << T >>  << A >>
Guenter Strubinsky <gxstrubi@essvote.com> writes:
> bother writing them our opinion. The problem they get is the MASS of
> data they receive from us. It makes providers cranky! Don't worry that
> they bother writing back 2 U.

Two good reasons why this is a Bad Idea:

1) It is not very hard to fake addresses. Many spam mails don't have a
valid address anyway, or an address pointing to an innocent third party.

2) The provider of the jerks doing this have many other
customers. They should not suffer from misdirected attacks by clueless
persons.

There is one correct way of dealing with spam (Mail to the responsible
usenet or abuse account). If you don't know how to find which account
that is, don't try to be smart. If the amount of traffic really
bothers you, contact your local newsmaster. He should know to deal
with this.

Followup-to set to poster.

Geir

Article: 11586
Subject: Re: Newbie seeks cheap fun w/FPGAs
From: Mike Butts <mbutts@realizer.com>
Date: Tue, 25 Aug 1998 16:26:27 +0000
Links: << >>  << T >>  << A >>
Tom Burns wrote:
> 
> A reduced version of Altera's Max+Plus II software is available free for
> the downloading and it handles several parts, I believe including the FLEX
> 10K10, a 10,000+ gate SRAM-based device.  You may have to make the PCB that
> uses it, but you can download the FPGA program to it over the PC's serial
> or parallel ports.  You don't have to buy the BitBlaster or ByteBlaster
> download cables; just download the data sheet for them - you can make
> either yourself from the info in the datasheet.

Absolutely.  The Flex6K family starts at $20 in singles over the
counter at <http://www.wyle.com> and others.  They take credit cards;
it's easy.  That's the EPF6016TC144-3, which has 1300 LEs, good for
10K+ gates.  Altera's PLS-WEB 8.3 is the real stuff, not a toy, with
outstanding documentation.  You can even code in AHDL, their (pretty
basic) HDL, and synthesize into the part, with the free SW.

We just got the first couple of our little KIM-RC boards up and at
least partly tested this month.  (It's a hobby activity for me so
progress is when I get some time.)  Built a ByteBlaster clone 
according to the Altera app note, and it works fine.  Hand-soldering
the little PQFP is a trick, but even that can be done.  

We'll keep this newsgroup posted on the KIM-RC.  That's the little
board I posted about a few months ago.  We hope to make it available 
by the end of the year.  Flex6016, 1Mbit SRAM, clock, parallel and 
serial ports, motor driver, leds and buttons, extra I/Os on headers, 
voltage regulators, hook up a little power cube or batteries and you're 
running.  I'll be developing a simple 16-bit stack-based CPU and a fast 
native Forth system on it, for reconfigurable computing experiments, 
and releasing it all (HW, AHDL code & SW) under the GPL.  (In my 
copious free time! ;-)  Also thinking of a logic analyzer 
configuration, and robotics-related apps.  Hoping others get some 
boards and develop for it and share as well.

In the meantime, by all means, download some software, get a cheap 
FPGA, and start hacking.  Share and enjoy!

   --Mike
Article: 11587
Subject: Re: FPGA vendors
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 25 Aug 1998 14:16:16 -0400
Links: << >>  << T >>  << A >>


Reza Bohrani wrote:

> I am new to to world of FPGA and would like to now which vendor to choose.
> We have Actel, Altera, Xilinx, Lucent ... and many more. Can anyone please
> tell me which one is the cheapest, the "best"?
> Sincerely
> Reza

These are relative terms, especially "best".  Part prices vary depending on
what kind of deal you can get with a supplier.  Don't forget, cost also
includes the time & effort to climb the learning curve,  and any tools for
design capture, simulation, place&route and programming.  The cost for
components also should include the cost of making a programming error (one
time programmable, vs E/EPROM types that need to come off the board for
programming vs in-circuit programmables) You might sit with your distributor
for a discussion on costs.

As to best, it really depends on your application.  For a heavily arithmetic
design (ie DSP) the xilinx 4k/spartan architecture is in my opinion the hands
down winner because of the flexibility of the carry logic (which doesn't use
up LUT terms), and the ability to use the cell for RAM (makes compact delay
Queues).  If you are looking for synthesizability, the Altera 6/8/10K families
might be a better choice because the global nature of the routing resource
makes them less sensitive to good place and route.  If you want high speed
and/or lots of registers, the Atmel 6K and 40K devices may be the best
choices, as there is a higher register to logic density than other devices.
If you need non-volatility (or the usually lower price per gate of the raw
devices) then Actel or Quicklogic devices would be the likely ticket.  What it
comes down to is that any of the devices on the market are "best" depending on
your needs.  As it has been said many times before beauty is in the eye of the
beholder.  What you need to do is look at your application to determine which
features you are likely to need and make a determination as to the best fit
for your needs from there.


--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11588
Subject: Re: half full flag in a xilinx async fifo?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 25 Aug 1998 14:29:39 -0400
Links: << >>  << T >>  << A >>


Guy Gerard Lemieux wrote:

> you can also keep your read/write ptrs in Gray code
> but then you'll probably want to decode both ptrs into
> binary to do the subtract.  doing the subtraction
> in the Gray code domain involves 2 parallel carry chains
> which FPGAs are not optimized for.  i can give you
> a reference if you want one though.
>

You can get around this by using a composite counter that has a 2 bit gray code
counter for the LSBs and whatever counter is convenient for the remaining bits.
The decode is gated by the gray code counter so that it is only valid on a count
that is away from the count enable of the upper counter.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11589
Subject: Re: PROM alternative
From: berryhill@uchicago.edu (Jeff Berryhill)
Date: Tue, 25 Aug 1998 18:58:23 GMT
Links: << >>  << T >>  << A >>
In article <6rt9de$j01$1@nnrp1.dejanews.com>,
	jcvilleneuve@hotmail.com writes:
> 
> 
> Hello there!!!
> 
> Is anybody has used something else than a PROM for the
> configuration cycle of
> their FPGA (example direct CPU to fpga)?
> 
> 
> 
> Thank you, Jici
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum


We are currently designing a board, upon which resides upwards of a dozen
Altera FLEX10K FPGAs.  The board resides in a crate with VMEbus access from
a PC.  The board itself contains an Altera MAX7000 chip which coordinates
VME I/O, a large (16 Mb) FLASH memory, and an additional MAX9000
'boot chip' which emulates the configuration cycle of a FLEX 10K.  

Configuration works as follows.  Using the PC, configuration data is
written to the FLASH memory over VME.  Writing to a particular VME
address initiates a configuration cycle by the boot chip, which reads
data from the FLASH memory and writes it to the configuration data ports
of the FLEX10Ks.   For a single board, this is not very practical, but
for dozens of similar boards which are part of a much larger system, there
are advantages to having this flavor of ISP. 

Another project we are working on has both eproms and and a front panel 
connector (for use with a ByteBlaster), with a mechanical switch which
multiplexes them.  At the prototyping stage the front panel connector
is used for configuration.  Once a 'final' program is decided upon, the
program is written to the eprom, the switch is flipped, and subsequent
configuration is done with the eprom.    

Article: 11590
Subject: Re: New Evolutionary Electronics Book
From: jmccarty@sun1307.spd.dsccc.com (Mike McCarty)
Date: 25 Aug 1998 22:30:24 GMT
Links: << >>  << T >>  << A >>
In article <35e18082.1903959@news.gv.net>, Jim Weir <jim@rst-engr.com> wrote:
)
)->Summary
)->^^^^^^^
)->In reconfigurable hardware, the behaviours and interconnections of the
)->constituent electronic primitives can be repeatedly changed. Artificial
)->evolution can automatically derive a configuration causing the system to
)->exhibit a pre-specified desired behaviour. A circuit's evolutionary 
)
)Oh BOY.  If the summary is this readable, I just can't WAIT to curl up with
)this sucker some cold evening when I can't sleep.  {;-)
)
)Jim


Let me translate this little bit into English.

	Hardware which can be changed can be changed more than once. It
	is sometimes possible to make the hardware configure itself.

How's that?

I think the original is obfuscated bullshit. People who lack content
sometimes make up for it with obfuscation.

Mike
-- 
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for DSC.         <- They make me say that.
Article: 11591
Subject: Re: vector product minimization problem
From: "John L. Smith" <jsmith@visicom.com>
Date: Tue, 25 Aug 1998 18:48:45 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Rickman wrote:

> Stanley Chow wrote:
> >
> > In article <35DCA3C7.9A810F57@visicom.com>,
> > John L. Smith <jsmith@visicom.com> wrote:
> > >> z=x6 + x7
> > >> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
> > >>
> > >> Can you get less than 11?
> > >
> > >I don't think so Dan, add up the number of 1-bits (or 0-bits +1 if this isless) in
> > >the co-efficients, then subtract 1 (because you always start with
> > >one):
> > >
> > >coef:               1 2 3 4 5 6 7 8
> > >#of adds(or subs):  1 1 2 1 2 2 2 1  -> Total-1 = 11
> >
> > This is not a true lower bound.
> >
> > It is possible for a single addition to produce two bit, for exmaple:
> >
> >    x = a+b
> >    y = 2x + x   = 3a+3b
> >    z = 4y + y   = 15a + 15b
> >
> > In three additions, the result has 8 one-bits.
>
> Stanley,
>
> No, this is not a lower bound. Also John's calculation is wrong. He
> shows 2 bits set in the coefficient 7. It should be three bits giving a
> total of 13 bits with 12 adders. But this gives you the upper bound
> actually.

Hi Dan/Stanley/Rick,  I realized _after_ posting that what I said was
a bit off from Dan's original query. Been offline for
a few days, would like to elaborate further.
  What I meant for the coef 7 entry was that it could be
generated as +8 - 1, or 2 more addition equivalents.
I didn't explain thoroughly, just as bad as wrong I guess.

Stanley:
x = a+b
y = 16x-x = 15a + 15b,
two addition equivalents -> 8 one bits (but you know this).

To put the original problem into slightly different
notation,

Total = A + 2B + 3C + 4D + 5E + 6F + 7G + 8H

Now tabulate the additions (as Rick suggests below):

8                  H
4          D E F G
2      B C     F G
1    A   C   E   G

Now, certain patterns become evident; in this
case, symmetries can be seen:

1) 4 ... F G
   2 ... F G

2) 2 ... C ... G
   1 ... C ... G

3) 4 ... E . G
   1 ... E . G

For each of the above, it is less work
to add first 'horizontally' then do one
'vertical' addition than to perform
two vertical adds and 1 horizontal.
Unfortunately, all these symmetries
involve the G column; using any one
means not using any of the others.

So there is possible piece of a logic
reduction algorithm: Tabulate the
bits and find non-coincident symmetries.
Each one allows the removal of an adder.

Another piece (that I posted about orig.)
is to stay within a single column,
where any coef spanning N powers of 2
can be implemented in at most 1 + N/2
additional adders and/or subtractors.
Repeating patterns allow reduction
to O(logN), see earlier post on fixed
division to get the idea there.

>
>
> In order to use fewer adders, you need to take advantage of common bits
> in the coefficients. The above exaple takes advantage of the 2 and the 4
> bits common to both the 6 and the 7 coefficients. This is shown in the
> expression z = x6 + x7. This allows the result of this addition to be
> used in two places from the original expression eliminating one adder.
>
> That is also what you have shown in your example where you have
> eliminated 4 adders by using this process twice.
>
> I think that you can see this by expressing each product as a sum of the
> products of the binary coefficients and the variable. Then find an
> optimal grouping of coefficients that eliminates additions. Of course
> this is not an algorithm. But I think this is the mathmatical basis for
> finding one. You need to search this space for optimal groupings.
>
> --
>
> Rick Collins
>
> redsp@XYusa.net
>
> remove the XY to email me.



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<HTML>


<P>Rickman wrote:
<BLOCKQUOTE TYPE=CITE>Stanley Chow wrote:
<BR>>
<BR>> In article &lt;35DCA3C7.9A810F57@visicom.com>,
<BR>> John L. Smith &lt;jsmith@visicom.com> wrote:
<BR>> >> z=x6 + x7
<BR>> >> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
<BR>> >>
<BR>> >> Can you get less than 11?
<BR>> >
<BR>> >I don't think so Dan, add up the number of 1-bits (or 0-bits +1
if this isless) in
<BR>> >the co-efficients, then subtract 1 (because you always start with
<BR>> >one):
<BR>> >
<BR>> >coef:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
1 2 3 4 5 6 7 8
<BR>> >#of adds(or subs):&nbsp; 1 1 2 1 2 2 2 1&nbsp; -> Total-1 = 11
<BR>>
<BR>> This is not a true lower bound.
<BR>>
<BR>> It is possible for a single addition to produce two bit, for exmaple:
<BR>>
<BR>>&nbsp;&nbsp;&nbsp; x = a+b
<BR>>&nbsp;&nbsp;&nbsp; y = 2x + x&nbsp;&nbsp; = 3a+3b
<BR>>&nbsp;&nbsp;&nbsp; z = 4y + y&nbsp;&nbsp; = 15a + 15b
<BR>>
<BR>> In three additions, the result has 8 one-bits.

<P>Stanley,

<P>No, this is not a lower bound. Also John's calculation is wrong. He
<BR>shows 2 bits set in the coefficient 7. It should be three bits giving
a
<BR>total of 13 bits with 12 adders. But this gives you the upper bound
<BR>actually.</BLOCKQUOTE>
<TT>Hi Dan/Stanley/Rick,</TT><TT>&nbsp; I realized _after_ posting that
what I said was</TT>
<BR><TT>a bit off from Dan's original query. Been offline for</TT>
<BR><TT>a few days, would like to elaborate further.</TT>
<BR><TT>&nbsp; What I meant for the coef 7 entry was that it could be</TT>
<BR><TT>generated as +8 - 1, or 2 more addition equivalents.</TT>
<BR><TT>I didn't explain thoroughly, just as bad as wrong I guess.</TT><TT></TT>

<P><TT>Stanley:</TT>
<BR><TT>x = a+b</TT>
<BR><TT>y = 16x-x = 15a + 15b,</TT>
<BR><TT>two addition equivalents -> 8 one bits (but you know this).</TT><TT></TT>

<P><TT>To put the original problem into slightly different</TT>
<BR><TT>notation,</TT><TT></TT>

<P><TT>Total = A + 2B + 3C + 4D + 5E + 6F + 7G + 8H</TT><TT></TT>

<P><TT>Now tabulate the additions (as Rick suggests below):</TT><TT></TT>

<P><TT>8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
H</TT>
<BR><TT>4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; D E F G</TT>
<BR><TT>2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; B C&nbsp;&nbsp;&nbsp;&nbsp; F G</TT>
<BR><TT>1&nbsp;&nbsp;&nbsp; A&nbsp;&nbsp; C&nbsp;&nbsp; E&nbsp;&nbsp; G</TT><TT></TT>

<P><TT>Now, certain patterns become evident; in this</TT>
<BR><TT>case, symmetries can be seen:</TT><TT></TT>

<P><TT>1) 4 ... F G</TT>
<BR><TT>&nbsp;&nbsp; 2 ... F G</TT><TT></TT>

<P><TT>2) 2 ... C ... G</TT>
<BR><TT>&nbsp;&nbsp; 1 ... C ... G</TT><TT></TT>

<P><TT>3) 4 ... E . G</TT>
<BR><TT>&nbsp;&nbsp; 1 ... E . G</TT><TT></TT>

<P><TT>For each of the above, it is less work</TT>
<BR><TT>to add first 'horizontally' then do one</TT>
<BR><TT>'vertical' addition than to perform</TT>
<BR><TT>two vertical adds and 1 horizontal.</TT>
<BR><TT>Unfortunately, all these symmetries</TT>
<BR><TT>involve the G column; using any one</TT>
<BR><TT>means not using any of the others.</TT><TT></TT>

<P><TT>So there is possible piece of a logic</TT>
<BR><TT>reduction algorithm: Tabulate the</TT>
<BR><TT>bits and find non-coincident symmetries.</TT>
<BR><TT>Each one allows the removal of an adder.</TT><TT></TT>

<P><TT>Another piece (that I posted about orig.)</TT>
<BR><TT>is to stay within a single column,</TT>
<BR><TT>where any coef spanning N powers of 2</TT>
<BR><TT>can be implemented in at most 1 + N/2</TT>
<BR><TT>additional adders and/or subtractors.</TT>
<BR><TT>Repeating patterns allow reduction</TT>
<BR><TT>to O(logN), see earlier post on fixed</TT>
<BR><TT>division to get the idea there.</TT>
<BLOCKQUOTE TYPE=CITE>&nbsp;

<P>In order to use fewer adders, you need to take advantage of common bits
<BR>in the coefficients. The above exaple takes advantage of the 2 and
the 4
<BR>bits common to both the 6 and the 7 coefficients. This is shown in
the
<BR>expression z = x6 + x7. This allows the result of this addition to
be
<BR>used in two places from the original expression eliminating one adder.

<P>That is also what you have shown in your example where you have
<BR>eliminated 4 adders by using this process twice.

<P>I think that you can see this by expressing each product as a sum of
the
<BR>products of the binary coefficients and the variable. Then find an
<BR>optimal grouping of coefficients that eliminates additions. Of course
<BR>this is not an algorithm. But I think this is the mathmatical basis
for
<BR>finding one. You need to search this space for optimal groupings.

<P>--

<P>Rick Collins

<P>redsp@XYusa.net

<P>remove the XY to email me.</BLOCKQUOTE>
&nbsp;</HTML>

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Article: 11592
Subject: Re: New Evolutionary Electronics Book
From: Tom Kean <tom@algotronix.com>
Date: Wed, 26 Aug 1998 01:29:17 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------EE8C6153CCE60DDFD44307D9
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Mike McCarty wrote:

> In article <35e18082.1903959@news.gv.net>, Jim Weir <jim@rst-engr.com> wrote:
> )
> )->Summary
> )->^^^^^^^
> )->In reconfigurable hardware, the behaviours and interconnections of the
> )->constituent electronic primitives can be repeatedly changed. Artificial
> )->evolution can automatically derive a configuration causing the system to
> )->exhibit a pre-specified desired behaviour. A circuit's evolutionary
> )
> )Oh BOY.  If the summary is this readable, I just can't WAIT to curl up with
> )this sucker some cold evening when I can't sleep.  {;-)
> )
> )Jim
>
> Let me translate this little bit into English.
>
>         Hardware which can be changed can be changed more than once. It
>         is sometimes possible to make the hardware configure itself.
>
> How's that?
>
> I think the original is obfuscated bullshit. People who lack content
> sometimes make up for it with obfuscation.
>

<FLAME>Actually, its not 'obfuscated bullshit' its precise scientific english: you
just have
to turn off the TV, put down your beer and engage your brain before reading it.

For example:

'Hardware that can be changed can be changed more than once' FALSE
what about fuse technologies?  The original text does not make this claim.

'It is sometimes possible to make the hardware configure itself'  The text does
not say this either - what it says is that a configuration can be derived from
artificial evolution.  The method of downloading the configuration is not
specified.
</FLAME>

Tom.


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Article: 11593
Subject: test - ignore
From: "E. Kappos" <YZ@ntu.edu.sg>
Date: 26 Aug 1998 02:16:33 GMT
Links: << >>  << T >>  << A >>
test
Article: 11594
Subject: Re: Paul Donachs Thesis
From: Cm Heong <r24558@email.sps.mot.com>
Date: Wed, 26 Aug 1998 10:22:52 +0800
Links: << >>  << T >>  << A >>
The URL works now, but I am not able to download files.

Paul Donachy has responded through email that their server is being
updated and should be done sometime September.

A big thank-you to everyone who has responded to my post.

Cheers,
C M Heong

Article: 11595
Subject: Re: SYNTHESIS TOOLS
From: Scott Campbell <sjcampbe@earthlink.net>
Date: Tue, 25 Aug 1998 21:17:09 -0700
Links: << >>  << T >>  << A >>
I am not sure what tool is the BEST on the market, but I have Xilinx's
Foundation series 1.4 software. It includes Synopsys' FPGA express for synthesis
as well as a HDL entry ( VHDL/Verilog/ABEL ), and schematic entry tools. I
believe that the student version ( schematic / ABEL entry ) is only $100, and
will soon be upgradable to VHDL/Verilog for free in their 1.5 release coming
soon. Of course the student version is limited to synthesis of Xilinx parts less
than 10,000 gates, but I believe the (1.5) upgrade will include larger device
size and support for Altera and Lucent parts. Check out their web page
http://www.xilinx.com Hope this helps.

Scott Campbell
sjcampbe@ece.ucdavis.edu
University of California Davis

Reza Bohrani wrote:

> Which pc-based synthesis tool is the best on the market. I have heard of
> Synplify; is that a good tool or should I go for Leonardo or are there other
> good tools?



Article: 11596
Subject: Image processing Algorithms using Altera HDL
From: ali Benkhalil <akbenkha@bradford.ac.uk>
Date: Tue, 25 Aug 1998 22:50:32 -0700
Links: << >>  << T >>  << A >>
Hi All,,

does anyone know where I might find an implementation of the image
processing or
computer vision algorithm (motion detection) in AHDL (Altera HDL) ?
It is not meant for commercial purposes, only for my PhD-research and
out of Altare Home Page.


Thanks,

Ali,



Article: 11597
Subject: How to design a PLL
From: Justen <justen@studm.hrz.uni-siegen.de>
Date: Wed, 26 Aug 1998 08:17:48 +0200
Links: << >>  << T >>  << A >>
Hi,

I would like to build a digital PLL with a XILINX 4010 FPGA. The
generated frequency should be 9.5MHz to 10MHz in steps of 1kHz. So I
have to use a 1kHz Referenz (this is also the frequenzy of the
PhaseDetector) and multiply it with 9.500 to 10.000. At the moment, I
use a PhaseDetector von Xilinx AppNote and an Integrator to close the
loop. But this isn't a good design. The PhaseJitter is to big. Could
anybody help me to improve this design?

Thanks Detlef

------------------------------------------------------------------
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Center for Sensor Systems (ZESS)     __|   __|     __|    __|
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E-Mail:     justen@zess.uni-siegen.de
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----------------------------------------------------------------


Article: 11598
Subject: Re: New Evolutionary Electronics Book
From: John Woodgate <jmw@jmwa.demon.co.uk>
Date: Wed, 26 Aug 1998 07:53:46 +0100
Links: << >>  << T >>  << A >>
In article <35E356DD.4CB89744@algotronix.com>, Tom Kean
<tom@algotronix.com> writes
>Actually, its not 'obfuscated bullshit' its precise scientific english:
No, it's not. It may not be BS, but it is certainly obfuscated, and that
makes it read like an offering from a green-ink merchant. Certainly, I
was initially misled.

What you call 'precise scientific English' is no good if the readers
(even skilled ones) cannot interpret it correctly.
-- 
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. 
OOO - Own Opinions Only. You can fool all of the people some of the time, but 
you can't please some of the people any of the time.
Article: 11599
Subject: Re: professional autorouters
From: simon@actrix.void.gen.nz (Simon Peacock)
Date: 25 Aug 1998 19:13:54 -1200
Links: << >>  << T >>  << A >>
In message <35e1e00e.18316240@news.vom.com> - marjan@vom.com (AbdulraHman
Lomax) writes:
:>
:>"Chr. Moecking" <uCon_electronics@csi.com> wrote:
:>
:>>Hi Michael,
:>>
:>>you wrote:
:>>>My question is: What autorouter do you use and recommend? Should we
:>>>switch to a totally different environment
:>>>with integrated placer and autorouter or is there a really good
:>>>autorouter which can read our Protel design files?
:>>
:>>I've never found a better autorouter than my brain and my hands, so
:>>you better make it manually.
:>
:>Non sequitur. Yes, human beings are very good at routing, or at least
:>they *can* be. However, sometimes a job simply does not require the
:>level of optimization that a human being can apply; in these cases an
:>autorouter can be very useful. So what if there are a few more vias:
:>vias are cheap, and unless production quantities are high, vias are
:>cheaper, much cheaper, than human labor. Now, if via count *does*
:>matter, or really good minimization of trace lengths, then manual
:>routing may, indeed, be better.
:>
:>The Protel 98 router, from what I have seen, is very good indeed. Not
:>as good as I am, but I do not expect all of my assistants to be as
:>good at PC design as I am. And the router is *much* faster than me....
:>
:>I've spent a *lot* more money on routers and gotten much worse than
:>Route 98. Yes, it may not do blind vias (I haven't actually checked.)
:>But, then again, I've never used a blind via and don't plan to in the
:>near future: why raise my customers fab cost?
:>
:>Of course, there are jobs where they are really useful, I am sure. I
:>just don't see them in general commercial work. Protel 98 supports
:>blind vias even if the autorouter doesn't.


The real question here is not is there a good autorouter but is there a good
autorouter within your price range..   I'm sure that if you have the money you
could buy one which will work and be mind bogling.. once you've programed all
the rules..  I'm sure that the PC you work on was autorouted.. by a $100k+
autorouter..

but Spectra isn't too bad.. if you've got a spair 60k

Remember Just remove the VOID

--
StarLite Design                Phone mobile: +64 25 40 2963 
Simon Peacock                          Home: +64 4 388 8964
simon@actrix.void.gen.nz                Fax: +64 4 388 8964
Address: P.O. Box 15-143 Miramar, Wellington, NEW ZEALAND




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