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Himlam8484 schrieb:
> Hi,
>
> First, thank you very much for your idea. I got some interestings
> thing from you. I have just come back my work from long holiday in my
> country.
> I compile 2 example file. Example_Sqrt is ok, But i have problems with
> fibonacci file. when i compile file fibo.psm
> i have the following screen:
>
> 01E LOAD ZH, 00
> 01F SUB YL, 01
> 020 STORE ZL, (YL)
> 021 FETCH ZL, _N
> 022 SUB YL, 01
> 023 STORE ZL, (YL)
> 024 CALL _outchar
> 025 ADD YL, 02
> 026 ; Fibonacci_result=Fibonacci(N); // calculate fibonacci of N
> 026 FETCH ZL, _N
> 027 SUB YL, 01
> 028 STORE ZL, (YL)
> 029 CALL _Fibonacci
>
> ERROR - Address is not 3-digits: _Fibonacci
>
> Provide a correct absolute address in range 000 to 3FF or
> a matching line label. Note that labels are case sensitive.
>
> Please correct and try again.
>
> KCPSM3 complete.
>
> Can you show me clearly again!
>
> I know, my questions may be stupid. But i think" wanting to know must
> to ask"
>
> please help me,
>
> Him Lam
>
Hi Him,
the fibo.psm assembles without errors on my machine.
maybe you have put the #endif in the wrong line?
Here is the version of fibonacci.c I used:
////////////////////////////////////////////////////////////////
// KCPSM3 ONLY
// HOW EASY IS TO BE AN FPGA DESIGNER !!!
#define use_scr_ram
////////////////////////////////////////
// spartan3.h is a library that must be used if yoy want to use
scracthpad memory
//
#ifdef use_scr_ram
#include "spartan3.h"
#endif
//
//
//#define ONE
#define TWO
//#define THREE
// Fibonacci example
// the sequence of Fibonacci is:
//
//1 1 2 3 5 8 13 21 34 55 89 144 233 377 610 987 1597 etc.
char N;
char Fibonacci_result;
char i,ii,Last;
char Next,Answer;
char Fibonacci(char N);
void main(){
// char Next,Answer;
#ifdef use_scr_ram
N = inchar(0); // read N from IO addr.0
outchar(0xaa,N); // test
Fibonacci_result=Fibonacci(N); // calculate fibonacci of N
outchar(0,Fibonacci_result); // write Fibonacci(N) at address 0
// the next loop calculta Fib(2) and write in 2, then calculate Fib(3)
and write in 3, etc.
for (ii=2; ii<=12;ii++){
// Fibonacci_result=Fibonacci(ii);
outchar(i,Fibonacci(ii));
}
#endif
#ifndef use_scr_ram
#asm
// N = inchar(N);
INPUT TMP, 00
STORE TMP,_N
// outchar(0xaa,N);
#endasm
#asm
loop: JUMP loop
#endasm
#endif
}
//
char Fibonacci( char N){
Last = 1;
Next = 1;
#ifdef ONE
for( i = 2; i <= N; i++ )
{
Answer = Last + Next;
Next = Last;
Last = Answer;
}
#endif
#ifdef TWO
i =2;
while(i<=N){
i++;
Answer = Last + Next;
Next = Last;
Last = Answer;
}
#endif
#ifdef THREE
i = 2;
do{
i++;
Answer = Last + Next;
Next = Last;
Last = Answer;
}
while (i<=N);
#endif
return Answer;
}
have a nice compilation
Eilert
Article: 115976normally you wont have specified any time constraints on the reset signal... I aam assuming you have a global asynchronous reset. To correctly manage the reset you should try to synchronise it to the internal clock using a couple of flip-flops. This way it ensures a synchronous release of the reset that can be treated and analysed in the same way as any other. I think you may still get the warnings for violations of the first asynchronous input. Anyways, the idea of synchronous vs asynchronous reset is a long discussion =) Ben "skyworld" <chenyong20000@gmail.com> wrote in message news:1172557239.722343.245410@p10g2000cwp.googlegroups.com... > Hi, > I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I > checked the timing report. Everything is ok, and there is no timing > violations. But when I run post simulation, the modelsim reports some > timing errors for some registers with $recovery(...). I checked the > time when these errors occur. They happened to be the time when reset > is de-assertion. I tried to change reset period, but this time other > register report $recovery/$setup/$hold errors. It is very strange > because I have passed P&R, there is no timing violations, why does > these errors orrur? Can anybody help me? thanks very much. >Article: 115977
On 26 f=E9v, 08:47, Steve Battazzo <thesteveman_i...@yahoo.co.jp> wrote: > I found some page online in french that actually came out somewhat > readable when translated to English, describing how to install version > 8.1i in Ubuntu 6.06 (which is what I'm using). I wrote a french article on this topic, so if the mentionned page is this one : "Installation Xilinx Webpack 8.1i sur linux (ubuntu 6.06 "dapper drake")" http://harded.free.fr/site/?p=3D55 Then I am probably the one to blame for the choice of french language instead of common english :) I don't know how the "automatic" translated version is, but if you have specific questions I can write some "non automatic" human explanations :) > I tried that, but only > got checksum errors when I tried to run the .sh file. > Any ideas? This is maybe now solved, and you have probably take care of that... but just in case... Did you check you really have enough free disk space for the downloaded file ? I got the same kind of error because my disk partition get full before the end of the download. Hope this help. Luzerne GANHIRArticle: 115978
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> wrote: > On Feb 26, 10:12 am, "Antti" <Antti.Luk...@xilant.com> wrote: > > finally announced! > > > > so now can talk about them - well still not documents on Xilinx > > website, but hopefully they will be available shortly > > > > Antti > I am pleased to announce that the Spartan-3AN FPGA family is now > officially out in the open. Full technical literature is now > available on the Xilinx web site. > Spartan-3AN Non-Volatile FPGA Family > http://www.xilinx.com/spartan3an Can I bring up the issue of the bigger devices in PQ208 packages again? Even so the PQ208 has not the maximum of IO pins available, and for fast I/O intense applications simultanious switching problems may be more visible, PQ208 has heavy advantages for prototyping and so may lead to more design wins: - relaxed PCB design rules for lower cost prototype boards - heavily relaxed solder requirements and post-solder control requirements - accessability of all pins for (scope) debugging. B.t.w.: the design win may not lead to high demand on the PQ parts itself, as for mass manufacturing BGA package advantage may apply and the package may be switched. Otherwise congratulations to the new family member! Cheers -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115979
aiiadict@gmail.com wrote: > can it be done? > where do I look for information? Where did you look already? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115980
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> wrote: ... > Hi Uwe, > Thanks for bringing this to our attention. I've passed this on to our > distribution manager and he's working to remedy the situation. Both > the XC3S400 and the XC3S500E FPGAs are most definitely available. The > working theory is that the PQ208 package option is not the highest > running product combinations. Consequently, our distributors aren't > stocking them. I fully understand the attraction of the QFP package, > however. As explained in the XC3SAN thread, the availability of big PQ208 parts may not lead itself to big demand on the "many-pin" PQ parts. But the ease of prototyping may lead to more design wins and so for demand for "not-so-many" PQ and for BGA parts... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115981
Hey all. I dont know whats happened my Modelsim but anytime I try and do anything with it like open/close/create a project I get this error: # ** Error: (vsim-7) Failed to open ini file "tmpfile" in write mode. # No space left on device. (errno = ENOSPC) There is almost 3Gb of free space on my harddrive so I dont understand the "No space left on device" line. Has anyone seen this before? Any suggestions? Cheers, RobArticle: 115982
"Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message news:erp4q3$di5$1@news.lysator.liu.se... > On 2007-02-23, HT-Lab <hans64@ht-lab.com> wrote: >> >> "Andreas Ehliar" <ehliar@isy.liu.se> wrote in message >> news:ern2na$s3t$1@news.lysator.liu.se... >>> I've been interested in using SystemVerilog for quite some >>> time now I don't really know if the tool support is there >>> yet. ..snip > > 2006a.112 is actually what I'm testing as well. Some interface constructs > work and some doesn't but I came up with a workaround (I think): Hi Andreas, There is a new special build 2006a1.18 which, according to our Mentor TME, has some updated SystemVerilog support. See: http://www.mentor.com/precision/customer/downloads/ Regards, Hans www.ht-lab.comArticle: 115983
Hey guys, I don't understand you... Lattice XP is far more advanced than this stuff, and around for almost a year now. OK, xilinx marketing is better but still ... nothing very exciting if one tries to be a bit objective. It looks to me that you are all a bit too much xilinx minded. I guess this S3-AN is a 2 die solution. As far as I know there is no 90nm flash/SRAM process around (except for Fujitsu then). Thus 2nd generation XP can be expected quite soon. Luc On 26 Feb 2007 14:01:30 -0800, "Antti" <Antti.Lukats@xilant.com> wrote: >On 26 Feb., 22:45, n...@puntnl.niks (Nico Coesel) wrote: >> "Peter Alfke" <p...@xilinx.com> wrote: >> >You had gotten a "sneak preview" per e-mail. >> >Please give our guys one more day to get the website running properly. >> >Apparently there is lots of (well-deserved) excitement... >> >Good! >> >Peter Alfke >> >> The mail Antti got looks good. Maybe I can slip the Spartan 3AN into a >> current design if it is not too different from a regular Spartan 3. >> >> -- >> Reply to nico@nctdevpuntnl (punt=.) >> Bedrijven en winkels vindt U opwww.adresboekje.nl > >consider them "as" S-3A, so look at S-3A and that what you get in >S-3AN as well. >only add the nonvolatile part... > >Antti > >Article: 115984
<robquigley@gmail.com> wrote in message news:1172569676.056541.176350@j27g2000cwj.googlegroups.com... > Hey all. > > I dont know whats happened my Modelsim but anytime I try and do > anything with it like open/close/create a project I get this error: > > # ** Error: (vsim-7) Failed to open ini file "tmpfile" in write mode. > # No space left on device. (errno = ENOSPC) > > There is almost 3Gb of free space on my harddrive so I dont understand > the "No space left on device" line. > > Has anyone seen this before? Hi Rob, If you are using Linux, can you check that you have enough space left in /var/tmp df -k /var/tmp Hans www.ht-lab.comArticle: 115985
lb.edc@telenet.be wrote: > I don't understand you... > Lattice XP is far more advanced than this stuff, and around for almost > a year now. OK, xilinx marketing is better but still ... nothing very > exciting if one tries to be a bit objective. I guess someone at Xilinx will reply as to what they consider to be their __technical__ edge. What is the real shipping status of the Lattice parts?Article: 115986
Hi, I'm looking for archive of Teaching Materials (especially, Xilinx FPGA Design Flow Workshop Materials). Those available at http://www.xilinx.com/univ/teaching_material.htm are based on the Xilinx ISE v.8, but I'm interested in these based on v.7. Best regards, Salam mesra, Serdecznie pozdrawiam, Nanyang Technological University, IntelliSys, PhD Student, Pawel Piotr Czapski pczapski (at) pmail . ntu . edu . sg, +65 93974059Article: 115987
Hi, Currently, I'm doing some experiments with multiple clock domains and Handel-C (by Celoxica). However, as far as I know, it is not possible to call PAL library in different clock domains. I do communicate different clock domains using channels. I just wonder if I use interfaces to communicate clock domains I may overcome these problems. Is it? Or is there any other solution to deal with it? Have you ever tried to call PSL library in different clock domains? Thank you for any suggestions. Best regards, Salam mesra, Serdecznie pozdrawiam, Nanyang Technological University, IntelliSys, PhD Student, Pawel Piotr Czapski pczapski (at) pmail . ntu . edu . sg, +65 93974059Article: 115988
Hi Michael, On 25 Feb., 02:22, Michael Gernoth <m...@gernoth.net> wrote: > To achieve this, I have written a wrapper library for impact which > maps calls to windrvr to the userspace libusb-library which should be > available on all modern linux distributions. You just made true one of my dreams. Finally! :-)) I'll give it a try ASAP. Greetings, TorstenArticle: 115989
Hi Austin, On 24 Feb., 18:15, Austin <aus...@xilinx.com> wrote: > The 10G MGTs are all discontinued. > > Anyone who had alrewady designed them in is supported. > > But, there are no new orders accepted. > > The issue was that the rate (10Gbs) was just too demanding for the > design and technology. By that, I mean yield of the final chips was > unacceptable. All MGTs had to work at all rates, over all temperatures, > with the exact same bit settings. Speaking of fast networking with Xilinx FPGAs: I've read about getting 780MByte/s via TCP/IP using a Virtex4 with the stack from treck.com. That should be fast enough for our current development. But in case we need more in future, any idea how to implement this on a Xilinx FPGA? Greetings, TorstenArticle: 115990
Tim wrote: > I guess someone at Xilinx will reply as to what they consider to be > their __technical__ edge. For one thing you can't access the flash in XP-parts from the logic, as far as I know. The flash is just for configuration. At least that's what the FAE told me, when i asked if there were at least a few blocks I could put user data into. So that would be one advantage of the Spartan-3AN. > What is the real shipping status of the Lattice parts? XPs are shipping, and in low quantities as well. Last time I asked my distributor, they had every part I asked for in stock. But it's been a while... -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 115991
Hello~ I'm beginner and so looking for someone who know how to get the infomation about the number of used BRAM from reporting file. I think that it would be like "Dual Port Memory". is it right? Thank you for reading.Article: 115992
>
> Directly from the Xilinx website, I've been getting issues with these,
> whether it's the single file download or the web install. 9.2i installer
> gave me a bus error and with the older versions the script files gave me
> some checksum errors as I said before (wget or otherwise).
> I found some old mirror sitehttp://www.tx-g.net.hu/files/xilinxthat
> had the files for 8.2i archived. I tried the WebInstall version from
> there (as it's a smaller file) and it actually opened, but the install
> didn't succeed.
> This led me to suspect that the single file install from this mirror
> would probably work ok for me. It is a slow server and took over 3 hours
> to downoad (against 20 minutes straight from Xilinx) but the install
> worked!
>
> I do have an AMD64 Athlon processor, so I may be interested in hearing
> your script file edit.
> Is it the settings.sh, Display:= 0 thing that I've been seeing around,
> or something else?
>
First, and I know this sounds dumb, but I'd suggest booting into
memtest86 (ubuntu ships it by default as one of your boot options) and
checking your ram. Every time I've had strange download problems it's
ended up being a ram problem -- and this has happened three times over
the past few years.
I found that I had to edit the top of settings.sh to identify my
platform as an x86 (and not x86-64) linux.
PLATFORM=lin
Why xilinx doesn't also release 64-bit webpack, I'm not sure :) But
their linux support has been so nice that I'm not complaining. Maybe
someday they'll actually package rpms or debs for us!
I'm curious, what do you use for HDL sim under linux?
...Eric
Article: 115993Hi, I have a process in my code that is decides if enable pin of a counter is high or low. When i start my simulation the process is triggered by one of the signals in the sensitivity list and the signal goes to high, but it doesn't get triggered when the same signal in the sensitivity list gets the triggering value again or the enable signal never goes to again... Any ideas please ...Article: 115994
Tim, It's true, flash is only for configuration. But still this flash can be used as mirror for the EBR (no write back though). I'm using the XP6 in small volumes (50pcs). LT was something like 4wks. Not bad I believe. Luc On Tue, 27 Feb 2007 11:14:14 +0000, Tim <tim@nooospam.roockyloogic.com> wrote: >lb.edc@telenet.be wrote: >> I don't understand you... >> Lattice XP is far more advanced than this stuff, and around for almost >> a year now. OK, xilinx marketing is better but still ... nothing very >> exciting if one tries to be a bit objective. > >I guess someone at Xilinx will reply as to what they consider to be >their __technical__ edge. > >What is the real shipping status of the Lattice parts?Article: 115995
lkjrsy@gmail.com wrote: > Hello~ > > I'm beginner and so looking for someone who know how to get the > infomation about the number of used BRAM from reporting file. > I think that it would be like "Dual Port Memory". is it right? > > Thank you for reading. > Look for "Number of FIFO16/RAMB16s" in *.mrp file.Article: 115996
Steve, hello, > So I'm going to try the getting the single file downfload from this > server.. as painfully slow as it is. > Any other input on what else I might try is appreciated, though. I used to run ISE 8.2.0.2 on Ubuntu 6.10 without serious trouble for some time. The only thing which was important to get the simulator going was: $ cd Xilinx/gnu/gcc/3.2.3/lin/i686-pc-linux-gnu/bin $ mv ld ld.bak $ ln -s /usr/bin/ld ld I now run ISE 9.1i on Ubuntu Feisty (7.04 - herd4). No problems at all -- and no trickery (you don't have to replace the linker as done for 8.2.*) But you have to install libc-dev. j,Article: 115997
ANIL CELEBI wrote: > Hi, I have a process in my code that is decides .... This would be much easier if you would show us the code. --- Joe Samson Pixel VelocityArticle: 115998
Yes, it can by using the user configurable/accessible boundary scan registers on the FPGA. For more info and a list of resources go to Google groups and search for a thread by me about the same thing on the Virtex II. ---Matthew Hicks > can it be done? > > where do I look for information? > > Rich >Article: 115999
On Feb 27, 3:14 am, Tim <t...@nooospam.roockyloogic.com> wrote:
> lb....@telenet.be wrote:
> > I don't understand you...
> > Lattice XP is far more advanced than this stuff, and around for almost
> > a year now. OK, xilinx marketing is better but still ... nothing very
> > exciting if one tries to be a bit objective.
>
> I guess someone at Xilinx will reply as to what they consider to be
> their __technical__ edge.
No doubt about it, the Lattice XP parts are a nice solution.
So what is the technical advantage of Spartan-3AN? Here are but a few
points to consider.
* Spartan-3AN FPGAs offer significantly more in-system Flash memory,
between 627K to 12,251K even after storing an uncompressed FPGA
configuration bitstream.
+ Store two different FPGA configuration bitstreams
o Dynamically select between the two from with the FPGA
application using the MultiBoot feature
o Fail-safe "live" in-system Flash updates
+ Code-shadow MicroBlaze code within the FPGA
+ Fully accessible from within the FPGA application
* Spartan-3AN In-System Memory is extremely robust
+ Intended for use by the FPGA application, not just configuration
+ 100,000 erase/program cycles
+ 20 year data retention
* Spartan-3AN FPGAs offer the power-saving Suspend mode
+ Retains FPGA configuration and application state
+ Fast response time
* Spartan-3AN FPGAs have embedded 18x18 hardware multipliers
? I don't believe that XP parts have multipliers
* Spartan-3AN FPGAs span a broader range of densities, up to 22.5K
LUTs
* Spartan-3AN FPGAs have more I/O, more I/O per package, up to 502 I/
O pins
* Spartan-3AN FPGAs offer more on-chip RAM
+ More block RAM
+ More LUT RAM
* Pin-compatible with select members of the Spartan-3A FPGA family
+ Architecturally identical to Spartan-3A FPGA family
I wouldn't claim that either part is "instant on", although the
Lattice XP part
-- Steve Knapp
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