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Messages from 11600

Article: 11600
Subject: Re: New Evolutionary Electronics Book
From: coulson@leland.Stanford.EDU (Gordon Coulson McNaughton)
Date: 26 Aug 1998 07:15:00 GMT
Links: << >>  << T >>  << A >>
A moment of your time please, Tom...

Tom Kean (tom@algotronix.com) wrote:
: Mike McCarty wrote:
: > )->In reconfigurable hardware, the behaviours and interconnections of the
: > )->constituent electronic primitives can be repeatedly changed. Artificial
: > )->evolution can automatically derive a configuration causing the system to
: > )->exhibit a pre-specified desired behaviour. A circuit's evolutionary

[snip]

: > Let me translate this little bit into English.
: >
: >         Hardware which can be changed can be changed more than once. It
: >         is sometimes possible to make the hardware configure itself.

[snip]

: <FLAME>
: Actually, its not 'obfuscated bullshit' its precise scientific english: you
: just have to turn off the TV, put down your beer and engage your brain
: before reading it.

I enjoy drinking beer.  I also enjoy thinking.  Are the two mutually exclusive?
Most of my friends are philosophical drunks. ;)

Actually, the summary is obfuscated.  That's not necessarily bad, that 
just happens to be a side-effect of the type of summary being written: a 
dense, high information-per-sentence paragraph that attempts to explain a 
general concept (which takes an entire book to fully describe, or so one 
infers) in a short amount of space -- hence, a summary of the concept.  In 
order to explain such a wide concept in precise terms in a short summary, 
dense language is used which must be read carefully.  Obfuscation (as webster 
says, "to make obscure") is not the purpose of such language, rather it is a 
side effect of the concept-condensing process.

This is not the only kind of summary which could have been written.  It was 
written thoughtfully and deliberately.  Alternatively it could have been a 
topical overview of the specific discussions within the text, etc.  However, 
the author of the summary believed that this sort of dense conceptual 
specification would engage people who would be interested in reading the book.
The summary is obviously not bullshit, since it imparts very precise and 
accurate information to the people who extract it.

I sincerely hope that your flame against anyone not willing to extract that 
information was just a knee-jerk reaction (careful with those, now).  There 
was a pointed comment that the summary could have be written in a more 
accessible fashion: you disagree (maybe the book itself is not accessible, 
and such a summary would be misleading?).  Fine, disagree, but don't  
automatically light up a blowtorch (care with those, too!).

: For example:
: 
: 'Hardware that can be changed can be changed more than once' FALSE
: what about fuse technologies?  The original text does not make this claim.

The original text (as quoted by my newsreader, tin) says:
  "In reconfigurable hardware, the behaviours and interconnections of 
   the constituent electronic primitives can be repeatedly changed."
						^^^^^^^^^^
The use of the word "repeatedly" implies that the hardware can be changed 
more than once.  It may be false to infer that the *same* behavior or 
connection can be changed more than once, but it is very clear that the 
hardware in general can be.  Do you disagree with this interpretation?

: 'It is sometimes possible to make the hardware configure itself'
: The text does not say this either - what it says is that a configuration 
: can be derived from artificial evolution.

From the quoted portion of the message I saw, I would agree.

It is interesting to note that the summary uses the phrase "a circuit's 
evolutionary..."  If this refers to the evolutionary capabilities of the 
entire system in redesigning a specific circuit, you are right.

If this refers to the *physical* circuit, stating that the *physical* hardware 
circuit(ry) has evolutionary capabilities (outside of the context of a 
surrounding system), then one would assume that the circuit has the ability 
to modify itself (since it can evolve outside of a system, when there is 
nothing else to modify it!).

: </FLAME>

</rebuttal>

: Tom.

With respect, Gordon.

------------------------------------------------------------------
Common sense and a sense of humor are the same thing, moving at
different speeds.  A sense of humor is just common sense, dancing.
                -- Clive James
Article: 11601
Subject: Re: PROM alternative
From: "Daniel Lang" <dblx@hydra0.caltech.edu>
Date: 26 Aug 1998 07:56:01 GMT
Links: << >>  << T >>  << A >>
Jeff Berryhill <berryhill@uchicago.edu> wrote in article <Ey9E1B.4Bx@midway.uchicago.edu>...
> In article <6rt9de$j01$1@nnrp1.dejanews.com>,
> 	jcvilleneuve@hotmail.com writes:
> > 
> > Is anybody has used something else than a PROM for the
> > configuration cycle of
> > their FPGA (example direct CPU to fpga)?
> > 
> We are currently designing a board, upon which resides upwards of a dozen
> Altera FLEX10K FPGAs.  The board resides in a crate with VMEbus access from
> a PC.  The board itself contains an Altera MAX7000 chip which coordinates
> VME I/O, a large (16 Mb) FLASH memory, and an additional MAX9000
> 'boot chip' which emulates the configuration cycle of a FLEX 10K.  
> 

I did something very similar for a VXI based A/D converter board.
An Altera MAX7128S decodes the VXI A16 space registers and contains
a register that controls downloading 5 EPF10K20s and 2 EPF10K10s.
I first program the MAX7128S using a Byteblaster and then the rest
of the board is configured via the board's device drivers.  This
allows reconfiguration of the board for different applications.

Daniel Lang  dblx@tyrvos.caltech.edu  (but remove the x) 
Article: 11602
Subject: Re: How to design a PLL
From: jhallen@world.std.com (Joseph H Allen)
Date: Wed, 26 Aug 1998 09:26:08 GMT
Links: << >>  << T >>  << A >>
In article <35E3A88B.7FEBCF88@studm.hrz.uni-siegen.de>,
Justen  <justen@studm.hrz.uni-siegen.de> wrote:
>Hi,
>
>I would like to build a digital PLL with a XILINX 4010 FPGA. The
>generated frequency should be 9.5MHz to 10MHz in steps of 1kHz. So I
>have to use a 1kHz Referenz (this is also the frequenzy of the
>PhaseDetector) and multiply it with 9.500 to 10.000. At the moment, I
>use a PhaseDetector von Xilinx AppNote and an Integrator to close the
>loop. But this isn't a good design. The PhaseJitter is to big. Could
>anybody help me to improve this design?

If you look at the design equations for PLLs you discover that jitter is
usually specified as a phase angle relative to the reference (1KHz)
frequence... so your PLL is probably working fine, but not at the very high
performace you had hoped for.

Here are some things to try:

- The reference must be very low jitter.  It _must_ be xtal oscillator
  derived.

- The VCO should also be very low jitter.  Varactor tuned LC oscillators
  tend to be much better than relaxation oscillators.  The tuning range
  should be as narrow as possible (9.5 to 10 sounds good).

- If you can get away with it, increase your reference frequency.  A
  multiplier of 950 is much easier to deal with than 9500- you're getting
  phase corrections 10 times more frequently.

- Increase the bandwidth of the loop (reduce the value of the integrating
  capacitor).  This gives you more reference frequency feed-through, but
  less jitter.  Also make sure that you add the extra zero in the loop
  filter or the loop will not be stable: If you consider VCO-rate phase as
  the controlled variable, then you have two integrators (the VCO is an
  integrator of phase) in series.  When you close the loop, you'll get a
  second order system with no damping and lots of gain (the division ratio
  ends up being part of the gain from this point of view).

- Use a low noise op-amp for the integrator.

- Add a little droop to the integrator (pull the input up or down with a
  large resistor).  Any sequential phase detector not made with equal delays
  (as in random Xilinx place and route) will have a dead band where the loop
  is essentially open and has no control over the jitter.  The droop will
  force the loop to have a correction on each reference clock edge, thereby
  eliminating this problem.

- Get the Motorola PLL and MECL databooks and read the application notes
  therein.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 11603
Subject: Re: Porn spamming
From: ac@cd.com
Date: Wed, 26 Aug 1998 09:27:06 GMT
Links: << >>  << T >>  << A >>
I managed to get this stopped - you've probably noticed that they
haven't posted for the last few days. I won't go into the details
of how i did it, since the original offenders have probably found
this thread on dejanews. One of the people I listed admitted that
he hosted the sites, and that he had now asked them to move
elsewhere.

However, if you don't have any legal backing, then this procedure
will probably work in future cases:

Spammers (of this sort) will generally have a web site. To get some
contact names for their domain name, do a WHOIS search at Internic
(http://internic.net/cgi-bin/whois). These are real names and email
addresses - Internic needs them to contact the domain, to collect
their registration fees. There's a section at the bottom of the
search page, titled 'domain servers in listed order'. For many (not
all) sites, this will list the upstream service provider.

Email any addresses you can find on the 'whois' output, although
it isn't necessary to include the domain servers at this stage.
Tell them, politely, that your newsgroup has been spammed, and
that you will take steps to contact their upstream providers
if the abuse isn't stopped. Use a false return address if you want,
but there shouldn't be any problem using a real address with
this sort of message.

This should do the trick. If it doesn't, copy the email to the
domain servers listed on the 'whois' output. These are just
domain names, so you'll need to find a real address - 
postmaster@domain and abuse@domain should be Ok. Some sites
list themselves, or a related site, as their own domain server,
in which case you can use 'traceroute' to find any upstream
connections. There are lots of traceroute servers - just do a
search for 'traceroute'.

Article: 11604
Subject: Re: How to design a PLL
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 26 Aug 1998 09:38:10 -0400
Links: << >>  << T >>  << A >>
If you read Joseph's post, he specifically states he is building a digital PLL.
Your hints, while correct for analog PLLs are not all that applicable for a digital
one.  To improve the jitter specification on a digital PLL, Joseph needs to raise
the frequency of his master clock (not the reference).  Reading Joseph's post
again, I think what he really wants is digital frequency synthesis.  If he is not
attempting to lock to an external reference, then he should use an accumulator with
a programmable increment and a high frequency master clock.  If he is attempting to
lock to an external signal (the 1KHz reference), then a PLL or DPLL is needed.  If
there is a VCO, then it is a PLL not a DPLL.  The DPLL needs a higher frequency
master clock.  The amount this is higher than the target frequencies determines the
amount of jitter.
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11605
Subject: Re: FPGA vendors
From: Srikanth Gurrapu <gurrapu@ti.com>
Date: Wed, 26 Aug 1998 09:16:41 -0500
Links: << >>  << T >>  << A >>
Hello Reza,

Different vendors have different characteristics and different price
ranges for different perfromance levels..

I guess the best starting point is to estimate your design
gate-count/speed-requirement..
I have experience w/ Altera and Xilinx(Two leading FPGA vendors, in my
opinion)..
Lots of literature is avalibale at altera.com and xilinx.com

I feel the Altera FPGAs are cheaper compared to Xilinx FPGAs.. The Altera
EPLDs
have EABs which can be used as big chunks of memory blocks unlike distributed
memort element slike in XIlinx.. So, if your design has lots of memory, Altera
might be better..
The Altera place&rooute tools are alsoeasy to learn as I recently did while
designing w/ 10K100-1 which is kind of the largest and fastest FPGA available
in 240-pin package..
With the new Xilinx versions, I guess it is also easy to learn the Xilinx
tools..

Reza Bohrani wrote:

> I am new to to world of FPGA and would like to now which vendor to choose.
> We have Actel, Altera, Xilinx, Lucent ... and many more. Can anyone please
> tell me which one is the cheapest, the "best"?
> Sincerely
> Reza



Article: 11606
Subject: Re: vector product minimization problem
From: "John L. Smith" <jsmith@visicom.com>
Date: Wed, 26 Aug 1998 12:14:23 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------566787CF4671EAA22D6AFE34
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

benyamin@my-dejanews.com wrote:

 Any thoughts?
(on constant vector dot variable vector product logic minimization)I don't think my
posts have been much help, you'veput a lot more thought into the topic than I have
time to.
Thanks for an interesting topic though, its been fun
thinking about.

You might consider extending your investigations
into (constant matrix)(variable vector). Depending
on the nature of the constants, there may be many
redundancies in the calculations that can be exploited
to produce simpler circuits.

May I ask if the S/W you're putting together is for
your own use, a commercial product, or are you
willing to share?

- John


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begin:          vcard
fn:             John L. Smith
n:              Smith;John L.
org:            Visicom Imaging Products
adr:            1 Burlington Woods;;;Burlington;MA;01803;USA
email;internet: jsmith@visicom.com
title:          Principal Engineer
tel;work:       781-221-6700
tel;fax:        781-221-6777
x-mozilla-cpt:  ;0
x-mozilla-html: FALSE
version:        2.1
end:            vcard


--------------566787CF4671EAA22D6AFE34--

Article: 11607
Subject: How to use port in Altera Max+II (7xxx)
From: Rizwan Muhammad <rizwan@krusty.ee.ualberta.ca>
Date: Wed, 26 Aug 1998 11:31:56 -0600
Links: << >>  << T >>  << A >>
Hello every one !

I am a new user to Altera and fpga technology and I am looking for how
to define the port in Altera board Maxp+II(7xxx) series,  as in shown in
my code (below to see) but whenever I am going to assign the port signal
to fpga it is always giving me the error that pin # is not defined in
VHDL code , also I dont know how to transfer the compiled code to Altera
fpga as I am unable to browse the assigned  fpga, please help me.

Thanking all of you in anticipation

Rizwan
------------------------------------------------------------------
entity shifter is
port (shftin :in bit_vector (0 to 3);
      shftout :out bit_vector(0 to 3);
      shftctl :in bit_vector (0 to 1));
end shifter;

architecture behav of shifter is    --architecture body
begin
 f2:
 process(shftin, shftctl)
 variable shifted:bit_vector (0 to 3);   --proc. decl. part
begin
 case shftctl is
 when "00" =>shifted :=shftin;
 when "01" =>shifted :=shftin(1 to 3) & '0';
 when "10" =>shifted :='0' & shftin(0 to 2);
 when "11" =>shifted :=shftin(0) & shftin(0 to 2);
end case;
shftout<=shifted after 10 ns;
end process f2;
end behav;

Article: 11608
Subject: FACTS: Evolutionary Electronics Book
From: adrianth@cogs.susx.ac.uk (Adrian Thompson)
Date: 26 Aug 1998 17:39:57 GMT
Links: << >>  << T >>  << A >>
THE FACTS about the New Evolutionary Electronics Book.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

BACK-COVER:
`Hardware Evolution' describes the use of computer simulations of Darwinian
Evolution as a way of designing electronic circuits automatically. Amidst
increasing interest from academic and industrial communities, researchers are
just beginning to map out the exciting possibilities and practicalities of the
idea. In this book, Adrian Thompson concentrates on the fundamentals - what
sort of thing can an evolved circuit be? Through a sequence of arguments and
experiments, it is shown that evolution can produce `bizarre but useful'
circuits, beyond the scope of conventional design. The experiments (the first
of their kind) apply evolution to a Field-Programmable Gate Array (FPGA) chip,
and show the promise of significant real-world engineering applications.

COMMENT:
This was my PhD thesis. It was selected by the British Computer Society to be
published unchanged by Springer. The summary I originally posted is a
scientific abstract, so yes it is more formal than a book would normally be.
Thanks to those who've pointed out that the attempts given by responders to
`translate into plain English' end up saying things that are wrong. A precise
statement in plain-speaking English without loss of information would have
been longer than the regulations allow a thesis summary to be.

In my original posting, I was attempting to be as brief and informative as
possible for a science/R&D audience. This has backfired somewhat in provoking
a discussion across several newsgroups! I'm pleased that people care, and for
those who don't want to read the summary (which does indeed take some
consideration), the back-cover text is provided above. The book itself, I
think, is quite readable: that's one of the BCS's selection criteria.

Ordering Information
^^^^^^^^^^^^^^^^^^^^
Springer-Verlag, 1988.
Distinguished Dissertations Series
ISBN 3-540-76253-1
http://www.springer.co.uk/comp/books/distinguished.html
email: postmaster@svl.co.uk
Article: 11609
Subject: Re: vector product minimization problem
From: benyamin@my-dejanews.com
Date: Wed, 26 Aug 1998 19:57:38 GMT
Links: << >>  << T >>  << A >>

> Now tabulate the additions (as Rick suggests below):
>
> 8                  H
> 4          D E F G
> 2      B C     F G
> 1    A   C   E   G
>

Such representations is exactly what I have been working on! That's why I
posted the question in the first place...I wanted to see if stuff like this
existed.  I have come up with a few rules about how one can minimize
expressions when the data is formatted in such a way, and I have also written
code to implement it.

The problem is that the search space can become quite large, so I am trying
now different approaches of keeping the problem managable.

Dan
benyamin@ucla.edu

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11610
Subject: CPLD/FPGA software
From: tigerz@my-dejanews.com
Date: Wed, 26 Aug 1998 20:39:17 GMT
Links: << >>  << T >>  << A >>
Hello,

I would like to learn about CPLD/FPGA programing.  I found that there are two
low cost tool from Cypress and Xilinx for $95.  Can someone give me suggestion
on which one to purchase and why?  Any other low cost alternative?  Thanks in
advance for feedback.

Tiger

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11611
Subject: Re: CPLD/FPGA software
From: Gerald Coe <gerry@see-sig.co.uk>
Date: Wed, 26 Aug 1998 22:36:49 +0100
Links: << >>  << T >>  << A >>
In article <6s1rpl$3p4$1@nnrp1.dejanews.com>, tigerz@my-dejanews.com
writes
>Hello,
>
>I would like to learn about CPLD/FPGA programing.  I found that there are two
>low cost tool from Cypress and Xilinx for $95.  Can someone give me suggestion
>on which one to purchase and why?  Any other low cost alternative?  Thanks in
>advance for feedback.
>
>Tiger
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum

Machxl2.1 is free from vantis - www.vantis.com

-- 
Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031,
Gerald Coe      | .demon.co.uk    | 68302, 64180, 80C188EB cpu modules. 
http://www.devantech.demon.co.uk  | Full custom uP control systems designed.
Article: 11612
Subject: Re: How to design a PLL
From: "Daniel Lang" <dblx@hydra0.caltech.edu>
Date: 26 Aug 1998 23:43:27 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <no_spam_randraka@ids.net> wrote in article <35E40FC2.4DB3B88@ids.net>...
> If you read Joseph's post, he specifically states he is building a digital PLL.
> Your hints, while correct for analog PLLs are not all that applicable for a digital
> one.  To improve the jitter specification on a digital PLL, Joseph needs to raise
> the frequency of his master clock (not the reference).  Reading Joseph's post
> again, I think what he really wants is digital frequency synthesis.  If he is not
> attempting to lock to an external reference, then he should use an accumulator with
> a programmable increment and a high frequency master clock.  If he is attempting to
> lock to an external signal (the 1KHz reference), then a PLL or DPLL is needed.  If
> there is a VCO, then it is a PLL not a DPLL.  The DPLL needs a higher frequency
> master clock.  The amount this is higher than the target frequencies determines the
> amount of jitter.
> 
Given the original posters specs (9.5 MHz to 10.0 MHz in 1 KHz steps), it
is unlikely that he is using a completely digital approach.
I pulled the app note off the Xilinx website and it is indeed a hybrid
analog/digital PLL with analog low-pass filter and VCO.
Joseph Allens tips are good.  I would like to mention one additional item.
When the reference leads the signal you get a pump down output and when
the reference lags the signal you get a pump up output (or vice versa
depending on the VCO).  You must adjust the timings so that when the 
phase error is very small, there is a small overlap where you get both
the pump up and pump down signals.  Use separate resistors from the pump
up and pump down outputs to the capacitor to avoid simultaneous conduction.
This avoids a dead zone in the comparator's phase response.

Daniel Lang  dblx@tyrvos.caltech.edu  (but remove the x)
Article: 11613
Subject: Re: CPLD/FPGA software
From: msimon@tefbbs.com
Date: Wed, 26 Aug 1998 23:55:53 GMT
Links: << >>  << T >>  << A >>

PALASM from AMD is free. 

I also like the Xilinx Software - available from discount book stores.

I haven't tried any other stuff yet.

Simon

tigerz@my-dejanews.com wrote:

>Hello,
>
>I would like to learn about CPLD/FPGA programing.  I found that there are two
>low cost tool from Cypress and Xilinx for $95.  Can someone give me suggestion
>on which one to purchase and why?  Any other low cost alternative?  Thanks in
>advance for feedback.
>
>Tiger
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum

Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.
Article: 11614
Subject: Digital PLL
From: mrizwan@rocketmail.com
Date: Thu, 27 Aug 1998 00:35:53 GMT
Links: << >>  << T >>  << A >>
I am in search of  information about the  digital phase lock loop, can	any
one send me  information that can help me  in designing  a  digital phase
lock loop, I want to design it by using FPGA  Altera  chip, or give me hint
about the material finding  about digital phase lock loop.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11615
Subject: OLE automation access to WorkViewOffice or ViewDraw ?
From: muzok@pacbell.net (muzo)
Date: 26 Aug 1998 18:14:57 PDT
Links: << >>  << T >>  << A >>
hi,
has anyone worked with the OLE automation interface to viewdraw or other portions
of WorkViewOffice ? Does anyone have a simple script to create a new schematic
and instantiate a component, save, netlist etc?

thanks

muzo

WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>
Article: 11616
Subject: Re: CPLD/FPGA software
From: "Mankit Wong" <lsckwong@netvigator.com>
Date: 27 Aug 1998 01:33:54 GMT
Links: << >>  << T >>  << A >>
Hi,

Try Lattice's free ISP Synario. You can download it from
http://www.latticesemi.com.

balabala

tigerz@my-dejanews.com wrote in article
<6s1rpl$3p4$1@nnrp1.dejanews.com>...
> Hello,
> 
> I would like to learn about CPLD/FPGA programing.  I found that there are
two
> low cost tool from Cypress and Xilinx for $95.  Can someone give me
suggestion
> on which one to purchase and why?  Any other low cost alternative? 
Thanks in
> advance for feedback.
> 
> Tiger

Article: 11617
Subject: compile -ungroup_all
From: iman@mercury.news.pacific.net.sg ( Imanuddin Amril Account)
Date: 27 Aug 1998 01:42:05 GMT
Links: << >>  << T >>  << A >>

Hello everyone ..

I am synthesizing my 8-bit uC using FPGA-compiler from Synopsys, 
targeting to XC4025EPG299-2. I follow all procedures for this 
Xilinx(XC4000)-Synopsys compilation from their docs/app notes.

First, compile using : compile -map_effort med
The result :
    report_timing : slack = +9.32(MET)
    report_fpga   : Total num. of CLBs = 1119
		    Total num. of cells = 1143
After PPR :
    100% connections routed (after quite a lot iterations and still 
    some nets failed to meet the constraint)

Second, compile using : compile -map_effort med -ungroup_all
(as new Xilinx app notes/v.1995 suggested)
The result :
    report_timing : slack = +32.17(MET)	-- definitely better
    report_fpga   : Total num. of CLBs = 696
		    Total num. of cells = 721 -- definitely smaller
After PPR :
    Only 86% connections routed (it gives up !)

Can somebody explain me this ? Any pointer to yield a better result 
for second effort is appeciated.
FYI all designs before this are successfully 100% routed using the 
second method, since it will guarantee more compact and smaller area
for cells (definitely better yield compare to first method). 
But why this failed ?

TIA

-- 
-iman
===============================================
= Watch the transformation or be a part of it =
===============================================
Article: 11618
Subject: Re: SYNTHESIS TOOLS
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Thu, 27 Aug 1998 03:05:46 GMT
Links: << >>  << T >>  << A >>
We recently compared the Foundation / Synopsys sythesiser against
Galileo Extreme 4.2.2, for a number of existing VHDL projects in the
5k - 20k gate range which had been synthesised with Galileo in the
past.
For the designs that the Synopsys tools were able to compile, it
produced results that were about 20% bigger.
There were a number of designs that required simple modifications to
compile, and some that (would have) required major modifications.
[ Things like generic parameters being 2 diminsional arrays, vhdl'93,
etc, caused problems. ]

I guess you get what you pay for.

I hear that Synplify is about the same as Galileo, but I have not
independently confirmed this.

--
Allan.

On Tue, 25 Aug 1998 21:17:09 -0700, Scott Campbell
<sjcampbe@earthlink.net> wrote:
>I am not sure what tool is the BEST on the market, but I have Xilinx's
>Foundation series 1.4 software. It includes Synopsys' FPGA express for synthesis
>as well as a HDL entry ( VHDL/Verilog/ABEL ), and schematic entry tools. I
>believe that the student version ( schematic / ABEL entry ) is only $100, and
>will soon be upgradable to VHDL/Verilog for free in their 1.5 release coming
>soon. Of course the student version is limited to synthesis of Xilinx parts less
>than 10,000 gates, but I believe the (1.5) upgrade will include larger device
>size and support for Altera and Lucent parts. Check out their web page
>http://www.xilinx.com Hope this helps.
>
>Scott Campbell
>sjcampbe@ece.ucdavis.edu
>University of California Davis
>
>Reza Bohrani wrote:
>
>> Which pc-based synthesis tool is the best on the market. I have heard of
>> Synplify; is that a good tool or should I go for Leonardo or are there other
>> good tools?
Article: 11619
Subject: Re: CPLD/FPGA software
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Wed, 26 Aug 1998 21:30:02 -0700
Links: << >>  << T >>  << A >>
tigerz@my-dejanews.com wrote in message <6s1rpl$3p4$1@nnrp1.dejanews.com>...
>Hello,
>
>I would like to learn about CPLD/FPGA programing.  I found that there are
two
>low cost tool from Cypress and Xilinx for $95.  Can someone give me
suggestion
>on which one to purchase and why?  Any other low cost alternative?  Thanks
in
>advance for feedback.

The replies you've gotten so far suggest free software.  This is certainly
worth a look, given the price, but as far as I'm aware the only thing you'll
get for free is schematic entry, ABEL entry, and JEDEC-style simulation.
This stuff is fun to play with, but if you have ambitions of doing serious
FPGA designs, you'd be much better off spending that $100.

The $100 you send to Xilinx gets you the most compehensive package.  You get
full simulation capabilities, schematic entry, state machine entry, and
logic synthesis for all of Xilinx's CPLDs and the more modest FPGAs.  The
Xilinx university software is version 1.3, which is unfortunate since
version 1.4 and above include VHDL synthesis as well.  It is legal to
install 1.4 with your 1.3 license but you need to find someone with the CDs.
Xilinx is going to upgrade all those student copies to 1.5 later this year.
They're probably holding off on upgrading people to 1.4 because the VHDL
synthesis (provided by Synopsys' FPGA Express) isn't very well integrated
into the design flow yet.

The $100 you send to Cypress will get you a VHDL synthesis package today.
And a decent book.  And, um... that's about it.  There is a JEDEC-style
simulator, but it's not really all that useful.  The book is useful for
learning VHDL, whereas the book that comes with the Xilinx stuff is more an
introduction to digital design techniques that happens use ABEL (primarily)
as strictly a means to an end.  The guy who wrote that book has translated
all of the ABEL into VHDL lately and has it on his web site, however.  Note
that the Cypress $100 package includes software updates for awhile; you can
get the same package without the update service for <$50 at a bookstore; the
software is bundled with the book.

If you have to get just one, in general I'd go for the Xilinx software.
You'll get VHDL no later than the end of this year.  If you really want to
learn VHDL, the Cypress package is better to start with.

One other thing I can think to mention is that Xilinx doesn't support the
student editions of the software; you're supposed to go bug your instructor
(which is unfortunate in a way, since not all instructors know much more
about the software than the students do...).  On the other hand, Cypress
doesn't designate their software as a student version, so while you're
pretty much stuck e-mailing them, you can get them to answer any question
you have.

---Joel Kolstad



Article: 11620
Subject: Busses in Xilinx Foundation's schematic capture program
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Wed, 26 Aug 1998 21:59:22 -0700
Links: << >>  << T >>  << A >>
I've been trying to use busses in Foundation's schematic capture program
(Active CAD "lite" by Aldec, I believe), and I have a question.  If I
instantiate some component for the Xilinx unified component libraries, say,
a 16 bit counter, and I only want to look at the lower 12 bits of that
output, how can I do it using a bus?  If I just declare a bus with 12
members and connect it to the counter's output, it'll connect Output[15:4]
to my Bus[11:0] given the "left to right" bus pin to bus terminal mapping
rule that the on-line help discusses.  (I wish their on-line help gave a few
more examples... they seem to give examples of exactly the kind of
connection I'm trying NOT to make...)

I'm thinking I need to label the bus connection as something like
garbage[3:0],Bus[11:0] so that the upper four bits just head off into
hyperspace and I get the 12 lowermost bits that I wanted.  However, I'm sure
the software is going to complain if I start creating these orphan nets with
names like "garbade".

Any ideas?  The Xilinx help line guy was trying to tell me that you have to
take that bus and draw 12 bus taps to get what I want, but I had a real hard
time believing that.  He's still checking into it however.

Thanks a lot.

---Joel Kolstad
Joel.Kolstad@USA.Net



Article: 11621
Subject: Re: How to design a PLL
From: "Mirko Kovacevic" <mirko@mediaone.net>
Date: Wed, 26 Aug 1998 23:19:41 -0700
Links: << >>  << T >>  << A >>
Hi Detlef,

Your main problem is the big dividing ratio (10,000). For these dividing
ratios you need reference clock with very, very low jitter. Your output
jitter will be crystal oscillator jitter multiplied with 10,000 plus
additional jitter of the VCO itself. Try to keep the VCO power supply as
clean as possible.

Regards,
Mirko

Justen wrote in message <35E3A88B.7FEBCF88@studm.hrz.uni-siegen.de>...
>Hi,
>
>I would like to build a digital PLL with a XILINX 4010 FPGA. The
>generated frequency should be 9.5MHz to 10MHz in steps of 1kHz. So I
>have to use a 1kHz Referenz (this is also the frequenzy of the
>PhaseDetector) and multiply it with 9.500 to 10.000. At the moment, I
>use a PhaseDetector von Xilinx AppNote and an Integrator to close the
>loop. But this isn't a good design. The PhaseJitter is to big. Could
>anybody help me to improve this design?
>
>Thanks Detlef
>
>------------------------------------------------------------------
>Dipl.-Ing. D.Justen               ______|  _____|   ___|   ___|
>Center for Sensor Systems (ZESS)     __|   __|     __|    __|
>Paul-Bonatz-Str. 9-11               __|    ____|    __|    __|
>57074 Siegen                       __|     __|       __|    __|
>Germany                           ______|  _____| ____|  ____|
>Tel.:       ++49271/ 740-2432
>Fax.:       ++49271/ 740-2336
>E-Mail:     justen@zess.uni-siegen.de
>Homepage:   http://www.zess.uni-siegen.de
>----------------------------------------------------------------
>
>


Article: 11622
Subject: Re: vector product minimization problem
From: benyamin@my-dejanews.com
Date: Thu, 27 Aug 1998 12:13:54 GMT
Links: << >>  << T >>  << A >>

> (on constant vector dot variable vector product logic minimization)I don't
think my
> posts have been much help, you'veput a lot more thought into the topic than I
have
> time to.
> Thanks for an interesting topic though, its been fun
> thinking about.
>
> You might consider extending your investigations
> into (constant matrix)(variable vector). Depending
> on the nature of the constants, there may be many
> redundancies in the calculations that can be exploited
> to produce simpler circuits.
>
> May I ask if the S/W you're putting together is for
> your own use, a commercial product, or are you
> willing to share?
>
> - John
Everyone posting have helped me out a lot, and the discussions have been great
as well.  I think there is a lot more one can do with these ideas, and as John
noted, matrix products can be minimized quite well -- the more coefficients,
the more constant subexpressions, the more minimization.

As shown by Feig and Winograd ("Fast Algorithms for the Discrete Cosine
Transform"), the 8x8 matrix of DCT coefficients can be reduced to two 4x4
matricies.  This was exploited by Woods (working w/ the 6200) and Bergmann (w/
the 4000).  Both authors implemented the dual 4x4 transforms using Distributed
Arithmetic.  Feig used modulo addition/multiplications to illustrate how pairs
of variable terms

 {x(i) + x(k-1-i)} and {x(i) - x(k-1-i)}

can be grouped into subexpressions.  The minimization approach discussed here
does the same thing, but discovers the subexpressions in a "brute force"
manner. Moreover, the truncation caused by fixed point arithmetic introduces
further subexpressions that did not exist in the original cosine terms.

I am submitting a paper discussing this topic to FPGA'99, so you're welcome to
that, which outlines the algorithms used.  I will have to check with those in
power (my advisor(s), DARPA, etc.) about making the source available!

Thanks again,
Dan Benyamin
benyamin@ucla.edu

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Article: 11623
Subject: Re: How to design a PLL
From: Catalin <no@spam.com>
Date: Thu, 27 Aug 1998 08:34:55 -0400
Links: << >>  << T >>  << A >>
One way to lower the jitter is to increase the 1KHz reference. If you still
want the 1KHz resolution your options are:

1. Fractional-N techniques (this requires a DAC). Basicaly, a digital
phase accumulator is used to inject a saw-tooth like waveform into the
PLL loop. A technique introduced by HP (I think) about twenty years ago.

2. Divide both the VCO output and the reference with variable (and much
smaller) numbers. For example (I am assuming a 10MHz reference
frequency):
- for 9.5MHz use 19/20 instead of 9500/10000
- for 9.673MHz use 148/153 instead of 9673/10000 and you will get
9.673203MHz, etc.
Of course there will be frequencies that cannot be approximated by a
fraction of small numbers, for example 9.501MHz. For these just use a
second (or even a third) reference frequency which is not in a small
harmonic ratio to 10MHz. The ratios can be easily computed on the fly
with a modified Euclid algorithm (which can also be implemented in an
FPGA) or they can be precomputed and stored in a ROM table (which might
also fit in an FPGA).

3. Look at the Cypress part ICD2061A (www.cypress.com). It might do
exactly what you want. It is a programmable dual clock PLL generator
used in graphics applications. It has a very wide range and I believe low
jitter. Doesn't require any external components and is programmed trough
a simple serial interface.

Catalin Baetoniu

Mirko Kovacevic wrote:

> Hi Detlef,
>
> Your main problem is the big dividing ratio (10,000). For these dividing
> ratios you need reference clock with very, very low jitter. Your output
> jitter will be crystal oscillator jitter multiplied with 10,000 plus
> additional jitter of the VCO itself. Try to keep the VCO power supply as
> clean as possible.
>
> Regards,
> Mirko



Article: 11624
Subject: Re: Example Code
From: "Willy" <willy@asic.co.za>
Date: 27 Aug 1998 13:25:36 GMT
Links: << >>  << T >>  << A >>
Try http://miles.winlink.no/~tom/hwb/co_ISA_Tech.html



APS <resp@associatedpro.com> wrote in article
<35DECDFF.FA39A3D0@associatedpro.com>...
> check at http://www.associatedpro.com
> 
> G. R. Jeffrey wrote:
> 
> > I am new to the fpga world. I have some Altera flex10k devices that I
> > want to use to implement a routing protocol.
> >
> > Does anyone know where I can get some (simple) example codes that use
> > the ISA bus to interact with fpga/cpld devices. I spent all of
> > yesterday, unsuccessfully, trying to write/read to/from ram on a
device.
> >
> > Also, is there a web site that explains the ISA bus signals?
> >
> > Thanks,
> >
> > Gersham Jeffrey.
> 
> 
> 
> --
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
> Richard Schwarz, President              EDA & Engineering Tools
> Associated Professional Systems (APS)   http://www.associatedpro.com
> 3003 Latrobe Court                      richard@associatedpro.com
> Abingdon, Maryland 21009
> Phone: 410.569.5897                     Fax:410.661.2760
> 
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
> 
> 


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