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On Feb 28, 11:20 am, "radarman" <jsham...@gmail.com> wrote:
> Hello,
> I have a ComBlock 1200 (comblock.com) FPGA board with a Analog Devices
> AD9860 MxFE interface. I'm trying to get the SPI interface up and
> running to configure it.
>
> Right now, I can write to any register. I've tested this by writing
> ramping levels to the aux DACs and watching the output on a scope. I
> also have the entire SPI bus on a scope, and everything looks good.
>
> The problem is reads. Everything reads back 0. I've looked at the MISO
> signal on a scope, and it's there, and properly aligned. I've brought
> it out from the FPGA on a separate test point to verify that I didn't
> mess up the UCF - the signal is making it into the device. I even
> looked in FPGA editor, and the signal is getting all the way to the
> opb_spi block.
>
> Note, I am using the manual select option. The MxFE doesn't like the
> SS line going high between bytes, so I have to wrap each transfer with
> a slaveselect call. This is the jist of what I'm doing:
>
> Status = XSpi_SetOptions( &MxFE_SPI, XSP_MANUAL_SSELECT_OPTION |
> XSP_MASTER_OPTION);
> Status = XSpi_Start( &MxFE_SPI );
> if( Status != XST_SUCCESS ){
> xil_printf("->Error! Failed to configure MxFE SPI Interrupts.\n
> \r");
> return XST_FAILURE;
> }
>
> Status = XSpi_SetSlaveSelect( &MxFE_SPI, 0x1 );
> Status = XSpi_Transfer( &MxFE_SPI, SPI_TxBuffer, SPI_RxBuffer, 2 );
> if( Status != XST_SUCCESS ){
> xil_printf("Whoops! SPI Failure.\n\r");
> return XST_FAILURE;
> }
> Status = XSpi_SetSlaveSelect( &MxFE_SPI, 0x0 );
>
> Note, both SPI_TxBuffer and SPI_RxBuffer are the same length as the
> FIFO depth, but most transfers are only 2 bytes (address & data). ADC
> reads (if they worked) would be three bytes (1 Address, 2 Data) When I
> try to raed, the entire SPI_RxBuffer is empty. (all values the same as
> their initialized values)
>
> Also, the ISR does appear to be working. (Writes work fine, and I can
> see the interrupt signal on the scope)
>
> What could I be doing wrong?
Problem solved.
What I'm doing wrong is not waiting long enough. I didn't realize at
first that the XSPI transfer function is non-blocking.
-Seth
Article: 116051On Wed, 28 Feb 2007 13:45:03 -0800, cs_posting wrote: > On Feb 28, 1:54 pm, "B. Joshua Rosen" > <bjro...@polybusPleaseDontSpamMe.com> wrote: >> I'm trying to use the Altera USB Byte Blaster Cable on Linux (Scientific >> Linux 4.4, i.e. RHEL 4). The Programmer application sees the cable, >> however it says there are insufficient privileges on the port. I've tried >> running Quartus as root, that didn't fix the problem. There is no Firewall >> and Secure Linux is disabled. Anyone have any suggestions? > > Yes, the program needs to call ioperm() on the printer port address > before trying to talk to it. > > Being root (or an setuid root executable) just means you have the > right to make that function call; it doesn't mean it's necessarily > been done. I found the instructions on the Altera site. Thanks anyway.Article: 116052
on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding information on this. Using Impact. thanks!Article: 116053
I can certainly understand the fuzziness as the varying ribbon lengths seem very contradictory. This was one of the factors that lead to the decision to not specify a maximum length. Just from personal observation, I have seen many groups create varying lengths (usually 3 ft or less) of ribbon cable for their specific needs without any problem. It is important to note though that there have been a small number of occasions where a custom length cable did not work for one reason or another. -David "Marlboro" <ccon67@netscape.net> wrote in message news:1172696459.233980.159910@h3g2000cwc.googlegroups.com... > Hi Davide, > > Sorry for my English, I meant it a "dongle" not a thong :))) > Looks like I'm missing you something here. You have a 30ft ribbon > cable working just fine and couldn't make it works at 1ft ? I know > signal integrity is length depedency, but those numbers (30, 1) just > building up my fuzziness > > Regard, >Article: 116054
<mtsukanov@gmail.com> wrote in message news:1172700224.105157.31840@s48g2000cws.googlegroups.com... > on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding > information on this. Using Impact. > > thanks! A blank check gives me carte blanche? Most programmable, non-volatile memories are one-way programmable; that is - when erased - all bits are one polarity and programming involved programming only the bits that are the opposite polarity. This means that some meory can simply be "added to" but almost all of the time a new program involves changing some of the programmed polarities back to erased polarities. Erasure can only occure on a block or device level for most of these devices. The blank check tells you the reprogram *can* be successful because there are no unerased bits left that will need the erased status. It's easier to check for the entire erasure than for just the bad bit polarities. - John_HArticle: 116055
"Fred" <fred@n0spam.com> wrote in message news:1172664477.23596.0@proxy00.news.clara.net... > I'm writing the initial state machine for a PCI-Express card and am stuck > at the very first hurdle. I'm using a Philips PX1011 PHY and I'm able > detect the receiver on the motherboard. > > I then send it TS1s with pad characters in the Link and Lane numbers but > the motherboard transmitter doesn't transmit TS2 but instead goes into > idle state. I'm convinced that correct serial data is coming out of the > PHY. There's no need for speed negotiation since both are advertising the > slowest speed. > > I would be grateful if anyone here could help. > > If you designed/developed the board are you sure that you didn't simply swap Rx and Tx? You wouldn't be the first to do that! How are you debugging this? Do you have equipment connected (oscilliscopes or logic analyzers) that let you directly observer the link (differential pairs) or are you inferring what is going on? You didn't say if the motheboard transmitted TS1s, or not. If the motherboard DID NOT transmit TS1's then the motheboard probably didn't succesfully "detect" your board (i.e. never exited the detect state and never entered the polling state). If the motherboard did transmit TS1s and then eventually went back to electical-idle then it probably isn't receiving your TS1s correctly (and it is configured to NOT go into "compliance mode"). TCArticle: 116056
"Marlboro," The mystery is actually caused by reflections on the cable. If the reflection returns at exactly the wrong moment, the bits are confused. The reflection is the incident wave hitting the receiver, bouncing back to the transmitter, and bouncing back (again) to the receiver. If you has a signal integrity simulation program (eg Mentor's Hyperlynx), you could actually simulate this effect, and see it happening. Another consideration is that ribbon cable will couple (cross-talk) to itself if it is rolled up on itself. We have see the cable not working, unrolled it, spread it out over the floor, and it then works just fine. Try reading: http://www.ibiblio.org/kuphaldt/electricCircuits/AC/AC_14.html or http://www.tpub.com/content/neets/14182/css/14182_109.htm or one of the many resources on the web for transmission line theory. AustinArticle: 116057
mtsukanov@gmail.com wrote: > on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding > information on this. Using Impact. 'blank check' means it checks the device is erased, ready to be programmed. Normally used in a re-cycle situation, when you want to program new code into the CPLD, you go along this chain of operations : Erase/BlankCheck/Program/Verifty/Secure/VectorTest Commonly devices are shipped blank, so the first 2 are optional on a new device, but required on a already programmed device. -jgArticle: 116058
John_H wrote: > At least there's a stake in the sand. > > And as complex as the pricing is, it isn't as complicated as airline ticket pricing :-0Article: 116059
Tim wrote: > Ray Andraka wrote: > >> Tim, I am failing to see it. >> If you are building a 16x32K memory, for example, you could do it >> with 32 16Kx1 plus 16 2:1 muxes, or you could do it with 32 1Kx18 >> BRAMs plus 16 16:1 muxes, which occupies about 3x the number of LUTs. >> Same number of BRAMs, more logic. > > Yes. But the power consumption can also vary depending on how many BRAMs > are active. It depends on the BRAM implementation and I haven't looked > at the V4 case. By effectively freezing most of the BRAMs at any moment, > the power hit goes down. It's the same with external SRAM and DRAM, > where the power consumption goes up and down with the number of banks > active, the number of RAMs active, and the read/write/refresh state. External SRAMs usually completely disable themselves after they are deselected and the last burst has ended. Assuming the BRAM functional schematics from the V4/V5 specifications are architecturally accurate for the few details shown, it seems that each BRAM port's address registers (and the address decoder they happen to sit in front of) operate regardless of the port's 'enable' signal which appears to only control read, write and output latch operations - not address decoding. If so, the only ways to completely 'suspend' a V4/V5 BRAM (prevent internal activity) would be to either stop the clock (regional clock mux?) or freeze addresses (+data for extra nanowatts, maybe) before the BRAM's. Both approaches imply an extra wait state before accessing a disabled BRAM (can be hidden by pipelining BRAM controls) and the second one would also cost way too many extra FFs/routing, most likely undoing any savings from that second approach in the process. I think the clock gating with 16:1 BRAM mux approach would have the highest chance of achieving measurable power reduction. On the V5, this might be an even better candidate: 36kbit BRAMs mean half as many BRAMs to mux/control and six input LUTs enable fast, efficient, single-slice 2x(8:1) muxes. In any case, it sounds like quite a bit of trouble only to optimize tens of microwatts away from the bottom line. --- Is LUT6 the greatest thing since sliced bread? Maybe not - but finally having single-LUT 4:1 muxes is certainly great.Article: 116060
"Tim" <tim@nooospam.roockyloogic.com> wrote in message news:es4a0k$f0t$1$8302bc10@news.demon.co.uk... > Symon wrote: > >> The other choice that I can think of is to use an interposer to connect >> the FPGA to the board. I read recently about magic elastomer materials to >> connect BGA to PCBs with excellent SI properties. > > Is that the Samtec stuff? Wasn't in their catalog last time I looked. Hi Tim, I've looked for that after Teraspeed referenced it in an article and, like you, not found it yet. I was looking at something else the other day that had an elastomer with tiny wires in it like this:- | | | | | | | | | O O O O O O O O O | | | | | | | | | O O O O O O O O O | | | | | | | | | O O O O O O O O O | | | | | | | | | So, vertical lumpy wires. When you used it the wires deformed :- / / / / / / / / O O O O O O O O \ \ \ \ \ \ \ \ O O O O O O O O / / / / / / / / O O O O O O O O \ \ \ \ \ \ \ \ A bit more higgledy-piggley than that! Each PCB pad/ BGA ball used several of these wires to make the contact, like a zebra strip in LCD connectors. Sadly, I can't remember the link. Anyone else see it? Cheers, Syms.Article: 116061
So if I understand the datasheet well, the flash device is just brought in the same package, isn't it? It even seems to be an Atmel DataFlash (R) device. At the end .. the big winner is ... Atmel. They are now delivering configuration devices to both Xilinx and Altera. Probably this is one of the reasons that they are stepping out of the PLD business. (at least this is what I heard) One thing to be mentioned - no 'instant on' feature with the S3-AN as the boot time is still in the 100ms range - as with normal SPI flash. I agree - being pin compatible with S3-A is a feature, no migration path between densities however is not so nice. In other words, I need more to convince me to switch over ... Luc On 27 Feb 2007 10:45:46 -0800, "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> wrote: >On Feb 27, 10:36 am, Jim Granville <no.s...@designtools.maps.co.nz> >wrote: >> Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: >> >> >> >> > * Pin-compatible with select members of the Spartan-3A FPGA family >> > + Architecturally identical to Spartan-3A FPGA family >> >> This last point would seem important. So if one places external flash >> alongside a 3A, (That flash being larger, or smaller, (or faster?) than >> the in-package Flash of 3AN) you get all the same Flash-access features ? >> >> -jg > >Correct. You have many of the same Flash size advantages by >connecting an external Flash to a Spartan-3A device. Obviously, >however, it is no longer a single package. The Spartan-3AN In-System >Flash memory requires no user-I/O pins. Instead, all access is >through an internal design primitive called SPI_ACCESS. > >I should also mention that Spartan-3AN FPGAs still support _all_ the >other Spartan-3A configuration modes (Master Serial, Master Parallel, >Slave Serial, etc.). Spartan-3AN FPGAs exclusively offer the Internal >Master SPI mode. > >-- Steve KnappArticle: 116062
Hi, If you know how to write your framing and encoding for SONET you might get there with V4, otherwise look for other solutions - better documented, proven technology, etc... Luc On 28 Feb 2007 10:18:21 -0800, "comp.arch.fpga" <ksulimma@googlemail.com> wrote: >On 28 Feb., 18:52, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: >> comp.arch.fpga wrote: >> > Is there anybody in this group who has experience with V4FX MGT Sonet >> > Alignment? >> >> > The documentation is rather short on details. The interaction of the >> > two alignment stages is not clear to me at all. >> > What we see is that we get a comma detect signaled and the output data >> > stream is correctly aligned. >> > As a reaction on that we turn offENPCOMMAALIGNand ENMCOMMAALIGN. >> >> > But nevertheless the MGT keeps realigning on any new occurence of the >> > comma pattern. >> > (only the bits are shifted around, there is no new comma detect >> > signaled.) >> >> TheENPCOMMAALIGNand ENMCOMMAALIGN are for 8b10b encoded steams >> which are not used by SONET. >> >> Ed McGettigan >> -- >> Xilinx Inc. > >According to Table 3-18 in ug076 the attribute ENMCOMMAALIGN controls >the byte aligner and ENPCOMMAALIGN controls both the byte aligner and >the SONET aligner. > >According to that table when ENxCOMMAALIGN = '1' the byte aligner >should "realign byte alignment mux when the A1 symbol is found on a >non-byte aligned boundary". >That is exactly what we see happening even tens of clock cycles after >we set ENxCOMMAALIGN = '0'. Instead we require it to "hold alignement >mux position" as it should according to documentation. > >Kolja SulimmaArticle: 116063
lb.edc@telenet.be wrote: > So if I understand the datasheet well, the flash device is just > brought in the same package, isn't it? It even seems to be an Atmel > DataFlash (R) device. > At the end .. the big winner is ... Atmel. They are now delivering > configuration devices to both Xilinx and Altera. Probably this is one > of the reasons that they are stepping out of the PLD business. (at > least this is what I heard) I don't think Atmel are exiting the PLD business - their recent releases in the CPLD ATF1502BE / 1504BE devices can foot it with the best. Most of their SPLD/CPLD have RoHS versions. I can see they are more of a fading force in the FPGA area, with the road map there thinner, and not all devices are RoHS, so no, they are not going to threaten a Xilinx Spartan-3AN :) That said, I know customers that still buy Atmel EPROMS, and most of those are also now RoHS. > One thing to be mentioned - no 'instant on' feature with the S3-AN as > the boot time is still in the 100ms range - as with normal SPI flash. > > I agree - being pin compatible with S3-A is a feature, no migration > path between densities however is not so nice. > > In other words, I need more to convince me to switch over ... The improved coupling between Flash and FPGA is a good thing, in both the 3A and 3AN series. It also reduces the pcb footprint, and has to reduce RFI issues, in those designs that continually access the flash. It's also a soft-border : you can design to use both 3A and 3AN. -jgArticle: 116064
On Feb 28, 3:59 am, lkj...@gmail.com wrote: > Hello. > > To improve the speed, I want to implement pipeline.But variables make > me sad... > > For example > > -- input: IN1,IN2 , output:OUT > signal A,B,C; > process(clk) > variable V_1,V_2,V_3; > begin > V_1 := IN1 > A <= V_1 > V_2 := A > B <= IN2 > V_3 := B+V_2 > C <= V_3 > OUT <= C > end process; > > Is there anyone who can break down above process? How many stages did your professor want you to pipeline this to? My best advice is, variables are a fact of life, don't dwell on them. Focus on the things that make you happy, like beer.Article: 116065
Symon wrote: > I've looked for that after Teraspeed referenced it in an article and, like > you, not found it yet. I was looking at something else the other day that > had an elastomer with tiny wires in it <<snipped>> I'm pretty sure that general design has been around for 10+ years, and my memory is that Samtec had an unsuccessful crack at productizing it some time ago. It's about time they tried again! -- TimArticle: 116066
mtsukanov@gmail.com wrote: > on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding > information on this. Using Impact. It reads back the program from the device and checks that the device is blank. That used to mean checking that all the bits were set to '1'. No doubt devices are more complicated now.Article: 116067
Daniel S. wrote: > In any case, it sounds like quite a bit of trouble only to optimize tens > of microwatts away from the bottom line. It has been 5 years since I did that sort of design, but at the Spartan-2/2e generation the power savings were not microwatts - they dominated power consumption on a 100MHz design. Could have been a design wrinkle - my designs have been known to have wrinkles! It would be interesting to hear from Peter or Austin what the situation is now - if ENA is deasserted, does BRAM power drop right down? This may be answered in the User Guides - I'll get to read them one day...Article: 116068
Hi, My first recommendation would be to avoid mixing signals and variables unless absolutely necessary because the two have different update policies. Variables are updated on-the-fly or "in program order" while signals are updated with the last written value only after all triggered processes have been evaluated. Assigning a value to a signal from within a synchronous process will always infer FFs. Results with variables may vary wildly from one synthesis/simulation tool to another and how they get interpreted is also highly dependent on how the code is arranged. Using signals exclusively avoids introducing unnecessary confusion. Since ISE supports register balancing and a few other related options that will automatically move FFs up and down combinational logic paths to improve timing margins, you can try adding registers in front and after combinational blobs. Most of the time, ISE does a decent job relocating two or three register levels. This is not ideal for bleeding-edge results but is worth a shot to nudge large-ish combinational blobs into timing margins without having to untangle them (or at least postpone that with minimal effort if possible) for explicit pipelining. lkjrsy@gmail.com wrote: > In order to improve the performance, I try to implement the pipeline. > But variables make me sad. > > For example. > > -- Input: IN1, IN2 / output : OUT > signal S1,S2,S3 > process(clk) > variable V1,V2,V3 > begin > V1 := IN1 > S1 <= V1 > V2 <= S1 > S2<=IN2 > V3:= S2+V2 > S3 <= V3 > OUT<= S3 > end process; > > is there anyone with idea about this? >Article: 116069
So do you mean that I can ignore these warnings? On 2=D4=C227=C8=D5, =CF=C2=CE=E74=CA=B157=B7=D6, "Benjamin Todd" <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > normally you wont have specified any time constraints on the reset signal= .=2E. > I aam assuming you have a global asynchronous reset. > > To correctly manage the reset you should try to synchronise it to the > internal clock using a couple of flip-flops. This way it ensures a > synchronous release of the reset that can be treated and analysed in the > same way as any other. I think you may still get the warnings for > violations of the first asynchronous input. > > Anyways, the idea of synchronous vs asynchronous reset is a long discussi= on > =3D) > > Ben > > "skyworld" <chenyong20...@gmail.com> wrote in message > > news:1172557239.722343.245410@p10g2000cwp.googlegroups.com... > > > Hi, > > I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I > > checked the timing report. Everything is ok, and there is no timing > > violations. But when I run post simulation, the modelsim reports some > > timing errors for some registers with $recovery(...). I checked the > > time when these errors occur. They happened to be the time when reset > > is de-assertion. I tried to change reset period, but this time other > > register report $recovery/$setup/$hold errors. It is very strange > > because I have passed P&R, there is no timing violations, why does > > these errors orrur? Can anybody help me? thanks very much.Article: 116070
Rob wrote: > The question I have is can you use the platform flash as a means to > hold your MicroBlaze code and have a boot loader grab from it? Check out xapp 482 (Storing User Data/Code in Platform Flash Images). Haven't tried it myself but seems to be supported in some form or other. http://direct.xilinx.com/bvdocs/appnotes/xapp482.pdf Regards, JohnArticle: 116071
Hi, I am going through the net to download CAN VHDL core. HurriCANe is removed from the ESA site, and the link in opencores site for VHDL CAN core is going to some odd page. can you please guide me on where i can download this or if anyone does have these free versions can you mail me ? Thank you for your time rajuArticle: 116072
Hello,
I'm getting usual results from my BUFR network in Timing Analyzer:
<SNIP>
--------------------------------------------------------------------------------
Hold Violations: TS_adc1_dclk_p = PERIOD TIMEGRP "TG_adc1_dclk_p" 4 ns
HIGH 50%;
--------------------------------------------------------------------------------
Hold Violation: -0.974ns (requirement - (clock path skew +
uncertainty - data path))
Source: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7
(FF)
Destination: adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7
(FF)
Requirement: 0.000ns
Data Path Delay: 1.275ns (Levels of Logic = 0)
Positive Clock Path Skew: 2.249ns
Source Clock: adc1_dclk rising at 0.000ns
Destination Clock: adc1_dclk rising at 4.000ns
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 to
adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.268 adc1_reg_inst/nshifts_gen[1].dff_ins/
d_r_7
net (fanout=1) 1.065 adc1_reg_inst/d_array<2><7>
Tckdi (-Th) 0.058 adc1_reg_inst/nshifts_gen[2].dff_ins/
d_r_7
---------------------------- ---------------------------
Total 1.275ns (0.210ns logic, 1.065ns route)
(16.5% logic, 83.5% route)
</SNIP>
2.25 ns positive clock path skew? Omg!? So, then I looked at the
partially PAR'ed output on this SX55 FPGA. Turns out the stupid tools
are expanding the BUFR network across multiple BUFR regions, including
horizontally (x direction). I have an 8k FIFO (necessary) to
transition from this BUFR clock to a slower BUFG clock. Looks like the
tools are placing the FIFO on the left side of the FPGA and the top-
right BUFR is using non BUFR resources (I assume) to route the clock
across.
Is this what's causing my enormous clock path skew? I will try to
apply some area_group slice/bram constraints to my FIFOs, but I find
this to be an extreme pain in the butt... I'm using a COTS board,
which is configured with 4 ADC data channels and 4 ADC clocks. The ADC
data is about 180 degrees out of phase w/ the clock (fine). Is there a
way to constrain nets/instances/etc. to a regional clock region?
That'd be really sweet...
Is there a better way to transition from the regional clock to a
global clock other than using a FIFO? This is giving me a headache b/c
my design takes forever to PAR and I can't meet timing :(
Thanks,
-B
Article: 116073On Feb 27, 2:42 pm, Tim <t...@nooospam.roockyloogic.com> wrote: > Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > > > I am pleased to announce that the Spartan-3AN FPGA family is now > > officially out in the open. Full technical literature is now > > available on the Xilinx web site. > > Can you summarize the availability picture for the various parts for > prototype quantities and for production quantities? Samples of the XC3S200AN, XC3S700AN, and XC3S1400AN FPGAs are available now through Xilinx sales partners, typically with 4 week leadtime. http://www.xilinx.com/onlinestore/silicon/online_store_s3an.htm The XC3S50AN and XC3S400AN are still to come, likely within the next 90 days. If you click on the Avnet and NuHorizons web sites, you'll likely see a "No Stock, Please Call" message. I encourage you to "please call". Please allow me to shed my Xilinx mantle and speak OPINION. <opinion>Xilinx distributors do not carry stock on Engineering Samples because Xilinx maintains a "non-cancellable, non-returnable" policy with the distributors. Distributors have no incentive to stock inventory and consequently carry no inventor on engineering samples. All orders for engineering samples are placed with Xilinx as they come in.<end opinion> I'd highly recommend downloading ISE 9.1i, Service Pack 2 (available now) before starting a design. Service Pack 3 (mid March/early April) will have improved in-system programming support. http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp -- Steve KnappArticle: 116074
I have a project that need dma support and after I read some document and code in Xilinx EDK, I'm confused by dma support of ipif core, anyone had use it and give some suggestion ? Or Xilinx can say something about it ? Thank you!
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