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On Mar 15, 5:20 pm, "MM" <m...@yahoo.com> wrote: > It probably has to do with your choice of trigger condition. Does anything > happen when you click on Trigger Now button? > > /Mikhail I tried but nothing happened, it alway gave me that message.Article: 116701
On Mar 15, 5:35 pm, "MM" <m...@yahoo.com> wrote: > "Rebecca" <pang.dudu.p...@hotmail.com> wrote in message > > news:1173990547.149492.274780@y80g2000hsf.googlegroups.com... > > > I tried but nothing happened, it alway gave me that message. > > That was the button with the exclamation mark, right? > > Did you use Chipscope inserter to instantiate the core or did you do it > manually through HDL? The reason I am asking is because it is much easier to > connect something wrong if you do it yourself... > > /Mikhail Yes, thant is the button with the exclamation mark. And I used chipscope inserter. ThanksArticle: 116702
stephen.craven@gmail.com wrote: > If you were analyzing a newer part, you could make use of 'debit', a > tool available from http://www.ulogic.org/trac. > I have only given it a cursory look, but it appears to reverse a > bitstream into a custom textual netlist. So additional work would be > required to take it to EDIF, XDL, or the like. But it does draw > pretty fpga_editor-like pictures from bitstreams. On the other hand, the older parts were smaller. Maybe small enough that it could be done partly by hand. If you had some idea what the logic was supposed to do, that would help. -- glenArticle: 116703
It probably has to do with your choice of trigger condition. Does anything happen when you click on Trigger Now button? /MikhailArticle: 116704
Peter Alfke wrote: > John is of course right. Memories have no global or parallel clear. > Such a clear would require an extra input to every data storage cell, > plus a wire interconnecting these inputs. Too expensive and too slow > in the highly competitive high-density RAM market. I remember wondering some years ago (in the 8080 days) if SRAM tended to power up to the same state. It seemed that the screen image on power up, before the software cleared the screen, tended to be similar. While a clear would be expensive, designing memory cells, either SRAM or DRAM, to power up in a certain state might not be as expensive. I don't know that anyone has tried, though. I also remember discussions about EPROMs that erase to either 0 or 1, and which processors have opcode X'00' as NOOP. -- glenArticle: 116705
"Bob Golenda" <bgolinda@nospam.net> wrote in message news:NNdKh.367$B61.242@newsfe06.lga... > Hi Marc, > > Have you actually done this and gotten it to work? > > Thanks! > We have it working. I say "we" as it was mostly my software colleague's effort:) Apparently it took him a day or less to port the code from the appnote to PPC in V4, which we have been using. We are programming Xilinx Platform Flash on a slave board using this method. /MikhailArticle: 116706
"Rebecca" <pang.dudu.pang@hotmail.com> wrote in message news:1173990547.149492.274780@y80g2000hsf.googlegroups.com... > > I tried but nothing happened, it alway gave me that message. > That was the button with the exclamation mark, right? Did you use Chipscope inserter to instantiate the core or did you do it manually through HDL? The reason I am asking is because it is much easier to connect something wrong if you do it yourself... /MikhailArticle: 116707
On Mar 15, 6:01 pm, "MM" <m...@yahoo.com> wrote: > > Yes, thant is the button with the exclamation mark. > > And I used chipscope inserter. > > Then it does sound like a clock problem... Open the design in the FPGA > editor and see if the clock really makes it to the core... > > /Mikhail Hard to see in the editor. But I noticed when I load the input netlist file which is targeting on virtex5, the inserter didn't recongnized it and I have to changed it manually from virtex4 to virtex5. If I don't change this setting, it can still generated the .ngo file. Is there any problem?Article: 116708
AdamE wrote: > Sorry for the slow reply - winter colds stink ;) I was actually > hoping to get a list of the synthesized logic equations prior to > conversion to the Xilinx primitives. I was able to get an EDIF > netlist but that's a bit too far down the tool chain as what I want to > look at is the optimized Boolean logic. Is that possible? I seem to > recall that generic vendor tools like Synplify had the ability to > export such information prior to the selection of a target technology. I've never tried this, but to get the sum of products I guess you can tell the tools that you are synthesizing for a big PAL? I don't know how to get the SOP, factorized for the X architecture. But someone will step in if there's a way.Article: 116709
> Yes, thant is the button with the exclamation mark. > And I used chipscope inserter. Then it does sound like a clock problem... Open the design in the FPGA editor and see if the clock really makes it to the core... /MikhailArticle: 116710
Glen, ten or fifteen years ago, it was possible to design latches = memory cells in a slightly asymmetric way, so that they were guaranteed to power-up in a specific state. That's what Xilinx did originally with the many configuration memory cells. With smaller geometries, this "trick" became unreliable, and Xilinx had to find a different way to power up without massive contention. And we found :-) Playing analog tricks becomes increasingly more cumbersome (and unreliable) as we now are deep, deep in sub-micron territory. Peter Alfke, Xilinx Applications On Mar 15, 2:22 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Peter Alfke wrote: > > John is of course right. Memories have no global or parallel clear. > > Such a clear would require an extra input to every data storage cell, > > plus a wire interconnecting these inputs. Too expensive and too slow > > in the highly competitive high-density RAM market. > > I remember wondering some years ago (in the 8080 days) if SRAM > tended to power up to the same state. It seemed that the screen > image on power up, before the software cleared the screen, tended > to be similar. While a clear would be expensive, designing memory > cells, either SRAM or DRAM, to power up in a certain state might not > be as expensive. I don't know that anyone has tried, though. > > I also remember discussions about EPROMs that erase to > either 0 or 1, and which processors have opcode X'00' as NOOP. > > -- glenArticle: 116711
glen herrmannsfeldt wrote: > Peter Alfke wrote: > >> John is of course right. Memories have no global or parallel clear. >> Such a clear would require an extra input to every data storage cell, >> plus a wire interconnecting these inputs. Too expensive and too slow >> in the highly competitive high-density RAM market. > > I remember wondering some years ago (in the 8080 days) if SRAM > tended to power up to the same state. It seemed that the screen > image on power up, before the software cleared the screen, tended > to be similar. While a clear would be expensive, designing memory > cells, either SRAM or DRAM, to power up in a certain state might not > be as expensive. I don't know that anyone has tried, though. DRAMs do not guarantee any specific power-up value but because they are built on femtofarad capacitors and somewhat leaky silicon, they should have a tendency to power-up mostly cleared. For SRAMs, I suspect results would indicate that they tend to power up with a specific device-unique pattern dictated by either the leakiest or strongest transistor in each bit and, given low-leakage transistors, it is not inconceivable that they may power-up biased towards their former power-on state. Guaranteeing that an SRAM cell will always power-up cleared (without Peter's clear input and the extra cell transistors) would require making the SRAM cell leaky by design and that would be really bad for static power usage. While this "solution" does not cost any surface area, it would cost some power and decrease manufacturability: devices that would fail to power-up with all memories cleared but are in otherwise perfect working order would be out-of-spec and have to be either scrapped or sold as "dirty power-up" parts that consume something like 1W extra static power for no reason. 1W may be nothing to you but some people are working on low-power FPGA applications and would not dare touch such parts with a broomstick. There aren't many applications where garbage memory content at power-up is a major issue and for the few cases where it may be so, there usually are a few simple work-arounds like having one reset for memories that need clearing and a second for everything else that gets stretched until the memory clearing processes are done. > I also remember discussions about EPROMs that erase to > either 0 or 1, and which processors have opcode X'00' as NOOP. EPROMs work by trapping a charge in the matrix's isolated gate transistors. The UV exposure increases the cells' leakage current to clear the device while programming is done by "controlled failure" of the isolated gate to program 1s, this is why EPROMs have somewhat low reprogramming endurance.Article: 116712
I've tired using the Xilinx 'partition' feature several times now with
very mixed/negative results.
I tried partions again today with the 9.1.2 s/w and it dies with an
unhelpful message:
DeleteInterpProc called with active evals
This application has requested the Runtime to terminate it in an
unusual way.
Please contact the application's support team for more
information.
Process "Place & Route" failed
My FAE tells me Xilinx wants the HDL source to help resolve this
problem - this
can't happen since a chunk of it is highly proprietary.
a) has anyone else seen this and found a work-around?
b) has anyone had a positive experience with partitions?
Please don't suggest trying SmartGuide - it has it's own set of
problems
with this design.
John Providenza
Article: 116713On 3=D4=C214=C8=D5, =C9=CF=CE=E72=CA=B121=B7=D6, Mike Treseler <mike_trese.= .=2E@comcast.net> wrote: > kangwei...@gmail.com wrote: > > Error (10334): VHDL error at tap.vhd(82): entity "tsb" is used but not > > declared > > The *entity* tsb is missing. > That is causing the error. > You can not do this tsb instance: > > TSB_1 : tsb port map(clk, Read_Data, tsb_out, First_oct); > > without a tsb entity. > > Next time consider using direct instances > instead of components. > > -- Mike Treseler thank you for your help ,i have solved the problemArticle: 116714
On 15 Mrz., 22:26, "MM" <m...@yahoo.com> wrote: > "Bob Golenda" <bgoli...@nospam.net> wrote in message > > news:NNdKh.367$B61.242@newsfe06.lga... > > > Hi Marc, > > > Have you actually done this and gotten it to work? > > > Thanks! > > We have it working. I say "we" as it was mostly my software colleague's > effort:) Apparently it took him a day or less to port the code from the > appnote to PPC in V4, which we have been using. We are programming Xilinx > Platform Flash on a slave board using this method. > > /Mikhail yes, I have ported XSVF player too. was to coldfire embedded linux. the porting itself is simple, and it pretty easy solution when storage is readily available. if the FPGA system doesnt run linux and only has small amount of available ram and no nonvolatile storage and no network and no high speed connections to any hosts, then its more efficient to program the XCF from bit file directly as then there is no overhead of the XSVF involved. this is unfortunatly a bit more than 1 day of work. well at least when doing it first time. Actually my first time was almost a month. but that was long time ago when xilinx had not even published the XCFxxP BSDL files yet. now its more info available so its a bit simpler to get going. and yet still Xilinx has not and will never publish the XCF programming specifications so its a bit RE and testing involved to get all timeouts correctly etc, as there is no reference datasheet for then existing :( AnttiArticle: 116715
"MM" <mbmsv@yahoo.com> wrote in message news:55toioF26p89uU1@mid.individual.net... > > "Bob Golenda" <bgolinda@nospam.net> wrote in message > news:NNdKh.367$B61.242@newsfe06.lga... > > Hi Marc, > > > > Have you actually done this and gotten it to work? > > > > Thanks! > > > > We have it working. I say "we" as it was mostly my software colleague's > effort:) Apparently it took him a day or less to port the code from the > appnote to PPC in V4, which we have been using. We are programming Xilinx > Platform Flash on a slave board using this method. > > /Mikhail This is using XSVFPlayer? How many M Bytes is the file? Don't you have to actually do an output of the file and record that, and then use XSVFPlayer?Article: 116716
I have ported a project that was developed on an ML401 Virtex4 board over to an Avnet Virtex4 PCI-E board. The ML401 uses a V4LX25 and the Avnet board uses a V4FX60. The only changes I made to the project had to do with just reassigning signals in the UCF. I have 2 DCM's in the project. Each DCM's lock signal is routed out to an LED on the board. Each DCM's output clock is routed to a header pin (as well as elsewhere in the design). After configuration (or after a pushbutton RESET to the FPGA) the lock LED's light and the output clocks are valid. This lasts about half a second. Then everything goes dead. So lock is high and valid clocks are output for at least hundreds of thousands of cycles. Then nothing. I can press the RESET button (resets the DCM's -- their lock's are used to distribute sync resets to the rest of the logic in the design) and the lock LED's light and the clocks are valid -- again, only for about half a second. One difference I noticed is that the ISE reports that the DCM hierarchical names have changed due to DCM Autocalibration. There are also multiple refences to this DCM autocalibration in various reports. I have never heard of this, and I can't find info on Xilinx site. Is there something different that happens with DCM's on V4FX parts compared to V4LX parts? I have checked Avnet app notes on this board. Their UCF doesn't have anything special in it that I overlooked. This is a weird problem I haven't looked in to very hard. Thought I would ask here to see if it is a bonehead move on my part : ) Thanks!Article: 116717
Sorry, it is late. The subject should be DCM AutoCALIBRATION not Autoconfiguration.Article: 116718
I should try searching for the correct term. I've found the info on Xilinx' site. I still don't know why the thing is failing though....Article: 116719
Hi, I have a design that is implemented on the Virtex4 and it consumes 69 FIFO16/RAMB16s. I hope to be able to implement it on a Spartan 3E evaluation board but clearly, it is not enough as the 3E only has 36Block rams My evaluation board has 4 DDR SDRAM of 512MBit, can I use those instead of the insufficient block rams? Cheers, KenArticle: 116720
I have created a simple project using Microblaze v4.0a and I use XESS XSA 3S1000,XStend v3.0 board. The project only had a seven segment LED pripherial (I used GPIO IP). The EDK8.1i software worked well. Then I downloaded the bitstream file (...\implementation\download.bit). XSTools v4.0.6 was ok, but the board did anything .When I used iMPACT, it showed an error "An error appears in the status register; the CRC Error bit is NOT 0", and couldn't to download to FPGA. Anyone please give me information about this problem ? Thank in advance!Article: 116721
"Bob Golenda" <bgolinda@nospam.net> wrote in message news:etmKh.242$ED5.20@newsfe04.lga... > > This is using XSVFPlayer? How many M Bytes is the file? Don't you have > to > actually do an output of the file and record that, and then use > XSVFPlayer? > We don't really care much about how big is the file as it gets downloaded from an external server when needed and the whole purpose of this is a rare in-field hardware upgrade. /MikhailArticle: 116722
I have to work again on an old project started 2004 with Quartus v3.0. Now I'm working with the actual v6.1. There are a lot of files in the project-directory :-((( therefore I want to clean up now. does someone know, if the files with this extensions are necessary or old ones: project.csf project.dpf project.eco project.esf project.fld project.psf project.ssf project_assignment_defaults.qdf I think, I only need: project.cdf project.qpf project.qsf project.qws Is this right? I don't want to erase files, and recognize in a few month that they were necessary! Thanks, ManfredArticle: 116723
I want to generate sgmii interface with coregen. I choose this IP-"Ethernet 1000BASE-X PCS/PMA or SGMII" , when i generate, I never find sgmii interface except sgmii_clk signal. So i want to ask where is the serial data bus? Thank you!Article: 116724
Rebecca wrote: > Hi, All > > The ChipScope gave me the message "Waiting for core to be armed" while > the program can run on the board at the same time. <snip> I had this problem using the USB cable and having the JTAG clock set too high. Try using a lower JTAG clock setting... Rob
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