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On Mar 26, 5:34 am, "Paul Leventis" <paul.leven...@gmail.com> wrote: > > The point is that it is this kind of unpredictable behavior between > > releases of the tools that give us cold feet when it comes to moving > > an existing project to a new release of the software. > > Hi Sanjay, > > Yes, there are always risks moving between versions of software. We > spend literally months between when we're finished programming a > Quartus II version and when we actually release it. That time is > spent running tons of tests -- every single old test we have lying > around, plus a bunch of new ones we write to cover new cases. > However, we cannot cover every possible form of input to the tool. > Did you file a bug report on your issue? Bug reports turn into new > tests that get run with each release, filling holes in our code > coverage. > > In your case, was it a relatively small piece of code whose synthesis > changed? Or was it a complex piece of code? I don't know if in this > case it was a bug (somebody broke inferencing?) or just a subtle > change in the myriad of choices/trade-offs the synthesis tool must > make. > > One approach to reduce the amount of change between releases is to > lock down the version of your synthesis tool -- be it Quartus or a 3rd > party tool. But you can continue to update your Quartus back-end to > get the latest & greatest P&R, timing, features, etc. I like to think > the *stability* and overall quality of Quartus does not degrade from > release to release -- in fact, as measured by number of IEs (internal > errors) per compile as reported by users, it has been steadily > improving. > > As suggested by yourself and another poster, sometimes the best > approach is to lock down to one version of the software for your > entire design cycle. We certainly have customers who do this. When > the family you are designing to is reasonably mature (for example, has > Final timing models), this may be the best solution. Or you could > take the Microsoft user approach -- wait until the first Service Pack > release when any of the little problems have been shaken out! > > Regards, > > Paul Leventis > Altera Corp. Hi Paul, In my case, the piece of code was just a simple signed 14x10 bit multiplier with some muxes around it - I'd say about 200 lines of verilog. BTW, I am guessing that one way to lock down QII as synthesis tool would be to generate intermediate files after the synthesis stage with old version of QII and then feed those files into the latest version of QII for back-end. Did you have any other way to do it? Thanks. Best, -sanjayArticle: 117201
On Mar 26, 3:19 am, psihode...@googlemail.com wrote: [...] > > So, any idea, how can we change this situation? Pick a project and help! Just one suggestion: http://iverilog.wikia.com/wiki/Main_Page Cheers, GuenterArticle: 117202
psihodelia@googlemail.com writes: > Today I see no alternative to use Xilinx or Alteras Web Packs. Both > are in a very sad state. As Linux or PowerPC user you cannot develop > your FPGA design with this tools. I'm using the Xilinx tools on Linux (but on x86, not PowerPC), and they seem to work fine for me. I haven't yet used the Altera tools on Linux, but I've been told that they work fine also. > On x86 or on Windows they are very > buggy, slow, and unproductive as well. On Linux x86 they don't seem buggy, slow, or unproductive. Well, maybe slow, but that's a subjective thing. What's the basis for comparison? > So, any idea, how can we change this situation? I doubt that you're going to see tools natively hosted on PowerPC, especially now that Apple has gone to x86. But Xilinx seems to take bugs and performance very seriously. > Will we meet the time > of Open Source development tools for programmable logic devices? Maybe someday, but not soon. Even if Xilinx and/or Altera did make the details of the internal architecture and bitstreams public, developing a complete FPGA tool chain appears to be a task at least three orders of magnitude larger than building a C++ tool chain, and there aren't that many open source C++ tool chains. I don't want to single out anyone in particular, but there seems to be a whole lot of relatively unfounded criticism of the Xilinx software in this newsgroup. It's true that I've found bugs in it from time to time, but I've been able to work around them, and Xilinx support has been quite helpful. I'm not aware of any other comparably sized piece of software that is particularly more robust. I think constructive criticism of the software is worthwhile, but just saying that it is too slow and buggy to use is clearly both unhelpful and factually incorrect. EricArticle: 117203
Dear users Thank you for your reply. I found that my problem lies in the state machine it self, so i basically removed the RAM from my project and ran the synatizer using quartus. The warning message has slighted change but may be its caused by the same mistake Warning: Found 80 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Regarding the RAMS timing what my state machine is doing is creating a vector throughout differnt stages of the process and when the vector is ready to be saved . The statemachine goes to a state that asserts the Clock input to the RAM to '1' and this is asserted 1 for one clock cycle of the clock in the state machine before returning to '0'; The other message i get is Warning: Timing Analysis is analyzing one or more combinational loops as latches Warning: Node "ramin[0]$latch" is a latch .. ... .... Am i strucuring my VHDL code wrongly or somthing. I am using mentor graphic FPGA adavantge and have graphical created a state machine. >From what i have understood is thatArticle: 117204
hi , please i want some informations about reading videos using VHDL : how to input videos then to treat it? please i want informations about automatic way and manual way please and thank youArticle: 117205
"kha_vhdl" <abaidik@gmail.com> wrote in message news:1174940209.715975.319910@p77g2000hsh.googlegroups.com... > hi , > please i want some informations about reading videos using VHDL : how > to input videos then to treat it? please i want informations about > automatic way and manual way > please and thank you "Paul" <pauljbennett@gmail.com> wrote in message news:1174417296.447543.97510@n76g2000hsh.googlegroups.com... > Sorry, but that's an amazingly unclear question.... what video > format? how is it stored? streaming input signal? analog input to an > ADC? You can't possibly expect anyone to help you with that > question... clarify and maybe you'll find some advice What has changed since the last time this was answered? 1) you need a video source to generate the simulation date - DVD, MPEG 2 file, DIVX 2) you need to translate that digital video into something your chip can use, specifically "what video format? how is it stored? streaming input signal? analog input to an ADC?" 3) the simulation data would ideally be stored in a file to bea read by an $fscanf or $fread type of command 4) your testbench translates the file data to input stimulus appropriate for your simulation Do you know at this point what you are trying to accomplish at a system level by "reading videos?" If so, please think about the process a little more and try to communicate your needs more precisely.Article: 117206
"John_H" <newsgroup@johnhandwork.com> wrote in message news:130ge9or0f8nf79@corp.supernews.com... > "kha_vhdl" <abaidik@gmail.com> wrote in message > news:1174940209.715975.319910@p77g2000hsh.googlegroups.com... >> hi , >> please i want some informations about reading videos using VHDL : how >> to input videos then to treat it? please i want informations about >> automatic way and manual way >> please and thank you > > > "Paul" <pauljbennett@gmail.com> wrote in message > news:1174417296.447543.97510@n76g2000hsh.googlegroups.com... >> Sorry, but that's an amazingly unclear question.... what video >> format? how is it stored? streaming input signal? analog input to an >> ADC? You can't possibly expect anyone to help you with that >> question... clarify and maybe you'll find some advice > > > What has changed since the last time this was answered? > > 1) you need a video source to generate the simulation date - DVD, MPEG 2 > file, DIVX > 2) you need to translate that digital video into something your chip can > use, specifically > > "what video format? how is it stored? streaming input signal? analog > input to an ADC?" > > 3) the simulation data would ideally be stored in a file to bea read by an > $fscanf or $fread type of command > 4) your testbench translates the file data to input stimulus appropriate > for your simulation > > > Do you know at this point what you are trying to accomplish at a system > level by "reading videos?" If so, please think about the process a little > more and try to communicate your needs more precisely. And another thing: my response was a Verilog response. You're looking for VHDL, aren't you? Please substitute your favorite VHDL file access commands for how to read simulation data from files. If you're looking for synthesized video interfaces and processing, your question is completely misleading with your request for "informations about automatic way and manual way."Article: 117207
Hi, I built a PCB with a spartan3-xc3s400 TQ144 and tried configuring it with the simple JTAG parallal cabel III from xilinx (http:// toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html), but ISE9.1 couldn't identify the FPGA. Since I soldered the FPGA myself, I think some pins are not soldered well to their pads. I need to know the minimal pins needed to make an FPGA configuration by JTAG possible so that I don't have to check all 144 pins. According to what I understood from the datasheet, the only pins needed to be connected to make the confguration and verfication through JTAG possible are: TDI: Pin 144 TDO: Pin 109 TCK: Pin 110 TMS: Pin 111 and All GND's and VCCAUX's in Bank 0 and BANK 1 ( the Banks which the JTAG pins are connected to) I am right here or wrong? Thank You, JJArticle: 117208
It is very frustrating to try to answer such a -excuse the harsh word- stupid request. I have all the sympathy in the world for mangled english syntax, grammar, spelling, and poor choice of words. (English is my second language, too). But I have no sympathy for questions that are inherently meaningless and impossible to answer in any language on this planet. If you are smart enough to operate a computer, you should also be smart enough to put meaningful information into a request. Do us a favor: Think before you type ! This newsgroup is not a baby-sitting operation. Peter Alfke On Mar 26, 1:16 pm, "kha_vhdl" <abai...@gmail.com> wrote: > hi , > please i want some informations about reading videos using VHDL : how > to input videos then to treat it? please i want informations about > automatic way and manual way > please and thank youArticle: 117209
JJ, You also need power and ground for the core voltage, Vccint. And, you need Vcco for the bank that has the IO pins for the MODE selection, and configuration (even if these are unused, we still need to power the bank so the part will come out of reset and power ON). The power ON reset requires: Vccaux, Vccint, and Vcco (on the config bank) before the part is allowed to do anything at all. AustinArticle: 117210
Eric Smith wrote: >> Will we meet the time >> of Open Source development tools for programmable logic devices? > > Maybe someday, but not soon. Even if Xilinx and/or Altera did make the > details of the internal architecture and bitstreams public, developing a > complete FPGA tool chain appears to be a task at least three orders of > magnitude larger than building a C++ tool chain, and there aren't that > many open source C++ tool chains. Since code compilers are relatively linear, the primary difficulties are properly parsing the code and recognizing optimizable patterns, somewhat like synthesis and mapping for programmable logic. Place&Route on the other hand is very chaotic with many startup parameters defined as random values just like neural networks... the amount of work and back-pedaling that happens behind the scene to produce the post-PAR design is impressive and there probably are only a few handfuls of people world-wide who are capable of designing such algorithms yet retain their sanity. > I don't want to single out anyone in particular, but there seems to be a > whole lot of relatively unfounded criticism of the Xilinx software in > this newsgroup. It's true that I've found bugs in it from time to time, > but I've been able to work around them, and Xilinx support has been > quite helpful. I'm not aware of any other comparably sized piece of > software that is particularly more robust. The ISE Navigator is a simple text editor with a few tree-views and miscellaneous eye-candy but it still manages to crash a few times per week. The Schematic editor is rather plain as well yet it crashes quite readily so I completely gave up on schematics after ISE 7.1. XST appears to have some severe syntax error intolerance and readily crashes instead of reporting the said syntax or malformed construct errors, leaving the user oblivious to the actual cause. My main complaint about PAR is extremely inconsistent runtimes for a given design... anywhere from 5 to 30+ minutes for one of my smallest projects. ISE tools crashing instead of reporting errors (like declaring an entity inside an entity because I forgot to swap 'entity' for 'component' in a black box component declaration) is the most obscure and annoying time waster in my book, inconsistent runtimes is a close second. Most other obscure crashes I have encountered were cleared by rebuilding everything, this makes design partitioning very much pointless. > I think constructive criticism of the software is worthwhile, but > just saying that it is too slow and buggy to use is clearly both > unhelpful and factually incorrect. I have not played with Quartus much but building a 95% full EP2C8 on a 2.4GHz Celeron took a steady 10-12 minutes while building a 15% full V2P30 on a 3GHz P4 takes a random amount of time over 20 minutes and sometimes would not even complete overnight. Given the much higher vacancy rate and lower system clock target on the V2P along with the faster computer, I would have expected ISE to complete faster for a similarly sized design. I have tried tweaking ISE options to make builds quicker but ~20 minutes is pretty much the best I have ever been able to get for that build. Quartus and its back-end tools have never crashed on me for any reason whatsoever over the few months I used them while ISE still crashes on me for random reasons even though I have been learning to work around its shortcomings for the last three years. If I had to pick FPGAs based on vendor tools alone, I would seriously consider focusing on Altera's... but I generally prefer Xilinx's architectures so I really wish Xilinx would catch up in back-end maturity/stability... without sacrificing even more wall-clock performance.Article: 117211
Hi there I have some general question for implementing a general RISC architecture. I have coded so far the fetch, decode, execute and writeback stage. 1) Next step is to implement forwarding. Do I have here a 2:1 multiplexer in front of the alu that takes as input the output of the alu of the former cycle and the source register and the decode stage then sets the multiplexer select signal ? 2) How is it working with a NOP instruction? Does there the alu "execute" for example a R0 = R0 + R0. As R0 is always zero this doesnt have any effect. Or is there somehow an additional signal from the decode stage that tells the alu to do nothing? 3) Normally the writeback is done in the first half of the clock cycle whereas the registers are read in the second half in the decode register. Does this mean that the decode logic just works in the second half of the clock cycle or does it do some stuff in the first clock cycle and then just read out the operands in the second half of the cycle? I know some easy questions but would be helpful for understanding to know this ;) Cheers, PatrickArticle: 117212
On 27 Mrz., 01:00, Austin Lesea <aus...@xilinx.com> wrote: > JJ, > > You also need power and ground for the core voltage, Vccint. > > And, you need Vcco for the bank that has the IO pins for the MODE > selection, and configuration (even if these are unused, we still need to > power the bank so the part will come out of reset and power ON). > > The power ON reset requires: Vccaux, Vccint, and Vcco (on the config > bank) before the part is allowed to do anything at all. > > Austin Aha, I see...thanks for the reply. Another thing, according to the datasheet the power suplies to each edge (there are 4 edges and each edge has 2 banks) of the TQ144 are connected internally together, i.e. Bank0&1, Bank2&3, etc. Each edge has 3xVCCO, 2xVCCAUX, 2xVCCINT, 4xGND. Does that mean I need to connect ONLY one pin of each power supply per edge for the FPGA to function (since they are connected internally)? JJArticle: 117213
Hi Lewis,
I have a suggestion on VHDL function interface.
Here is a point: ('-' is used to simplify the 'downto')
R(63-0) <= a0*b0(63-0) + a1*b1(63-0) + ... + an*bn(63-0);
To finish the output data bus, I have to add function:
BitAndVector(a, b), then the above equation becomes:
R(63-0) <= BitAndVector(a0, b0) + BitAndVector(a1, b1) + ... +
BitAndVector(an, bn);
If we have a new interface like this:
BitAndVectorThenOR(a, b, ...);
The above function can be called like this:
R(63-0) <= BitAndVectorThenOR(a0, b0, a1, b1, a2, b2);
or
R(63-0) <= BitAndVectorThenOR(a0, b0, a1, b1, a2, b2, a3, b3, a4, b3);
The big advantages are: it makes compiler easier to do the best
optimization about the coding and VHDL programmers are easier to call
routine functions.
The compiler will check if a0, a1, ... are the same type of inputs and
if b0, b1, ... are the same type of inputs as R. There must be even
number of input signals and so on.
Another example:
Function XOR(a0, a1, ...);
The following calls are all valid:
XOR(a0, a1, a2);
XOR(a0, a1, a2, a3, a4, a5);
The compiler will check if a0, a1, ... are the same type of inputs.
Any number of input signals more than 1 are allowed and the function
will do the specified XOR operation and so on.
Here is an example of my code to generate a XOR equation from 32 input
signals:
y_xor(0) <= (x(1) xor x(2) xor x(3) xor x(5) xor x(8) xor x(9)
xor x(11) xor x(14) xor x(17) xor x(18) xor x(19) xor x(21) xor x(24)
xor x(25) xor x(27) xor x(30) xor x(32) xor x(36) xor x(38) xor x(39)
xor x(42) xor x(44) xor x(45) xor x(47) xor x(48) xor x(52) xor x(54)
xor x(55) xor x(58) xor x(60) xor x(61) xor x(63));
If there is a new function interface:
y_xor(0) <= XOR(x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14),
x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36),
x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55),
x(58), x(60), x(61), x(63));
Any comments are welcome.
Weng
Article: 117214<zcsizmadia@gmail.com> wrote in message news:1174682072.388509.137320@l77g2000hsb.googlegroups.com... > On Mar 23, 4:02 pm, "Bob Golenda" <bgoli...@nospam.net> wrote: > > Hi Zoltan, > > > > > I've done it! You don't have to implement the whole xsvfplayer. > > > > Youi've done exactly what? Written a stand alone JTAG programmer that > > programs the XCF part without using any XSVF files or XSVFPlayer etc. stuff? > > > > > If you want to support only xcf devices in a fixed environment, the > > > programming is fairly simple. > > > > Sure, but it's knowing what you need to do, and the timing that is the > > hardest part, since there is no spec for programming the XCF. > > Yes, without xsvf player. We have very limited resources in our uC, so > I have to program the XCF page by page (512 bytes). I've just wrote > the code to implement the JTAG programming protocol to program one > page on XCF and then stream the mcs file page by page to the uC and it > programs the flash. > > >>there is no spec for programming the XCF > You can find some open-source xcf programming tools using the parallel > port pins to program a xcf device like a JTAG programmer. You can > strip down those tools to the bare minimum. > You can find a conservative JTAG clock freq, so you should'nt worry > about timing. Hi Zoltan, Glad to hear you have actually done it. The timing I was referring to is not the JTAG TCK frequency, but the programming timing info. Thanks for the info!Article: 117215
Hi Zoltan, > Stop whining and here is the code! But please don't ask for more help. > Figure out the rest on your own! I was hardly "whining", just trying to find out what the reality was. People can say how to do something all they want, but actually doing it is entirely different. And, the difference between an XSVF player and a real JTAG programmer is substantial. I'll take a look at what you posted, thank you.Article: 117216
"Patrick" <grabherp23@yahoo.de> wrote > 1) Next step is to implement forwarding. Do I have here a 2:1 > multiplexer in front of the alu that > takes as input the output of the alu of the former cycle and the > source register and the decode stage > then sets the multiplexer select signal ? Typically the 2:1 muxes are *ahead* of the ALU input operand registers. Call them A and B. Then one pipeline recurrence might be A -> ALU -> result mux -> A fwd mux -> A etc, assuming you have no MEM pipeline stage. > 2) How is it working with a NOP instruction? Does there the alu > "execute" for example a R0 = R0 + R0. Yes. > As R0 is always zero this doesnt > have any effect. Or is there somehow an additional signal from the > decode stage that tells the alu to do nothing? No, rather it probably does an add of 0 + 0. > 3) Normally the writeback is done in the first half of the clock cycle > whereas the registers are read in the second half in the decode > register. Does this mean that the decode logic just works in the > second half of the clock cycle or does it do some stuff in the first > clock cycle and then just read out the operands in the second half of > the cycle? It all depends upon your datapath and pipeline design. Once the IR is latched in FFs it is decoded "continuously". See also: http://fpgacpu.org/papers/xsoc-series-drafts.pdf http://fpgacpu.org/papers/soc-gr0040-paper.pdf Jan GrayArticle: 117217
Peter Alfke wrote: > But I have no sympathy for questions that are inherently meaningless > and impossible to answer in any language on this planet. > If you are smart enough to operate a computer, you should also be > smart enough to put meaningful information into a request. Do us a > favor: Think before you type ! > This newsgroup is not a baby-sitting operation. Well said Peter, though I tend to be more bemused than frustrated by such requests. My guess is that either they're students sitting on the wrong side of the bell curve that have been given an assignment that is way outside their capabilities, or hobbyists/hackers whose greatest achievement so far is patching their name and a few rude words into the credits of their favourite game and think 'how much harder can it be' to develop some cool video processor on an FPGA dev board. Any educated engineer or earnest hobbyist would have the common sense and also take the time to do at least enough research to be able to understand the problem they're trying to solve in the first place. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 117218
Thanks for your answers Jan, one more issue > Then one pipeline recurrence might be A -> ALU -> result mux -> A fwd mux -> > A etc, assuming you have no MEM pipeline stage. In the end there will be a Mem Pipeline. In that case I have a 3:1 mux and the decode logic selects then the correspoding value to use, either the forward of the alu, of the mem or of the register file. Is that correct? Cheers, PatrickArticle: 117219
"Patrick" <grabherp23@yahoo.de> wrote in message > Thanks for your answers Jan, one more issue > >> Then one pipeline recurrence might be A -> ALU -> result mux -> A fwd >> mux -> >> A etc, assuming you have no MEM pipeline stage. > > In the end there will be a Mem Pipeline. In that case I have a 3:1 mux > and the decode logic selects > then the correspoding value to use, either the forward of the alu, of > the mem or of the register file. Is that > correct? Yes, Patrick, that's exactly right. Note, if you have a shifter, or jump-and-link, or anything else that produces a value into a register, you may need to mux that result in and forward that as well. Another good reference is Computer Organization and Design by Patterson and Henessey. Have fun! Jan.Article: 117220
Daniel S. wrote: > The ISE Navigator is a simple text editor with a few tree-views and > miscellaneous eye-candy but it still manages to crash a few times per > week. I haven't had a crash in Navigator in perhaps 1000 hours of using various releases. I have had other ISE tools abort with internal errors. > The Schematic editor is rather plain as well yet it crashes > quite readily so I completely gave up on schematics after ISE 7.1. I've never used the Schematic Editor, so I can't comment on its quality (or lack thereof). It's clear that HDL support is a higher priority for Xilinx than schematic entry. > XST appears to have some severe syntax error intolerance and readily > crashes instead of reporting the said syntax or malformed construct > errors, leaving the user oblivious to the actual cause. I used to see that in 7.x, but haven't seen it much in 8.x and 9.1. Maybe 7.x trained me not to do things that it didn't like. Although it is obviously desirable for a tool to provide a good report of a syntax error rather than crashing, I'm much more concerned about ensuring that the tool does not crash for valid input. > My main complaint about PAR is extremely inconsistent runtimes for a > given design... anywhere from 5 to 30+ minutes for one of my smallest > projects. I haven't experienced that much variation; I've only seen about a 2:1 range. However, I'm not convinced that expecting consistent timing is realistic; a small change to your input may cause a siginficant difference in the routing difficulty, especially if you have tight timing constraints. EricArticle: 117221
"kha_vhdl" <abaidik@gmail.com> writes: > please i want some informations about reading videos using VHDL : how > to input videos then to treat it? It's rumored that the VHDL 2009 standard will include a standard package for video processing, so you're probably best off waiting for that.Article: 117222
Good Evening Mr. Tianxiang,
> Hi Lewis,
> I have a suggestion on VHDL function interface.
>
> Here is a point: ('-' is used to simplify the 'downto')
> R(63-0) <= a0*b0(63-0) + a1*b1(63-0) + ... + an*bn(63-0);
How do your propose to handle the case where someone
wrote an expression to get the bit one to the left of
the leftmost bit:
Y <= A(A'left - 1) ;
Golden Rule:
You can't change the language in a way that breaks code that is
currently valid.
Also note, in VHDL, "*" is multiply and "+" is add. Is that
what you mean or are using it as a short hand for "and" and "or".
> To finish the output data bus, I have to add function:
> BitAndVector(a, b), then the above equation becomes:
>
> R(63-0) <= BitAndVector(a0, b0) + BitAndVector(a1, b1) + ... +
> BitAndVector(an, bn);
>
> If we have a new interface like this:
> BitAndVectorThenOR(a, b, ...);
>
> The above function can be called like this:
> R(63-0) <= BitAndVectorThenOR(a0, b0, a1, b1, a2, b2);
> or
> R(63-0) <= BitAndVectorThenOR(a0, b0, a1, b1, a2, b2, a3, b3, a4, b3);
>
Is this the same AND-OR logic we talked about when you wrote
your conference paper? The overloaded "and" function I showed
you then has been integrated into the language with Accellera 3.0 draft
of VHDL. For the time being, you can use the following package:
library ieee ;
use ieee.std_logic_1164.all ;
package TempPkg is
------------------------------------------------------------
function "and" (
l : std_logic_vector ;
r : std_logic
) return std_logic_vector ;
------------------------------------------------------------
function "and" (
l : std_logic ;
r : std_logic_vector
) return std_logic_vector ;
end TempPkg ;
-- ==============================================================
package body TempPkg is
------------------------------------------------------------
function "and" (
l : std_logic_vector ;
r : std_logic
) return std_logic_vector is
variable result : std_logic_vector(l'range) ;
begin
for i in l'range loop
result(i) := l(i) and r ;
end loop ;
return result ;
end ; -- "and"
------------------------------------------------------------
function "and" (
l : std_logic ;
r : std_logic_vector
) return std_logic_vector is
variable result : std_logic_vector(r'range) ;
begin
for i in r'range loop
result(i) := r(i) and l ;
end loop ;
return result ;
end ; -- "and"
end TempPkg ;
With this package, you can write your equations as:
R(63 downto 0) <= (a0 and b0) or (a1 and b1) or ... or
(an and bn);
Hey, I even saved you enough typing that you don't have to be
overly concerned about having to use "downto".
Alternately you can use the following:
signal Y, A, B : std_logic_vector(7 downto 0) ;
Y <=
(A and (A'range => ASel)) or
(B and (B'range => BSel)) ;
Note I have portability concerns with the above code as at one point in
time Synopsys did not support it. If they still do not support it,
and you use their tools, report it as a bug (if you need help
convincing it is a bug, drop me an email).
> Another example:
> Function XOR(a0, a1, ...);
>
> The following calls are all valid:
>
> XOR(a0, a1, a2);
>
> XOR(a0, a1, a2, a3, a4, a5);
>
> The compiler will check if a0, a1, ... are the same type of inputs.
> Any number of input signals more than 1 are allowed and the function
> will do the specified XOR operation and so on.
>
> Here is an example of my code to generate a XOR equation from 32 input
> signals:
> y_xor(0) <= (x(1) xor x(2) xor x(3) xor x(5) xor x(8) xor x(9)
> xor x(11) xor x(14) xor x(17) xor x(18) xor x(19) xor x(21) xor x(24)
> xor x(25) xor x(27) xor x(30) xor x(32) xor x(36) xor x(38) xor x(39)
> xor x(42) xor x(44) xor x(45) xor x(47) xor x(48) xor x(52) xor x(54)
> xor x(55) xor x(58) xor x(60) xor x(61) xor x(63));
>
> If there is a new function interface:
> y_xor(0) <= XOR(x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14),
> x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36),
> x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55),
> x(58), x(60), x(61), x(63));
Write yourself a function that accepts std_logic_vector as an input and
add an extra set of parentheses to the call:
y_xor(0) <= XOR(( x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14),
x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36),
x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55),
x(58), x(60), x(61), x(63) ));
Now the function sees one input argument that is an array aggregate :).
Good Luck to You,
Jim Lewis
SynthWorks VHDL Training
Article: 117223unlikely <djoshi@btinternet.com> wrote in message news:1174898327.777633.236600@p77g2000hsh.googlegroups.com... > Dear Rob > > I also have some states that has not commands in them. The purpose of > these were to cause few clock cycle delays. Could this be a problem. > > > Regards > > Dharmesh Joshi >Article: 117224
Sometimes state machines are used to create read and write strobes for memory interfaces. So, even though you are transitioning from one state to another by a CLK, a signal (ie: rd_strobe, wr_strobe, or cs (chip select)) within a certain state can be synthesized as a global signal used to clock the appropriate registers. You can use the "Resource Property Editor" to check what signals are controlling the source and destination flops that are in violation. You can also highlight the violation within the report, right click, and choose "list paths" to see the detail timing analysis on the path. If both registers are being clocked by the same signal then you are probably dealing with either a gated clock or clock routing issue. If the clock you are using is on the global network, you can rule out clock skew caused by routing. Again, search the help files using the topics I gave you. <djoshi@btinternet.com> wrote in message news:1174897957.249777.268300@o5g2000hsb.googlegroups.com... > Dear Rob > > Thank You for your reply below. > > I am still a student learning more into FPGA so please excuse me style > of questioning > > Quartus defaults to the most stringent hold requirement, 0ns. A hold > violation is typically due to clock skew, gated clocks, or the sourse > and > destination register clocked by two different clocks. Your state > machine > probably transistions from one state to another by CLK_H; and certain > states > within your state machine are probably creating strobes that are > clocking > registers. My guess is that the source and destination register are > being > clocked by two different signals thus giving you this error. If you > really > don't need a 0ns hold requirment on this path, you can utilize the > Multicycle Hold assignment to get you by this timing warning. > > Search on "hold relationship" and "Multicycle Hold timing assignment" > in the > help section of Quartus. These two section should help you. > > > I got few things i need to ask. > > When you say " your state machine are probably creating strobes that > are clocking > registers", would that mean that once i get to into a state i am > asserting signal, for example the input vector to the RAM gets > asserted to ceratain binary value. My design uses only one clock, so > how can "My guess is that the source and destination register are > being > clocked by two different signals thus giving you this error" i check i > am not having this problem. > > > > Thank You very much for your help > > > > Regards > > > > Dharmesh Joshi >
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