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Messages from 118100

Article: 118100
Subject: Re: PLB Master
From: Jeff Cunningham <jcc@sover.net>
Date: Tue, 17 Apr 2007 10:23:33 -0400
Links: << >>  << T >>  << A >>
Eli Hughes wrote:
> HDL simulation only.  Just simulated the pieces of the interface and it 
> worked when it was implemented in a V2P20

I was interested what type of models for the other bus components you 
used, which you explained in another post. I hadn't thought of using the 
IPIF slave as a model.

I recently developed my own PLB master using the IBM supplied bus 
functional models and MXE for VHDL sim. It worked pretty well and the 
models are quite powerful, issue "intelligent" warnings and such, but it 
ran quite slow.

http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/618ba3d9dcc3b76b/2eff36c6baba0212?lnk=st&q=&rnum=2&hl=en#2eff36c6baba0212

-Jeff

Article: 118101
Subject: Re: 80000 Bit Shift Register - The Code
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Tue, 17 Apr 2007 15:24:39 +0100
Links: << >>  << T >>  << A >>

"Eli Hughes" <emh203@psu.edu> wrote in message 
news:f02joe$nfq$1@f04n12.cac.psu.edu...
> Eli Hughes wrote:
>>
>> I am implementing an 80000 Element Shift register to be used as a very 
>> long (1Sec) digital delay generator. (Yes, its that big).     It is 
>> clocked at 80kHz.
>> Any pointers on how to make this synthesize faster?

I would use block RAM resources for the delay-line storage instead of FFs. 
That way you just need 5 RAM blocks per data bit, and a counter or two, 
rather than creating some massive power-hungry flip-flop spaghetti... :)

      -Ben- 



Article: 118102
Subject: Re: 80000 Bit Shift Register
From: Andy <jonesandy@comcast.net>
Date: 17 Apr 2007 07:31:30 -0700
Links: << >>  << T >>  << A >>
On Apr 17, 9:05 am, Frank Buss <f...@frank-buss.de> wrote:
> Eli Hughes wrote:
> > Any pointers on how to make this synthesize faster?
>
> What about using block ram and just an index pointer? Shift-in: set current
> bit at index, increment index pointer, read current bit and shift it out.
> If the index pointer reaches some limit, reset it to 0. If you clock the
> FPGA with a higher frequency, then the read/write cycles are no problem
> with your shift clock.
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

In the past, I had problems trying to get synthesis to build a memory
of std_logic types (i.e. a long std_logic_vector). To get around it I
declared an array of one bit std_logic_vectors, and that worked fine.

You might be able to declare an array of 80000 of those, and then use
a binary counter to read/write the memory. I've had synthesis tools
stitch together multiple ram primitives automatically in the past (in
depth and in width), but not that deep with block rams (never tried
it).

Sorry, my expertise is in vhdl, not verilog, but maybe you get the
idea anyway.

Andy


Article: 118103
Subject: Re: plb_tft_cntlr_ref for an ML405 EDK Project
From: Peter Mendham <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk>
Date: Tue, 17 Apr 2007 15:51:01 +0100
Links: << >>  << T >>  << A >>
Ben Jones wrote:
> The EDK ports view has a "filter" setting which usually hides all the nets 
> which have default connections. If the ports are hidden then that probably 
> means they've been connected up already. 
They were indeed hidden as a "default connection" but they weren't 
connected to anything!  Thank you for your help, it seems to be working 
OK now.

Thanks,
-- Peter

Article: 118104
Subject: Re: No Synplify evaluation?
From: "HT-Lab" <hans64@ht-lab.com>
Date: Tue, 17 Apr 2007 15:26:25 GMT
Links: << >>  << T >>  << A >>
Hi Richard,

<Richard Klingler> wrote in message 
news:2007041714311816807-@news-europe.giganews.com...
> Good afternoon..
>
> Has anyone being lucky in the past getting a Synplify for Linux
> evaluation license?
>
> Mentor has some online feedback form to request an evaluation
> license, but apparently their eimail goes always to /dev/null (o;
>

Just call/email one of their distributors.

> I received the ispLever for Linux including license from Lattice
> directly but as you know the more expensive software lacks
> any synthesizing tools...

I believe Lattice has Precision under OEM agreement with Mentor, not sure if 
that includes the Linux version.

>
> I know I could switch to Windows..but..I already have it...
> (thanx again to Lattice Semiconductor for their great support
> sponsoring me software/hardware ;o)
>
> I just need the Linux version for porting several software
> to the Linux platform....

Good, stick with Linux :-)

Hans
www.ht-lab.com


>
>
> cheers
> rick
>
> 



Article: 118105
Subject: Re: XPS behavioral simulation fails: the design is not loaded
From: Newman <newman5382@yahoo.com>
Date: 17 Apr 2007 08:52:59 -0700
Links: << >>  << T >>  << A >>
On Apr 12, 1:24 pm, "ferorcue" <le_m...@hotmail.com> wrote:
> After designing a peripheral and checking that it is working with the
> BFM simulation, I am trying to simulate the whole system. I created a
> simple system with BSB in order to get experience with this
> simulation. I generated the Hdl libraries in XPS and modified the
> modelsim.ini to use the Smartmodels ( I use Modelsim SE PLUS 6.2a). I
> also checked it with:
> VSIM>vsim unisim.ppc405              And it is working ok.
>
> XPS creates the directory simulation/behavior with the scripts to
> simulate the system in Modelsim. The system was compiled using these
> scripts.
>
> I have an error while the system is loaded:
>
> # Loading opb_arbiter_v1_02_e.or_gate(imp)#1
> # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32)
> for port '/system/opb/opb/opb_abus_i/y'.
> #    Time: 0 ps  Iteration: 0  Instance: /system/opb/opb/opb_abus_i
> File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/
> opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125
> # FATAL ERROR while loading design
> # Error loading design
> # 1
>
> I do not how to solve this problem as the opb_arbiter_v1_02_e module
> is a Xilinx IP core, and it is read only.
> It has to be any solution, because some people are using this kind of
> simulation and I am trying to use it with a simple design created with
> BSB( bitstream ok, and the software project is the default
> TestAppMemory)
>
> Can anyone help me, thanks.
>
> Note: This is almost all the information of Modelsim
> # vsim -t ps system_conf
> # Loading /opt/modeltech/6.2a/linux/libswiftpli.sl
> # Loading /opt/modeltech/6.2a/linux/../std.standard
> # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_1164(body)
> ...
> ...
> ...
> # Loading /opt/modeltech/6.2a/linux/libsm.sl
> # ** Note (SmartModel):
> #    Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED
> # ** Note (SmartModel):
> #    Platform Type: x86_linux (32-bit).
> # ** Note (SmartModel):
> #    You can use the Browser tool to configure the SmartModel
> #    Library and access information about SmartModels:
> #       $LMC_HOME/bin/sl_browser
> #
> #    SmartModel product documentation is available here:
> #       $LMC_HOME/doc/smartmodel/manuals/intro.pdf
> #      http://www.synopsys.com/products/lm/doc/smartmodel.html
> #
> # Notice: timing checks disabled with +notimingcheck at compile-time
> # ** Warning (SmartModel):
> #    Model is being requested to run at a finer resolution than
> necessary.
> #    Time: 0 ps  Instance:/system/ppc405_0/ppc405_0/ppc405_i/
> ippc405_swift/ppc405_swift_inst
> # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
> unisim/.fpga_startup(fpga_startup_v)
> # Loading work.ppc405_1_wrapper(structure)
> # ** Warning (SmartModel):
> #    Model is being requested to run at a finer resolution than
> necessary.
> #    Time: 0 ps  Instance:/system/ppc405_1/ppc405_1/ppc405_i/
> ippc405_swift/ppc405_swift_inst
> # Loading work.jtagppc_0_wrapper(structure)
> # Loading jtagppc_cntlr_v2_00_a.jtagppc_cntlr(structure)
> ...
> ...
> ...
> # Loading opb_arbiter_v1_02_e.opb_arb_pkg(body)
> # Loading opb_v20_v1_10_c.opb_v20(imp)#1
> # Loading opb_arbiter_v1_02_e.or_gate(imp)#1
> # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32)
> for port '/system/opb/opb/opb_abus_i/y'.
> #    Time: 0 ps  Iteration: 0  Instance: /system/opb/opb/opb_abus_i
> File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/
> opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125
> # FATAL ERROR while loading design
> # Error loading design
> # 1

I looked in the or_gate.vhd file and there is a generic that gets
passed in
called C_BUS_WIDTH with a default of 1.  Are you setting this value to
what
is required at the upper levels and passing it in?  This is a quick
guess on
my part.

Hope this helps,
Newman


Article: 118106
Subject: Re: 80000 Bit Shift Register
From: langwadt@ieee.org
Date: 17 Apr 2007 09:34:35 -0700
Links: << >>  << T >>  << A >>
On 17 Apr., 15:52, Eli Hughes <emh...@psu.edu> wrote:
> I am implementing an 80000 Element Shift register to be used as a very
> long (1Sec) digital delay generator. (Yes, its that big).     It is
> clocked at 80kHz.
>
> Its a very simple design, just an ordinary shifter register with 80k
> elements. It is being implemented in a V2Pro (Digilent XUP Board).
>
> I have simulated the design and it works OK.  I am now trying to
> synthesize the design and it is taking a *VERY* long time.  I tried to
> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It
> failed 5 hours later with an out of memory error.  I am now trying on a
> Xeon Work station with 3GB of RAM.
>
> Any pointers on how to make this synthesize faster?
>
> What kind of machines are people using out there to synthesize large
> designs?

haven't checked if it actually works but it should be close,
synthesize in seconds infering 5 blockrams:

module shift(clk,in,out);

input clk,in;
output out;

reg out;

reg [80000:0] shiftreg;
reg [16:0]    index;

always@(posedge clk)
begin
	out <= shiftreg[index];
	shiftreg[index] <= in;
	if(index <17'd80000)
		index <= index +17'd1;
	else
		index <= 17'd0;

end


-Lasse









Article: 118107
Subject: Re: Safety of bidirectional lines
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Tue, 17 Apr 2007 13:18:54 -0400
Links: << >>  << T >>  << A >>
Symon wrote:
> "Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote in message 
> news:Ic3Vh.17620$iq5.533929@wagner.videotron.net...
>> IOBs use current-limited output drivers for slow slew
> Hi Daniel,
> Can you point me to a reference for this statement?
> Thanks, Syms. 

The funny thing with references is that you come across them when you do 
not need them (searching for something else) and you have no idea what you 
searched for to find them when you need those accidental finds afterwards.

As I mentioned in my first reply, it was a table in one of Xilinx's 
documents but I do not remember which... may have been an appnote, a 
whitepaper or electrical specs. Since I vaguely remember it being less 
formal than specs, it probably was a V4 or S3 appnote... possibly about 
SSO, power distribution or other board-level stuff. (I have notoriously bad 
memory for unnecessary information.)

Actually, I think the link was posted by someone here (somewhere around 
September) and I read it simply out of curiosity. I think that thread was 
about IOB power dissipation in FPGAs.

Article: 118108
Subject: Re: Why 166Mhz DDR?
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Tue, 17 Apr 2007 13:57:34 -0400
Links: << >>  << T >>  << A >>
rohit2000s@yahoo.com wrote:
>>
>> The maximum operating frequency is determined by how fast the DRAM is able
>> to get data into or out of the active row (data) register and other control
>> structures with the maximum amount of pipelining enabled. Since the high-K
>> process used for DRAMs yields slow logic, latency cycles (intermediate
>> registers) pile up really fast on high-speed DRAMs.
> 
> Thanks Ben & Daniel ! I think you answered my curiosity question :)
> 
> -Uday

If your curiosity wants to see something extreme, download datasheet for 
some DDR and DDR2 devices and compare these timings with the latest 1.6GHz 
Samsung GDDR4 devices... there is a pretty drastic difference in the number 
of latency cycles, particularly CAS.

Article: 118109
Subject: ANN: Tyd-IP Code Generator V3.1 released
From: stenasc@yahoo.com
Date: 17 Apr 2007 11:21:45 -0700
Links: << >>  << T >>  << A >>
Version 3.1 of Tyd-IP Code Generator has now been released. Now
supporting multirate filter design, designers can create a wide range
of IP, including filters, FFTs, NCOs etc. which can be targetted at
any FPGA or ASIC. Until, the end of May 2007, the multirate
coefficient and VHDL module, will be available free of charge to all
purchasers of Tyd-IP.

Regards
Robert


Article: 118110
Subject: Re: 80000 Bit Shift Register
From: "HT-Lab" <hans64@ht-lab.com>
Date: Tue, 17 Apr 2007 18:45:06 GMT
Links: << >>  << T >>  << A >>

"Eli Hughes" <emh203@psu.edu> wrote in message 
news:f02jfc$nfi$1@f04n12.cac.psu.edu...
> I have simulated the design and it works OK.  I am now trying to 
> synthesize the design and it is taking a *VERY* long time.  I tried to 
> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It 
> failed 5 hours later with an out of memory error.  I am now trying on a 
> Xeon Work station with 3GB of RAM.
>
> Any pointers on how to make this synthesize faster?

I just tried Precision on your code and it took 10 minutes to synthesize on 
an AMD3500+ with 4Gbyte of memory. Compile took 400Mbyte, and synthesis 
1.4Gbyte (rough estimate from the task manager on Win2K).

Hans
www.ht-lab.com



Article: 118111
Subject: Re: 80000 Bit Shift Register
From: Eli Hughes <emh203@psu.edu>
Date: Tue, 17 Apr 2007 15:34:43 -0400
Links: << >>  << T >>  << A >>

Thanks for all of the pointers.  I ended up just implementing the delay 
with BlockRam. The simulation worked great.  I will post the code as 
soon as I very *real* operation.





HT-Lab wrote:
> "Eli Hughes" <emh203@psu.edu> wrote in message 
> news:f02jfc$nfi$1@f04n12.cac.psu.edu...
>> I have simulated the design and it works OK.  I am now trying to 
>> synthesize the design and it is taking a *VERY* long time.  I tried to 
>> synthesize on my PC (P4 3.2GHz, 1G Ram) when I left work last night.  It 
>> failed 5 hours later with an out of memory error.  I am now trying on a 
>> Xeon Work station with 3GB of RAM.
>>
>> Any pointers on how to make this synthesize faster?
> 
> I just tried Precision on your code and it took 10 minutes to synthesize on 
> an AMD3500+ with 4Gbyte of memory. Compile took 400Mbyte, and synthesis 
> 1.4Gbyte (rough estimate from the task manager on Win2K).
> 
> Hans
> www.ht-lab.com
> 
> 

Article: 118112
Subject: creating library in ISE 9
From: "mans" <(myname_here)_123456@yahoo.com>
Date: Tue, 17 Apr 2007 21:27:29 GMT
Links: << >>  << T >>  << A >>
Hello,

I am newbie in VHDL. I want to create a library with several pkg on it so 
when I am creating a new library; I could add it to my new project and then 
use the pakage.



What I am doing now is as follow:



Every time that I create a new project, I am creating a new library in its 
library view and then add all of my packages source code to it.



The main problem in this technique is that I need to create the library 
every time that I create a new project. Is there any way that I can create a 
library that it is included automatically to all newly generated projects?



One solution is to create a library in one project and then tell its path to 
other projects, but how can I do this?



Best regards




 



Article: 118113
Subject: Re: SETUP & HOLD time confusion
From: Peter Alfke <peter@xilinx.com>
Date: 17 Apr 2007 14:45:16 -0700
Links: << >>  << T >>  << A >>
I promised to inquire, and that's what I did. Unfortunately, the issue
is very complicated and convoluted. Too much so for a quick answer.
The user guide text is bad, and offers no help.
I got a very long explanation that does not lend itself for "public
consumption".
I will think about this more, and we will have to come up with a
better decription, albeit perhaps a simplified one.
Peter Alfke

On Apr 12, 7:34 pm, "Peter Alfke" <a...@sbcglobal.net> wrote:
> No, no, no. Let's not make a bad thing even worse.
>
> I am ashamed that a Xilinx document publishes the above quoted
> nonsense.
> But let's at least look at the basics:
> Set-up time and hold-time are both input timing requirements.
> "3 ns set-up time" means, the new data must be there at least 3 ns
> before the clock edge, in order to be guaranted to be captured in the
> flip-flop. (like the airline says: you must be there one hour before
> departure)
> If data arrives later, it might actually make it, but there is no
> guarantee.
> A positive hold-time requirement (very rare and always bad!) means
> that the data being clocked in must actually linger on the D pin (for
> the specified positive hold time) beyond the clock edge. Bad
> requirement, since it is often very hard to live with. That's why most
> good parts specify "zero hold time", which means, you can take away
> the data right at the clock edge. In reality even a bit earlier, but
> that would have to be specified as a negative hold-time value, and few
> data sheets do.
> In other words, D must be stable from as early as a set-up time before
> the clock, to as late as a (positive) hold time after the clock, but
> most hold times are specified as 0.
> If you change D within this required timing window, the flip-flop will
> make the decision for you, whether it catches the early or the later
> data, but it usually catches a clean 0 or 1. If you change data at a
> very narrow "bulls-eye" point in time, then the flip-flop can indicate
> its displeasure by having an unpredictable output delay, the infamous
> metastable delay.
> I do not have the foggiest idea what the stupid sentence in your quote
> means, but it deserves to be eradicated and translated into English.
> Let me inquire.
> You obviously hit a sensitive nerve with me...
> Peter Alfke
>
> On Apr 12, 6:02 pm, "Newman" <newman5...@yahoo.com> wrote:
>
> > On Apr 12, 2:31 pm, "M. Hamed" <mhs...@gmail.com> wrote:
>
> > > In the Xilinx Synthesis and Simulation Design Guide there is this
> > > phrase:
>
> > > "While Xilinx data sheets report that there are zero hold times on the
> > > internal registers and I/O registers with the default delay and using
> > > a global clock buffer, it is still possible to receive a $hold
> > > violation from the simulator. This $hold violation is really a $setup
> > > violation on the register. However, in order to get an accurate
> > > representation of the CLB delays, part of the setup time must be
> > > modeled as a hold time."
>
> > > Can somebody put some more explanation to this phrase? I understand
> > > how the setup/hold window can be shifted back and forth by adding
> > > delay to the data path but I dont understand why the need for modeling
> > > part of the setup time as hold time, and how to properly fix hold time
> > > violations.
>
> > > Thank you.
> > > /MHS
>
> > Here is a stab at it.
> > The min propagation delay from a flip flop to another flip flop plus
> > the global clock uncertainty is more than the hold time of the
> > destination FF. If the propagation delay is continuously increased,
> > first you'll get a setup violation, if increased further... a hold
> > violation, increased further... no violation.  Once one hits the setup
> > violation point and further, the functionality of the device comes
> > into question.
>
> > I believe the answer is to limit the propagation delay with timing
> > constraints.
>
> > Newman



Article: 118114
Subject: Re: creating library in ISE 9
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 17 Apr 2007 15:46:44 -0700
Links: << >>  << T >>  << A >>
mans wrote:

> The main problem in this technique is that I need to create the library 
> every time that I create a new project. Is there any way that I can create a 
> library that it is included automatically to all newly generated projects?

I keep hdl source files and all the synthesis projects
that use those files in separate directories.
That way, multiple projects can pick up
exactly the same source. Synthesis spews
lots of files during compilation that
I don't want those mucking up the source directories.

         -- Mike Treseler

Article: 118115
Subject: Re: type/subtype definition in entity
From: zhangpei@gmail.com
Date: 17 Apr 2007 16:22:17 -0700
Links: << >>  << T >>  << A >>
Thanks a lot for your useful suggestion and informations, Alan and
Andy.

Accellera VHDL 2006 ( which will be VHDL 2007 with minor changes?)
looks perfect for my need.

http://www.synthworks.com/papers/vhdl_accellera_lewis_marlug_2006_bw.pdf

type std_logic_matrix is array (natural range <>) of
std_logic_vector ;
-- constraining in declaration
signal A : std_logic_matrix(7 downto 0)(5 downto 0) ;

entity e is
port (
A : std_logic_matrix(7 downto 0)(5 downto 0) ;
. . .
) ;

That makes VHDL more like C for 2-dimensional arrays.

Anyway, I will use other method to implement my needs.

Z

On Apr 17, 6:09 am, Andy <jonesa...@comcast.net> wrote:
> Right now, there isn't a good way to handle what you want, exactly. As
> Alan said, Accellera's 2006 std has the ability to invoke packages
> with generics, which would do what you want.
>
> For now, I would do one of two things:
>
> First, the package for this entity could use a constant from another
> package (a higher level project package) to get the sizes. BTW,
> whenever I create packages that have typedefs, etc for an entity, I
> them at the top of the same file that has the entity/arch in it. That
> way, if you've compiled the entity/arch, you've also compiled the
> package necessary to use it. I also often define a record type to hold
> all the generics for the entity in that package. That way handling all
> the generics up through the hierarchy gets easier. Higher level
> packages for higher level entities reference the lower level entities'
> packages' generic record definitions, and so on, all the way to the
> top. So adding a new parameter for a lower level entity means adding
> it only to the entity/arch/package that needs it, and to the top level
> where it gets set. It gets automatically plumbed through all the
> levels in between.
>
> The second method would be to pack the entire array into one long SLV
> (can be an unconstrained port). Then you can pass generics into the
> entity that allow you to recompose the array from the SLV (or
> decompose the array to drive the port). Not the prettiest solution,
> but it works.
>
> Hope this helps,
>
> Andy
>
> On Apr 17, 4:46 am, Alan Fitch <alan.fi...@spamtrap.com> wrote:
>
> > zhang...@gmail.com wrote:
> > > I want to define a type related to entity generics, like an array in
> > > the following codes. But It seems I have no places to put those
> > > subtype/type statements in the entity. I can not use package to define
> > > those subtype/type since there are related to entity generics.
>
> > > Any solution or idea?
>
> > > Thanks a lot,
>
> > > Z
> > > 04/16/07
>
> > > ===============
> > > library IEEE;
> > > use IEEE.std_logic_1164.all;
> > > use IEEE.std_logic_arith.all;
> > > use IEEE.std_logic_unsigned.all;
>
> > > entity ir is
> > > --   Here is not correct
> > > --   subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
> > > --   type    MY_UNSIGNED_VECTOR is array(natural range<>) of
> > > MY_UNSIGNED;
> > >    generic (
> > >       EL_SIZE  : POSITIVE := 16;
> > >       EL_COUNT : POSITIVE := 8
> > >    );
> > > --   Here is not correct either
> > > --   subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
> > > --   type    MY_UNSIGNED_VECTOR is array(natural range<>) of
> > > MY_UNSIGNED;
> > >    port (
> > >       val_b : out MY_UNSIGNED_VECTOR (0 to EL_COUNT-1);
> > >       clk_i : in std_logic
> > >       ...
> > >    );
> > > end ir;
>
> > Hi Z,
>
> >    you must put the declarations in a package, e.g.
>
> > library ieee;
> > use ieee.std_logic_arith.all; -- prefer numeric_std, it's a standard
> >   package mytypes is
> >       subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
> >       type    MY_UNSIGNED_VECTOR is array(natural range<>) of MY_UNSIGNED;
>
> >    end package mytypes;
>
> > Of course you then don't have access to the generic. So you need to
> > fix the generic size using a constant or the subtype itself, e.g.
>
> >   package mytypes is
> >       constant EL_SIZE : positive := 10;
> >       subtype MY_UNSIGNED is unsigned(EL_SIZE-1 downto 0);
> >       type    MY_UNSIGNED_VECTOR is array(natural range<>) of MY_UNSIGNED;
>
> >    end package mytypes;
>
> > You must make the package visible in front of the entity of course, e.g.
>
> > library mylib;
> > use mylib.mytypes.all;
> > library ieee;
> > ...
>
> > entity...
>
> > assuming you compiled the package into library 'mytypes'
>
> > Does that help?
>
> > In Accellera VHDL2006 you can have package generics, which would be a
> > neater solution - but your tools must have 2006 support.
>
> > regards
> > Alan
>
> > --
> > Alan Fitch
> > Douloshttp://www.doulos.com



Article: 118116
Subject: Re: SETUP & HOLD time confusion
From: Newman <newman5382@yahoo.com>
Date: 17 Apr 2007 16:35:36 -0700
Links: << >>  << T >>  << A >>
On Apr 12, 2:31 pm, "M. Hamed" <mhs...@gmail.com> wrote:
> In the Xilinx Synthesis and Simulation Design Guide there is this
> phrase:
>
> "While Xilinx data sheets report that there are zero hold times on the
> internal registers and I/O registers with the default delay and using
> a global clock buffer, it is still possible to receive a $hold
> violation from the simulator. This $hold violation is really a $setup
> violation on the register. However, in order to get an accurate
> representation of the CLB delays, part of the setup time must be
> modeled as a hold time."
>
> Can somebody put some more explanation to this phrase? I understand
> how the setup/hold window can be shifted back and forth by adding
> delay to the data path but I dont understand why the need for modeling
> part of the setup time as hold time, and how to properly fix hold time
> violations.
>
> Thank you.
> /MHS

Here is some stuff from http://toolbox.xilinx.com/docsan/xilinx5/data/docs/sim/sim0066_10.html

Debugging Tips
When you are faced with a timing violation, the following questions
may give valuable clues as to what went wrong.

Was the clock path analyzed by TRACE or Timing Analyzer?
Did TRACE or Timing Analyzer report that the data path can run at
speeds being clocked in simulation?
Is clock skew being accounted for in this path delay?
Does subtracting the clock path delay from the data path delay still
allow clocking speeds?
Will slowing down the clock speeds eliminate the $setup/$hold time
violations?
Does this data path cross clock boundaries (from one clock domain to
another)? Are the clocks synchronous to each other? Is there
appreciable clock skew or phase difference between these clocks?
If this path is an input path to the device, does changing the time at
which the input stimulus is applied eliminate the $setup/$hold time
violations?
Based on the answers to these questions, you may need to make changes
to your design or testbench to accommodate the simulation conditions.

Special Considerations for Setup and Hold Violations
Zero Hold Time Considerations
While Xilinx data sheets report that there are zero hold times on the
internal registers and I/O registers with the default delay and using
a global clock buffer, it is still possible to receive a $hold
violation from the simulator. This $hold violation is really a $setup
violation on the register. However, in order to get an accurate
representation of the CLB delays, part of the setup time must be
modeled as a hold time. For more information on this modeling, please
refer to Xilinx Answer 782 at the Xilinx Support web site.

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=782

The waveforms in Answer Record 782 looks bad probably because it needs
to be displayed in a fixed font
It was last updated on 08/06/01 and may not apply anymore.

Perhaps Peter can comment on the validity of the Answer Record 782.
Hope this helps.

-Newman


Article: 118117
Subject: Block RAM strange behavior, address off by one
From: "M. Hamed" <mhs000@gmail.com>
Date: 17 Apr 2007 17:13:10 -0700
Links: << >>  << T >>  << A >>
I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every
time I issue a read, the word at the location previous to the given
address is read. For example if I'm reading from address 5, the word
at address 4 is output instead. The data written to the block seems
correct when I view it in ModelSim so I assume it's something with the
read.

Viewing signals at the BRAM input in ModelSim shows the correct
address at the input of port A and the read clock signal goes high but
the wrong word appear at the output. ENA is always 1 and WEA is always
0. The very most recent Write to this same address (from a different
port) also shows the correct value being written.

The design works correctly in RTL but this problem only occurs with
the post-route netlist.

Did anyone encounter a similar problem like this before and can give
me a hint on what's going on.

Thank you.


Article: 118118
Subject: Re: Block RAM strange behavior, address off by one
From: Gabor <gabor@alacron.com>
Date: 17 Apr 2007 19:12:59 -0700
Links: << >>  << T >>  << A >>
On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote:
> I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every
> time I issue a read, the word at the location previous to the given
> address is read. For example if I'm reading from address 5, the word
> at address 4 is output instead. The data written to the block seems
> correct when I view it in ModelSim so I assume it's something with the
> read.
>

This does seem strange.  Are your writes and reads always made to
sequential memory locations (i.e. 1, 2, 3, ... in order)?  Perhaps the
error is in cycle timing and not address?

> Viewing signals at the BRAM input in ModelSim shows the correct
> address at the input of port A and the read clock signal goes high but
> the wrong word appear at the output. ENA is always 1 and WEA is always
> 0. The very most recent Write to this same address (from a different
> port) also shows the correct value being written.
>
> The design works correctly in RTL but this problem only occurs with
> the post-route netlist.
>
> Did anyone encounter a similar problem like this before and can give
> me a hint on what's going on.
>

The only time I've seen something similar was with an old version of
the
BRAM simulation models that needed a slight positive hold time in the
address.  In effect it was the behavioral simulation that incorrectly
gave
the read data on the same clock that the address was presented.  In
fact
BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the
output data should have changed on the following clock cycle.  In the
post-PAR timing simulation, the output changed on the following clock
cycle as expected.

> Thank you.



Article: 118119
Subject: Re: Block RAM strange behavior, address off by one
From: Peter Alfke <alfke@sbcglobal.net>
Date: 17 Apr 2007 20:02:22 -0700
Links: << >>  << T >>  << A >>
A few ideas:
Are you sure about the content of the various locations?
Could the error have happened when you wrote data into the BRAM?

When reading, read twicein sequence from the same address. Then you
will see whether this is a read pipelining problem, or whether you
really are always reading the wrong information.
The error has to somewhere in your timing.

Be a sleuth!
Peter Alfke

On Apr 17, 7:12 pm, Gabor <g...@alacron.com> wrote:
> On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote:
>
> > I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every
> > time I issue a read, the word at the location previous to the given
> > address is read. For example if I'm reading from address 5, the word
> > at address 4 is output instead. The data written to the block seems
> > correct when I view it in ModelSim so I assume it's something with the
> > read.
>
> This does seem strange.  Are your writes and reads always made to
> sequential memory locations (i.e. 1, 2, 3, ... in order)?  Perhaps the
> error is in cycle timing and not address?
>
> > Viewing signals at the BRAM input in ModelSim shows the correct
> > address at the input of port A and the read clock signal goes high but
> > the wrong word appear at the output. ENA is always 1 and WEA is always
> > 0. The very most recent Write to this same address (from a different
> > port) also shows the correct value being written.
>
> > The design works correctly in RTL but this problem only occurs with
> > the post-route netlist.
>
> > Did anyone encounter a similar problem like this before and can give
> > me a hint on what's going on.
>
> The only time I've seen something similar was with an old version of
> the
> BRAM simulation models that needed a slight positive hold time in the
> address.  In effect it was the behavioral simulation that incorrectly
> gave
> the read data on the same clock that the address was presented.  In
> fact
> BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the
> output data should have changed on the following clock cycle.  In the
> post-PAR timing simulation, the output changed on the following clock
> cycle as expected.
>
> > Thank you.



Article: 118120
Subject: Any recommendations for FPGA PCI development board?
From: "hitsx@hit.edu.cn" <hitsx@hit.edu.cn>
Date: 17 Apr 2007 21:17:30 -0700
Links: << >>  << T >>  << A >>
I want to buy a FPGA PCI development board supporting the following
features:
1. Large FPGA device, Xilinx FPGA prefered, especially Virtex2p/
Virtex4/Virtex5 series.
2. PCI(33M/32bit,66M/64bit) bridge interface with license IP Core, or
third party ASIC implemented, or small FPGA(like spartan2 FPGA)
implemented.
3. Detailed and complete reference design for PCI development in both
FPGA side and PC side.

Thanks.


Article: 118121
Subject: Re: vpw/pwm controller
From: ashasravanthi@gmail.com
Date: 17 Apr 2007 21:34:05 -0700
Links: << >>  << T >>  << A >>
On Apr 17, 4:29 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On 16 Apr 2007 01:56:48 -0700,
>
> ashasravan...@gmail.com wrote:
> >hi all,
> >        can anyone tell me where i can get a freevpw/pwmcontroller
> >either in vhdl or verilog according to j1850 standards.
>
> Sounds like we don't know what "j1850" is.  Could you point
> us at a reference somewhere?
>
> Generally, PWM or other pulse generators are so easy to write
> in HDLs that I build them afresh each time I need one, using
> a few standard arrangements that I've used in the past.
> Input register, counter, comparator, output register...
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

hi
   i think i am not clear in my question.i am actually trying to
develop vpw controller but not vpwm signal.  SAE j1850 is automotive
protocol standard.
i am looking for ip cores like j1850 BDLC VPW core by DRIVVEN INC
which is a paid version . i need  free sources similar to that.can
anyone suggest me some refereces for this.


thanks,
ASHA



Article: 118122
Subject: Re: OPB To Wishbone Bridge
From: sheikh.m.farhan@gmail.com
Date: 17 Apr 2007 21:48:59 -0700
Links: << >>  << T >>  << A >>
On Apr 16, 9:31 pm, jetm...@hotmail.com wrote:
> Hi Farhan,
>
> My experience with this wrapper was not a good one.
>
> It won't bridge a memory controller for you, because it has an
> (undocumented) limit of only working in the address range
> 0x80000000-0x800000ff.  It won't signal SI_ToutSup either, resulting
> in another hard-to-meet timing requirement on your memory controller.
>
> I tried to use the bridge to interface with a wishbone ATA host (also
> from opencores). It sort-of worked, but it was far from satisfying.
> Reading the OPB IPIF specs I realized that most signals map one-to-one
> with WB. It was a piece of cake to connect the wishbone peripherial
> directly to the OPB IPIF, without bridge.  Faster, cheaper, better.
>
> Regards,
> Marc

Hi Marc,
Did you get my reply to your answer? I replied to your answer on the
group but I dont see my reply appearing here. I sent my reply to you
directly by using the 'Reply to Author' option. I hope you received
it.

waiting for some more help from you.

Regards
Farhan


Article: 118123
Subject: Re: OPB To Wishbone Bridge
From: sheikh.m.farhan@gmail.com
Date: 17 Apr 2007 21:54:59 -0700
Links: << >>  << T >>  << A >>
On Apr 18, 9:48 am, sheikh.m.far...@gmail.com wrote:
> On Apr 16, 9:31 pm, jetm...@hotmail.com wrote:
>
>
>
>
>
> > Hi Farhan,
>
> > My experience with this wrapper was not a good one.
>
> > It won't bridge a memory controller for you, because it has an
> > (undocumented) limit of only working in the address range
> > 0x80000000-0x800000ff.  It won't signal SI_ToutSup either, resulting
> > in another hard-to-meet timing requirement on your memory controller.
>
> > I tried to use the bridge to interface with a wishbone ATA host (also
> > from opencores). It sort-of worked, but it was far from satisfying.
> > Reading the OPB IPIF specs I realized that most signals map one-to-one
> > with WB. It was a piece of cake to connect the wishbone peripherial
> > directly to the OPB IPIF, without bridge.  Faster, cheaper, better.
>
> > Regards,
> > Marc
>
> Hi Marc,
> Did you get my reply to your answer? I replied to your answer on the
> group but I dont see my reply appearing here. I sent my reply to you
> directly by using the 'Reply to Author' option. I hope you received
> it.
>
> waiting for some more help from you.
>
> Regards
> Farhan- Hide quoted text -
>
> - Show quoted text -

--------------------------------------------------------------------------------------------------------------------------
Since my last reply appeared on the group, let me post my 'lost' reply
once again.
-------------------------------------------------------------------------------------------------------------------------
"Marc, what you are saying is, I should throw away the OPB-> wishbone
wrapper and directly connect the OPB IPIF signals to wishbone (slave,
in my case) signals. Could you kindly give me more details on which
IPIF signal to connect with wishbone slave signals. Following is a
list of the wishbone slave signals that have to talk to OPB via IPIF.

===================================
input            CLK_I;
input            RST_I;
input   [31:0]   ADR_I;
input            CYC_I;
input   [31:0]   DAT_I;
input    [3:0]   SEL_I;
input            STB_I;
input            WE_I;
input    [2:0]   CTI_I;
input    [1:0]   BTE_I;

output  [31:0]   DAT_O;
output           ACK_O;
output           ERR_O;
output           RTY_O;
===================================

I hope I am making some sense here while asking for more details :)

Regards
Farhan


Article: 118124
Subject: ModelSim Waveform naming question
From: motty <mottoblatto@yahoo.com>
Date: 17 Apr 2007 22:13:52 -0700
Links: << >>  << T >>  << A >>
I am using ModelSim SE and was wondering if there is a way to make a
waveform display mnemonics.  I am simulating a state machine and it
would be convenient to have the waveform display the state name
instead of the binary/hex of the state.  I looked all over the
documentation and didn't find anything.

The module is written in verilog and the states are parameterized.  NC-
Sim had an easy way to map numerical values to text.  You create the
mapping and then can apply it to any waveform.  I just haven't found
an easy way to do this in ModelSim.  It is probably staring me in the
face!




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