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walterb wrote: > Give me a fast DSP anyday. They are far more flexible. I have to disagree here. An FPGA provides a very flexible fabric for hosting whatever process you decide to implement. Why, you can even implement a microprocessor if you are so inclined. For the current cost structure, A DSP microprocessor is still the sensible choice IF it complete the task within the allotted time. What the FPGA buys you is the capability of customizing your hardware so that you can compute your algorithm all at once instead of in the sequential manner done by a CPU. The bottom line, is that FPGAs doprovide more flexibility than a CPU, and in many cases higher performance. However, the design path is very different (hardware vs. software), so unfamiliarity with implementing algorithms in hardware or with working within the confines of the FPGA architecture can lead to disappointing results, as Walt has discovered. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12151
Hi, Professor Koren's web page is http://www.ecs.umass.edu/ece/koren/ and the web page for his fantastic book is at http://www.ecs.umass.edu/ece/koren/arith/ There are also javascripts at the webpage that actually show the implementations of things like Booth Multiplication, Wallace Trees, SRT dividers, and more. Take care. James Stine Lehigh University jes6@eecs.lehigh.edu Matthias Brucke wrote: > On Thu, 01 Oct 1998 01:10:52 -0400, "James E. Stine" > <jes6@eecs.lehigh.edu> wrote: > > >... Israel Koren, > >who you may have heard of from University of Massachussetts, provides > >a much better overview of the basics of computer arithmetic > >from an algorithmic point of view. > > Could you please give a URL for that page? > > > > >But, I loved Ray's homepage....Great JOB!!!! > > I agree ;) > > > > > thanks in advance > > Mats > -- > Matthias Brucke Computer Science Departement > VLSI Group University of OldenburgArticle: 12152
The important thing to distinguish is HOW the FIR is implemented in both. DSP's usually use A/D converters with interrupt vectors hooked up to the DSP through the A/D/ converter. Each sample produces an interrupt and processing MUST (and I mean MUST) be completed before each interrupt. However, on DSP's I agree with Ray that FIR's filters might be faster because you can implement any arithmetic you wish. However there will be very complex logic to guarantee that the FIR sample is processed before the next cycle. This may be why walter is having problems. James Stine jes6@eecs.lehigh.edu Ray Andraka wrote: > walterb wrote: > > > Give me a fast DSP anyday. They are far more flexible. > > I have to disagree here. An FPGA provides a very flexible fabric for hosting > whatever process you decide to implement. Why, you can even implement a > microprocessor if you are so inclined. For the current cost structure, A DSP > microprocessor is still the sensible choice IF it complete the task within the > allotted time. What the FPGA buys you is the capability of customizing your hardware > so that you can compute your algorithm all at once instead of in the sequential > manner done by a CPU. > > The bottom line, is that FPGAs doprovide more flexibility than a CPU, and in many > cases higher performance. However, the design path is very different (hardware vs. > software), so unfamiliarity with implementing algorithms in hardware or with working > within the confines of the FPGA architecture can lead to disappointing results, as > Walt has discovered. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 12153
Whatever happened to the Viewlogic synthesis tool called Aurora? I understand that it produced superior results for FPGAs than FPGA-Express. Now that Synopsys bought Viewlogic, is Aurora dead? Rob Weinstein Memec Design Services rob_weinstein@memecdesignDOTcom In article <36124C3D.65BFACDF@viewlogic.com>, John Willoughby <jww@viewlogic.com> wrote: > Check out www.Viewlogic.com. Great tools (Fusion/SpeedWave for VHDL > simulation, FPGA-Express for synthesis, etc.) integrated under the > Intelliflow manager makes a very easy-to-use package from Viewlogic, the > leader in FPGA design solutions. > > John Huang wrote: > > > I want to buy a FPGA tool, do you recommand which > > one is better, how about Accolade and Aldec? > > > > John Huang > > -- > *-------------------------------------------------------* > * John Willoughby ジヨン ウイロビイ * > * System Simulation Mktg office: 508-303-5238 * > * Viewlogic Systems mobile: 508-254-9608 * > * 293 Boston Post Rd West fax: 508-460-7826 * > * Marlboro, MA 01752 email: jww@viewlogic.com * > * * > * "Well done is better than well said" - Ben Franklin * > *-------------------------------------------------------* > > -- Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesignDOTcom -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12154
Hi Michael,
The problem may be that since you have defined a signal 'Q', Altera may be
trying to synthesize an internal tri-stated node; this is not supported in
the 7000 series parts.
Try the following code instead:
entity data_out_unit is
port(data, data_out: in std_logic; -- data_out is a control
signal
SDA: out std_logic); -- SDA connects to a
pull-up resistor bus line
end data_out_unit;
architecture behavior of data_out_unit is
begin
process(data, data_out)
begin
if (data_out = '1') then
SDA <= 'Z';
else
SDA <= data;
end if;
end process;
end behavior;
Article: 12155have you had a look at exemplars new leo spectrum? they are a couple of cool new features in there (integration w/ backend tools, cross-probing), though as a linux guy you probably won't like the new windows like look and feel (actually it feels much better than it looks :-) download it from their web (26MB, but what the heck, an ok 3d demo game has same size ;-) then get a eval license and go endric AXIS Systems Inc. Jake Janovetz wrote in message <6uvuou$jdh@tempest.ece.uiuc.edu>... > >Howdy all... > > I'm wondering what the main differences are between the >Exemplar and Synopsys synthesis tools for FPGAs. I'm not >interested in hearing that "most people use Synopsys." >(Linux is better than Windows, so it is clear the "most people" >make the wrong decision) > Opinions are fine, I'd just like to hear how people chose >between the two. Incidentally, I use Leonardo (Exemplar) and >like it. But I haven't used Synopsys all that much to form >a decision. > > > Cheers, > Jake > > >-- > janovetz@uiuc.edu | Once you have flown, you will walk the earth with > University of Illinois | your eyes turned skyward, for there you have been, > | there you long to return. -- da Vinci > PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.htmlArticle: 12156
Viewlogic sells and supports FPGA Express which is our synthesis tool of choice. FPGA Express provides excellent quality of results and is integrated into Viewlogic's IntelliFlow FPGA Design Manager. Aurora was retired as a Viewlogic product almost one year ago. Philip Lewer Viewlogic Systems In article <6v096f$tnt$1@nnrp1.dejanews.com>, pipjockey@my-dejanews.com wrote: > Whatever happened to the Viewlogic synthesis tool called Aurora? I understand > that it produced superior results for FPGAs than FPGA-Express. Now that > Synopsys bought Viewlogic, is Aurora dead? > > Rob Weinstein > Memec Design Services > rob_weinstein@memecdesignDOTcom > > In article <36124C3D.65BFACDF@viewlogic.com>, > John Willoughby <jww@viewlogic.com> wrote: > > Check out www.Viewlogic.com. Great tools (Fusion/SpeedWave for VHDL > > simulation, FPGA-Express for synthesis, etc.) integrated under the > > Intelliflow manager makes a very easy-to-use package from Viewlogic, the > > leader in FPGA design solutions. > > > > John Huang wrote: > > > > > I want to buy a FPGA tool, do you recommand which > > > one is better, how about Accolade and Aldec? > > > > > > John Huang > > > > -- > > *-------------------------------------------------------* > > * John Willoughby ジヨン ウイロビイ * > > * System Simulation Mktg office: 508-303-5238 * > > * Viewlogic Systems mobile: 508-254-9608 * > > * 293 Boston Post Rd West fax: 508-460-7826 * > > * Marlboro, MA 01752 email: jww@viewlogic.com * > > * * > > * "Well done is better than well said" - Ben Franklin * > > *-------------------------------------------------------* > > > > > > -- > Rob Weinstein > Memec Design Services - Phoenix > rob_weinstein@memecdesignDOTcom > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 12157
Viewlogic sells and supports FPGA Express which has excellent quality of results for programmable devices. FPGA Express is integrated into IntelliFlow which is Viewlogic's FPGA design manager. Aurora has been retired as a Viewlogic product for almost a year now. FPGA Express produces superior results to Aurora. Philip Lewer Viewlogic Systems In article <6v096f$tnt$1@nnrp1.dejanews.com>, pipjockey@my-dejanews.com wrote: > Whatever happened to the Viewlogic synthesis tool called Aurora? I understand > that it produced superior results for FPGAs than FPGA-Express. Now that > Synopsys bought Viewlogic, is Aurora dead? > > Rob Weinstein > Memec Design Services > rob_weinstein@memecdesignDOTcom > > In article <36124C3D.65BFACDF@viewlogic.com>, > John Willoughby <jww@viewlogic.com> wrote: > > Check out www.Viewlogic.com. Great tools (Fusion/SpeedWave for VHDL > > simulation, FPGA-Express for synthesis, etc.) integrated under the > > Intelliflow manager makes a very easy-to-use package from Viewlogic, the > > leader in FPGA design solutions. > > > > John Huang wrote: > > > > > I want to buy a FPGA tool, do you recommand which > > > one is better, how about Accolade and Aldec? > > > > > > John Huang > > > > -- > > *-------------------------------------------------------* > > * John Willoughby ジヨン ウイロビイ * > > * System Simulation Mktg office: 508-303-5238 * > > * Viewlogic Systems mobile: 508-254-9608 * > > * 293 Boston Post Rd West fax: 508-460-7826 * > > * Marlboro, MA 01752 email: jww@viewlogic.com * > > * * > > * "Well done is better than well said" - Ben Franklin * > > *-------------------------------------------------------* > > > > > > -- > Rob Weinstein > Memec Design Services - Phoenix > rob_weinstein@memecdesignDOTcom > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12158
After reading all the good ideas on this topic, I thought I'd throw in my 2 cents. Having worked for a PLD company for 9 years I think I have seen most of the creative schemes for security protection. I've also seen them all broken by the Taiwanese game copiers. In the end, the only security scheme I've seen work consistently is to ship parts with no vendor lablel only a customer designs #. This way the people trying to copy the device have not idea if it's programmable, an ASIC or standard product. Simple and very effective. Derek Palmer Peter wrote: > >This is not beyond the realm of battery backup, but certainly isn't going > >to last long on a coin-cell. Two or three AA size ni-cad batteries though > >would be fine for a system that is not turned off for days at a time. > >An AA rechargeable will supply 5mA for 130 hours or more, depending on > >chemistry. AA nicads are rated for 650 to 800mAH. NMH batteries are > >around 1250mAH ( 250 hours at 5mA). > > I spent a lot of time working with batteries, once upon a time. > > I would avoid Nicads. They tend to fail, within 10 years, into a short > circuit (actually a low impedance) mode. I have seen this in hundreds > of them, in products I designed long ago! Lithiums are the proper way > but as you say, not much good at 5mA. > > Also, the Nicad in every consumer product I have ever bought has > failed within 10 years, often much less. > > NMH I have not used in my own designs, but those I have here in the > workshop tend to self-discharge within a few months at most. Those in > my $3k Toshiba go flat within a month. > > But 5mA static Icc seems high. I recall the 3142 etc (emphasis on the > "1") used 5mA at DC but most Xilinx parts draw only microamps. Why not > use one of those? > > Sanyo Energy make some very nice rechargeable lithiums; their only > minus is that the mAh capacity is about 1/5 of what you get with a > same-size primary version. They have a 10+ year shelf life to a 50% > discharge - amazing for a rechargeable cell. Easy constant voltage > trickle charge, too. > > The other issue with batteries is that one cannot reflow solder them. > They have to be either hand soldered, flow soldered (quickly!), or > fitted into a holder whose contacts are going to corrode over time. > > -- > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but > remove the X and the Y.Article: 12159
Re: Wallace Trees I have heard that Wallace trees do not "lay out" efficiently in VLSI, because the wire density is too high. This is an unsubstantiated romour - I'm no expert in this area. There was a good paper in IEEE Transactions on Computers in early 1993, I believe, by Earl Swartzlander, concerning the combinatorial optimization of a fast lookahead adder for the 29000 series of microprocessors. This one had good specs for the fab process (4 ns, in a1990 or 1991 process) and also a very compact layout. It also described a computer algorithm that would let you trade off lookahead parameters (generate & propagate) dependinging on your speed/area requirements. Good luck, Donald Gillies, Ph.D. - t_dgilli@qualcomm.com - Planetwide Software, Inc. (consultant) / Globalstar Satellite CDMA Project, Qualcomm Inc., 6455 Lusk Blvd San Diego, California 92121 - phone: 619-651-2326. Adjunct Professor of EE, UBC, Vancouver BC Canada V6T 1Z4 http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.htmlArticle: 12160
The irregular routing in Wallace trees do make them unattractive for VLSI implementation according to several articles I have read (I am not a VLSI expert). That routing makes for an even worse implementation in FPGAs (where my expertise lies). Donald Gillies wrote: > Re: Wallace Trees > > I have heard that Wallace trees do not "lay out" efficiently in VLSI, > because the wire density is too high. This is an unsubstantiated > romour - I'm no expert in this area. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12161
WHEN WILL THESE PEOPLE GET THE IDEA?!?!
We don't want Windows applications! I need to be able to use Make and
other CLI features. Ooooh, this really pisses me off.
Thanks for the pointer, I may check it out.
Cheers,
Jake
"jj" <jj@do.gov> writes:
>have you had a look at exemplars new leo spectrum? they are a couple of cool
>new features in there (integration w/ backend tools, cross-probing), though
>as a linux guy you probably won't like the new windows like look and feel
>(actually it feels much better than it looks :-)
>download it from their web (26MB, but what the heck, an ok 3d demo game has
>same size ;-)
>then get a eval license and go
>endric
>AXIS Systems Inc.
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 12162Stephen Peddle <smp@spam.com> wrote in article <VWQO1.380$Ba.272115@typhoon.mbnet.mb.ca>... > I just talked to my rep yesterday and was told Foundation 1.5 is shipping > ... BUT > there are a lot of us using it, and it could take up to a month to complete > all the shipments. > > ie if you need it right away, you should probably ask for it. > > Also, when you get your 1.5, don't forget to check the web site for the > latest patches. (Yes they have already uploaded some!) > My copy came today (1 October). What's funny is that yesterday I called the Xilinx office in Phoenix and they said it could be a couple more weeks... -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAMArticle: 12163
Hi, Yes, they do have very irregular layouts. Research has shown that SD (signed-digit) adders have better layouts regularity but suffer from actual conversion to normal representation although Milos Ercegovac and Tomas Lang has shown some on-the-fly conversion routines which convert nicely. Furthermore, some more research has been done with what is called 4-2 compressors and has shown that these layouts have very regular layouts. Its a very intersting topic! They is plenty of research into these topics from the IEEE Symposium on Computer ARithmetic which is held every two years. James Stine jes6@eecs.lehigh.edu Donald Gillies wrote: > Re: Wallace Trees > > I have heard that Wallace trees do not "lay out" efficiently in VLSI, > because the wire density is too high. This is an unsubstantiated > romour - I'm no expert in this area. > > There was a good paper in IEEE Transactions on Computers in early > 1993, I believe, by Earl Swartzlander, concerning the combinatorial > optimization of a fast lookahead adder for the 29000 series of > microprocessors. This one had good specs for the fab process (4 ns, > in a1990 or 1991 process) and also a very compact layout. It also > described a computer algorithm that would let you trade off lookahead > parameters (generate & propagate) dependinging on your speed/area > requirements. > > Good luck, > > Donald Gillies, Ph.D. - t_dgilli@qualcomm.com - Planetwide Software, Inc. > (consultant) / Globalstar Satellite CDMA Project, Qualcomm Inc., > 6455 Lusk Blvd San Diego, California 92121 - phone: 619-651-2326. > Adjunct Professor of EE, UBC, Vancouver BC Canada V6T 1Z4 > http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.htmlArticle: 12164
Hi - I'm looking for QuickLogic programming hardware, in case somebody out there wants to liquidate some assets. In particular, a programmer base, 208 adaptor, and 100/144 adaptor... thanks - - Jesse -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12165
hi, it seems easy enough to just pop the top off of the part - a lot of chips that i've seen, using a regular lab scope, make it easy for you as they write the chip name in the corner. or if you want to get scientific you can look at the structure and compare it to the fpga's you have piled up on the bench. for a few hundreds of dollars you can make a pretty good library. am i missing something? rk Derek Palmer wrote: > After reading all the good ideas on this topic, I thought I'd throw in my 2 > cents. > Having worked for a PLD company for 9 years I think I have seen most of the > creative schemes for security protection. I've also seen them all broken by > the Taiwanese game copiers. In the end, the only security scheme I've seen > work consistently is to ship parts with no vendor lablel only a customer > designs #. This way the people trying to copy the device have not idea if > it's programmable, an ASIC or standard product. Simple and very effective. > > Derek PalmerArticle: 12166
On 1 Oct 1998 20:09:27 -0500, janovetz@tempest.ece.uiuc.edu (Jake
Janovetz) wrote:
>
>WHEN WILL THESE PEOPLE GET THE IDEA?!?!
>
>We don't want Windows applications! I need to be able to use Make and
>other CLI features. Ooooh, this really pisses me off.
>
>Thanks for the pointer, I may check it out.
>
As far as I am aware the "Windows look and feel" in Leonardo is just a
TCL/TK front end to a command line program ("elsyn" at the prompt).
I'm using Leonardo 4.2.2 so I don't know what the situation is with
Leonardo Spectrum, but I would think that it is the same.
Hope this helps.
Dave
--
REPLACE "NOJUNK" in address with "david.storrar" to reply
Development Engineer |
Marconi Electronic Systems | Tel: +44 (0)131 343 4484
RCS | Fax: +44 (0)131 343 4091
Article: 12167Hello, I have trouble with installation of ISP Synario on WinNTpl platform (pl means polish NT version). After step-by-step installation I tried load ISP Synario Starter, I could see only window "ntolesrv". In process manager I could see "projnav.exe" but I couldn't see window with Project Navigator. I tried install this on some workstations with the same result. I tried to delete "license.dat" file and window with error didn't display - situation was as discribed above. I tried install this on Win95OSRpl without any problems. Best regards, Pawel Tomaszewicz -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 12168
On 1 Oct 1998 20:09:27 -0500, janovetz@tempest.ece.uiuc.edu (Jake Janovetz) wrote: > >WHEN WILL THESE PEOPLE GET THE IDEA?!?! > >We don't want Windows applications! I need to be able to use Make and >other CLI features. Ooooh, this really pisses me off. Well, check out Synplify which is a great Synthesis tool in my opinion. It is available for Solaris, Sunos, HP-UX and Windows. Goto http://www.synplicity.com/ JonasArticle: 12169
Hello, I have trouble with installation on WinNTpl platform (pl means polish version). After step-by-step installation I tried load ISP Synario Starter, I could see only window "ntolesrv". In process manager I could see "projnav.exe" but I couldn't see window with Project Navigator. I tried install this on some workstations with the same result. I tried to delete "license.dat" file and window with error didn't display - situation was as discribed above. I tried install this on Win95OSRpl without any problems. Please help me, in our Digital Circuit Laboratory are some NT Workstations. Best regards, Pawel Tomaszewicz -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12170
In article <6urnq8$6ut$1@aggedor.rmit.edu.au>, s9510300@cse.rmit.EDU.AU (Giang Thach Nguyen) wrote: > Does anyone know how to report delay of internal signals with Altera's Maxplus2 Timing Analyzer? I can only get the delay from one I/O pin to another I/O pin. Any input would be appreciated. > Open Timing Analyzer window, >From pull down menu choose Node, Timing Analyzing Source ..., In window Timing Analyzing Source check Type/All and click on List button. Pawel Tomaszewicz -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12171
--------------42F5F2587FF2CBAD6805BC7E Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Rickman wrote: > Jake Janovetz wrote: > One possibly big difference, depending on whether you have existing > code, is that Synopsys does not support VHDL-93. They seem to be pretty > stuck in VHDL-87. > > Otherwise, I can only stay that Synopsys is what comes with Xilinx > Foundation, so a lot of Xilinx users have it! ;) > I've heard from a Synopsys representative that vhdl-93 support is close. Regards Hans Lindkvist, M.Sc.and Lic.Tech in Comp.Eng. Senior Staff Engineer, Advanced Studies, Digital ASIC Research and Wideband Terminals Ericsson Mobile Communications AB Tel : Int+46 46 19 38 66 Scheelev臠en 15 Fax : Int+46 46 19 34 55 S-221 83 LUND Email: Hans.Lindkvist@ldecs.ericsson.se SWEDEN --------------42F5F2587FF2CBAD6805BC7E Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> Rickman wrote: <BLOCKQUOTE TYPE=CITE>Jake Janovetz wrote: <BR>One possibly big difference, depending on whether you have existing <BR>code, is that Synopsys does not support VHDL-93. They seem to be pretty <BR>stuck in VHDL-87. <P>Otherwise, I can only stay that Synopsys is what comes with Xilinx <BR>Foundation, so a lot of Xilinx users have it! ;) <BR> </BLOCKQUOTE> <PRE>I've heard from a Synopsys representative that vhdl-93 support is close.</PRE> Regards <BR>Hans Lindkvist, M.Sc.and Lic.Tech in Comp.Eng. <BR>Senior Staff Engineer, Advanced Studies, Digital ASIC <BR>Research and Wideband Terminals <BR> <BR>Ericsson Mobile Communications AB Tel : Int+46 46 19 38 66 <BR>Scheelevägen 15 Fax : Int+46 46 19 34 55 <BR>S-221 83 LUND Email: Hans.Lindkvist@ldecs.ericsson.se <BR>SWEDEN <BR> </HTML> --------------42F5F2587FF2CBAD6805BC7E--Article: 12172
pawel5732@my-dejanews.com wrote: > Hello, > I have trouble with installation of ISP Synario on WinNTpl platform (pl means > polish NT version). After step-by-step installation I tried load ISP Synario > Starter, I could see only window "ntolesrv". In process manager I could see > "projnav.exe" but I couldn't see window with Project Navigator. I tried > install this on some workstations with the same result. > I tried to delete "license.dat" file and window with error didn't > display - situation was as discribed above. > I tried install this on Win95OSRpl without any problems. > Best regards, > Pawel Tomaszewicz > Pawel, I don't believe the free version of Synario from Lattice (Synario ISP) will run on NT. We (Synario) have versions that will run on NT, but unfortunately they are not free. Sorry. I will check to see if there is any work around for your issue. Please contact me if you have any other issues. Jay Doherty Minc Washington/Synario Design Automation 508-893-7944Article: 12173
Kevin Horton wrote: > Is it possible to get the NFX780-series of chips any more? I've looked around > and cannot seem to find these for sale anywhere any more. I would really like > to get my hands on several more of this chips (say, 2-10 or more depending on > price) for my own projects. If I cannot get these any more, is there another > similar part I can use? I already have the "dev system" for these parts > (read: PLDshell and a parallel port :-) and this chip is perfect for my needs > and budget. I assume you're talking about the parts I know as the Altera EPX780 that was originally the Intel FX780. The bad news is that Altera stopped making them and they are so difficult to find that we've had to re-spin a board around the Xilinx 95xx series. Even if you do find some be careful as the last trawl we did found a batch of chips that didn't work!!Article: 12174
I'm looking for a reasonably priced Verilog simulator to add to our Xilinx Foundation+Express package. So far I can see VeriWell, Chronologic, QuickTurn. Anybody have any comments on these or others. We could go to $5000 which I assume writes off Cadence. Also looking for a Verilog PCI testbench suite.
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