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Messages from 121800

Article: 121800
Subject: Re: Counter ?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 13 Jul 2007 13:46:43 +0100
Links: << >>  << T >>  << A >>
On Fri, 13 Jul 2007 13:04:20 +0100, <miche> wrote:

 repeat(3)
>Yes, see my last post 2 day ago.
;

Why should anyone *except you* waste time trawling
through a NG looking for posts by you, when
you can't be bothered to include either a reference
or the germane content in your question?

Contrary to what appears to be your opinion, the 
world does not owe you a living, but only a 
fair hearing.  You'll get that soon enough if
you make a fair attempt to be heard.

I could write a solution to your counter problem
in considerably less time than it's taken me to
write this, but I don't really see the point.
Looks like plenty of other people feel pretty 
much the same way.  At least two of the people
who replied to this thread have a spectacularly 
impressive history of pertinent, courteous and
expert responses to various questions.  The
balance of evidence is that it's not *their*
fault that you're dissatisfied.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 121801
Subject: Re: CML output swing for V5
From: "Eddie H" <>
Date: Fri, 13 Jul 2007 05:47:41 -0700
Links: << >>  << T >>  << A >>
John,

Currently I have connected SMAs from ML523 to the Tektronix probe P7313SMA. This is a point to point connection and there is no other load.

I am using Tektronix P7313SMA probes. It says that the probe input has 50 Ohm termination. 13 GHz Typical.

Also I am using Tektronix DSA71254 scope. It is 12.5 GHz, 50 GS/sec scope.

Please let me know if I need to change my setup.

Thanks.

Eddie

Article: 121802
Subject: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
From: Patrick Dubois <prdubois@gmail.com>
Date: Fri, 13 Jul 2007 12:59:35 -0000
Links: << >>  << T >>  << A >>
On Jul 13, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote:

> Hi Patrick,
> So I'm still using 8.2, and this isn't the behaviour I see. An import
> overwrites any previous edits. Is this a new feature for 9.1?
>
> > In order to help you setting up the Chipscope Analyzer project, take a
> > look at csptool:
> >http://code.google.com/p/csptool/
>
> I downloaded it, sounds interesting, many thanks.
>
> All the best, Syms.

I have been using Chipscope since v7 and I think that it's always been
like that. After you load a new bit file, disconnect and reconnect the
JTAG (JTAG chain menu). Chipscope will then discover that the number
of signals changed and a dialog will pop-up asking if you want to
preserve signals names (choose yes). Then you will see new unnamed
signals in your signals list (they won't be in the waveform). Now you
can simply import the new cdc file to retreive the name of these new
signals. The rest of the Analyzer design should stay intact.

Cheers,
Patrick



Article: 121803
Subject: Re: CML output swing for V5
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 13 Jul 2007 13:13:13 GMT
Links: << >>  << T >>  << A >>
Eddie H wrote:
> John,
> 
> Currently I have connected SMAs from ML523 to the Tektronix probe P7313SMA. This is a point to point connection and there is no other load.
> 
> I am using Tektronix P7313SMA probes. It says that the probe input has 50 Ohm termination. 13 GHz Typical.
> 
> Also I am using Tektronix DSA71254 scope. It is 12.5 GHz, 50 GS/sec scope.
> 
> Please let me know if I need to change my setup.
> 
> Thanks.
> 
> Eddie

Super!

Yes, the setup will cause problems.  The current mode singals are 
current sinks if I understand CML properly.  THe pull=up terminations in 
the transmitter will be pulled from 1.2V by that switchable current 
sink.  If you have 50 ohms to ground, you now see an equivalent 
impedance of less than 50 ohms to an equivalent termination far below 1.2V.

Look at the receiver arrangement in the RocketIO user guide we pointed 
out yesterday.  If you can configure your setup to mimic that receiver, 
the CML voltage will look proper again.

Personally, for looking at common mode voltage, I'd connect the signal 
to the normal CML receiver and use the high-impedance FET probe to tap 
onto the signal.  The signal fidelity may go from good to miserable with 
the extra impedance even if it is a "small" impedance; nothing's really 
"small" at Rocket IO rates.  Even though your receiver may have troubles 
getting good data when you're probing, the common mode voltage should be 
accurate and you would have a "flavor" of the voltage swing.

Thanks for sharing the setup.  It should be a pretty quick 
reconfiguration if you have or can arrange a proper receiver.

- John_H

Article: 121804
Subject: Re: Counter ?
From: christopher.saunter@durham.ac.uk (c d saunter)
Date: Fri, 13 Jul 2007 13:13:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jon Beniston (jon@beniston.com) wrote:
: On 13 Jul, 11:51, <miche> wrote:
: > Hello,
: > I require a counter which counts up on positive clock;
: > can be reset to zero upon a reset signal;
: > will stop counting when reached max or rollover;
: > will restart counting only after a total reset, which is
: > not the same as the counter reset. (2 resets)
: > Waiting with anticipation.
: > Thanks.

: Will this do:

: http://tools.arantius.com/stopwatch

: Cheers,
: Jon

Jon that only has one reset - the OP clearly
mentioned that 2 are required...

:)

Cheers,
	Chris

Article: 121805
Subject: Re: Counter ?
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 13 Jul 2007 13:18:24 GMT
Links: << >>  << T >>  << A >>
miche wrote:
> Hello,
> I require a counter which counts up on positive clock;
> can be reset to zero upon a reset signal;
> will stop counting when reached max or rollover;
> will restart counting only after a total reset, which is
> not the same as the counter reset. (2 resets)
> Waiting with anticipation.
> Thanks.

If you were to write the function in C code, what would it look like? 
I'm hoping you have the software background.

You're working with CPLDs which isn't the typical homework assignment 
thing.  Are you taking your first steps into programmable logic?  Are 
you a hobbyist, electrical engineer, student, or software guy?  Knowing 
this can help us shape our response.

And please start asking questions rather than telling us something and 
waiting.

- John_H

Article: 121806
Subject: Re: ASM within C code in a PPC405 of VIRTEX II Pro
From: LilacSkin <lpaulo07@iseb.fr>
Date: Fri, 13 Jul 2007 06:21:12 -0700
Links: << >>  << T >>  << A >>
Ok !
If i want to call an ASM function with a C code, for example:
in main.c:

int a=11;
int b=12;
int result;

result = add(a,b);

in add.asm:

*add(int a, int b)
*       r1      r2
add: addi r1,r2
mr r0,r1
blr

It works ?
Tk !!!



Article: 121807
Subject: Re: highly-parallel highspeed connection between two FPGA boards
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 13 Jul 2007 14:37:52 +0100
Links: << >>  << T >>  << A >>
"Maurice Branson" <traubenuss@arcor.de> wrote in message 
news:46971c5b$0$3830$9b4e6d93@newsspool4.arcor-online.net...
> Tanks for your answers so far!
>
> Oay, to make it more precise: I'm looking for an interconnect system 
> (multi-channel plug + receptacle) for 24 differential pairs at signaling 
> rates of 3 - 6 Gbps per channel.
>
>
Hi Maurice,
Dunno if this fits your requirements, but these are cheap and v. fast. Maybe 
20Gb/s.
http://www.samtec.com/ftppub/testrpt/hsc-report_sal1-bottom-entry_web.pdf
HTH, Syms.
p.s. Looks like 'bottom entry' is the way to go!



Article: 121808
Subject: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
From: "jacobusn@xilinx.com" <naude.jaco@gmail.com>
Date: Fri, 13 Jul 2007 13:46:18 -0000
Links: << >>  << T >>  << A >>
Do you have a DCM that you instantiate yourself? If you generate a
controller with MIG without a DCM you still need to have your own DCM
outside the controller to remove skew from your clocks. Otherwise this
can give you problems later on. I would really recommend generating
your MIG design with the DCM etc. taken care of already unless you are
experienced enough or you run out of DCMs.

The problem that you get in MAP is because the clock that drives the
REFCLK on the IDELAYCTRL is not on global routing. I would recommend
that you have a look at the MIG User Guide and make sure your signals
matches the signals shown in the Top-Level Block Diagrams. You will
see that the clk_200 that drives the idelay_ctrl must come out of a
DCM.

Hope this helps,
Cheers


Article: 121809
Subject: Re: SystemC in modeling HW/SW
From: Patrick Dubois <prdubois@gmail.com>
Date: Fri, 13 Jul 2007 13:46:29 -0000
Links: << >>  << T >>  << A >>
On Jul 10, 10:24 pm, Ace <yasi...@gmail.com> wrote:
> Hi,
>
> I was told by a friend that SystemC is currently the best to modeling
> hw/sw design. I've read on the internet where people were saying that
> SystemC is a more "complete model" which I don't quite understand.
> I've look at several other tools for example Impulse C that gave a
> very good description on how hw/sw  modeling can be done easily using
> Impulse C.
>
> Could anyone be kind to share why do you think systemC is the best
> tool to model hw/sw and how? I'm open to any good source should you
> wish to share.
>
> Cheers!

Well, I'm not sure I can compare it to other alternatives but I can
give you an idea of how I use SystemC in a hw/sw design.

I created a SystemC model of the PowerPC used in the Ultracontroller-
II configuration (only 32 inputs, 32 outputs). It is very fast because
very simple (not cycle accurate because it simulates at the source
code level, never at the assembly level).

With my simulator (Active-HDL), I can then do a cosimulation of the hw
(vhdl) and sw (program in C, PPC model in SystemC). My PPC program is
in C but I compile everything in SystemC (since SystemC is C++, and C
can be made compatible with C++).

In my case, the alternative for co-simulation would have been to use
the swift model of the PPC, which I need an additional license for
from my simulation vendor, and is quite slow anyway apparently.

Now, what would be nice would be a SystemC model of the full PowerPC,
instead of the swift model.

Patrick


Article: 121810
Subject: Re: Designing the right clock tree for a multi-FPGA setup
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 13 Jul 2007 06:52:18 -0700
Links: << >>  << T >>  << A >>
On Thu, 12 Jul 2007 17:56:19 +0200, "Geronimo Stempovski"
<geronimo.stempovski@arcor.de> wrote:

>Hi folks,
>
>I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some 
>periphery. The three FPGAs are needed due to the data processing complexity 
>and the amount of high-speed IOs (MGTs). What I am most concerned about 
>right now is to find an appropriate clocking solution.
>
>In my opinion, there are mainly three alternatives to design the clocking 
>scheme:
>
>a) connection of the clock in a star-like topology, feeding each of the 
>three FPGAs with the same clock signal (which has to be possibly duplicated 
>by a clock buffer to generate three out of one clock reference signal, 
>thereby introducing additional jitter)
>
>b) clock in daisy-chain, feeding each of the three FPGAs with the identical 
>clock signal which is routed from one device to another (in terms of jitter 
>this is also not an optimal solution)
>
>c) each FPGA device is supplied with its own clock (which than can be 
>optimally routed to the device in short distances), but synchronization is a 
>major issue then
>
>Does anyone have sufficient experience in designing clock trees and is 
>willing to share his experience, comments, hints and suggestions with me?
>
>Thanks in advance
>
>Gero 
>

The most conservative way to do this would be to use three LVDS
drivers at the oscillator (or one of those new fancy LVDS clock
driver/tweaker chips), go differential star-routed to each chip, and
terminate at each one. Most FPGAs accept differential clocks these
days. That said, it's still a good idea to route the diff clock traces
carefully, low-skew, good impedance control, and away from any
crosstalk aggressors.

We also like to use a fast, hard 3.3 volt single-ended driver, source
terminated, and put a tiny logic schmitt trigger at the other end,
right next to the fpga clock input. FPGA clock inputs tend to have
little or no edge-noise immunity, and are hyper-delicate, so the
schmitt really helps if you're not running super fast and can tolerate
the added delay.

Long single-trace daisy chains are the riskiest, unless you regenerate
the clock at every way-station.

John


Article: 121811
Subject: Re: Designing the right clock tree for a multi-FPGA setup
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 13 Jul 2007 14:53:00 +0100
Links: << >>  << T >>  << A >>
"Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message 
news:46964f24$0$3841$9b4e6d93@newsspool4.arcor-online.net...
> Hi folks,
>
> I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some 
> periphery. The three FPGAs are needed due to the data processing 
> complexity and the amount of high-speed IOs (MGTs). What I am most 
> concerned about right now is to find an appropriate clocking solution.
>
> In my opinion, there are mainly three alternatives to design the clocking 
> scheme:
>
> a) connection of the clock in a star-like topology, feeding each of the 
> three FPGAs with the same clock signal (which has to be possibly 
> duplicated by a clock buffer to generate three out of one clock reference 
> signal, thereby introducing additional jitter)
>
Hi Geronimo,
This alternative will work. You should use a clock buffer to duplicate your 
clock three times.. The amount of jitter is generates will be at least an 
order of magnitude less than the jitter introduced just getting on to the 
FPGAs' internal clock trees.
>
> b) clock in daisy-chain, feeding each of the three FPGAs with the 
> identical clock signal which is routed from one device to another (in 
> terms of jitter this is also not an optimal solution)
>
You might also consider source synchronous busses to get data between FPGAs 
in addition to the star topology.
>
> c) each FPGA device is supplied with its own clock (which than can be 
> optimally routed to the device in short distances), but synchronization is 
> a major issue then
>
I see no advantages in using this third method.
>
> Does anyone have sufficient experience in designing clock trees and is 
> willing to share his experience, comments, hints and suggestions with me?
>
> Thanks in advance
>
> Gero
>
It's hard to advise you without a specific set of requirements, but I'd say 
your design stands a good chance of success simply because you're thinking 
hard about this up front! :-)
HTH., Syms. 



Article: 121812
Subject: Re: Counter ?
From: <miche>
Date: Fri, 13 Jul 2007 14:53:15 +0100
Links: << >>  << T >>  << A >>
> And please start asking questions rather than telling us something and
> waiting.

The question was asked two days ago.
I will not repost it. If people can't find it then that's fine.

I need a counter that count up from 0 to 15
When reaching 15 or 0 again - stop
Reset1 clears counter to zero
Reset2 starts counter
Language - verilog



Article: 121813
Subject: Xilinx V4 Custom IP
From: SWAmdata@gmail.com
Date: Fri, 13 Jul 2007 06:57:57 -0700
Links: << >>  << T >>  << A >>
I am trying to write a simple custom IP to get started.  I just want
to control the LED on my evaluation board.  I want to be able to write
a custom IP to prove to myself I am doing it correctly instead of
using the IP provided.

I am using a Memec V4 UltraController II eval board and EDK 9.1 SP2.
I created a template IP using EDK and then wrote my VHDL code to
control the LEDs.  The problem is I have no control over the LEDs.

In my led.vhd file I added to my entity and architecture:
    --USER ports added here
    pLED1									: out std_logic;
    pLED2									: out std_logic;
    pLED3									: out std_logic;

Then in user logic I added some internal signals to my architecture:

 signal iLED1									 : std_logic := '1';
  signal iLED2									 : std_logic := '0';
  signal iLED3									 : std_logic := '0';

And finally I added some assignments at the end of the architecture:
  pLED1 <= iLED1;
  pLED2 <= iLED2;
  pLED3 <= slv_reg0(2);

slv_reg0 is a register that can be written to and read over the OPB.
The slv_reg0 can be read and written through  XMD, but the LEDs do not
change.  Also using the default signal values, LED1 & LED2 should have
different states, but all 3 LEDs have the same state.

For completion I added:

Net fpga_0_LED1_pin LOC = D13 | IOSTANDARD = LVCMOS25;
Net fpga_0_LED2_pin LOC = D12 | IOSTANDARD = LVCMOS25;
Net fpga_0_LED3_pin LOC = D11 | IOSTANDARD = LVCMOS25;

to the system.ucf file.  And I added:

PORT fpga_0_LED1_pin = fpga_0_LED1, DIR = O
 PORT fpga_0_LED2_pin = fpga_0_LED2, DIR = O
 PORT fpga_0_LED3_pin = fpga_0_LED3, DIR = O

and

BEGIN opb_leds
 PARAMETER INSTANCE = opb_leds_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x73c00000
 PARAMETER C_HIGHADDR = 0x73c0ffff
 BUS_INTERFACE SOPB = opb
 PORT pLED1 = fpga_0_LED1
 PORT pLED2 = fpga_0_LED2
 PORT pLED3 = fpga_0_LED3
END

to the system.mhs file.

Does any see why the LEDs do not change state?

Thanks,
Glenn


Article: 121814
Subject: Re: Counter ?
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 13 Jul 2007 15:00:10 +0100
Links: << >>  << T >>  << A >>
<miche> wrote in message news:469783cb$1_1@mk-nntp-2.news.uk.tiscali.com...
>> And please start asking questions rather than telling us something and
>> waiting.
>
> The question was asked two days ago.
> I will not repost it. If people can't find it then that's fine.
>
Hi Miche,
A few days ago I posted here a link that explained how to ask technical 
questions on newsgroups in order to maximise your chance of a useful reply. 
I will not repost it. If you can't find it then that's fine.
HTH, Syms.



Article: 121815
Subject: Re: Counter ?
From: PFC <lists@peufeu.com>
Date: Fri, 13 Jul 2007 16:06:23 +0200
Links: << >>  << T >>  << A >>

> The question was asked two days ago.
> I will not repost it. If people can't find it then that's fine.

	Ok, fine ;)

> I need a counter that count up from 0 to 15
> When reaching 15 or 0 again - stop
> Reset1 clears counter to zero
> Reset2 starts counter
> Language - verilog

	I do that for you according to the following pro forma bill :

- copying example from page 10 of Verilog book....		$10
- adding 5 lines of code		$125
- simulation and testing (optional)	$50
- shipping and handling (by email)	$0.3
- lawyer to sign IP contract & NDA	$4000
- writing on a mailing list where at least 300 people can solve your  
problem in 2 minutes and not getting any answer because you start your  
message with "I need" and forgot to say "please" ...	Priceless !
	

Article: 121816
Subject: Re: Counter ?
From: Jon Beniston <jon@beniston.com>
Date: Fri, 13 Jul 2007 07:06:48 -0700
Links: << >>  << T >>  << A >>

> The question was asked two days ago.
> I will not repost it. If people can't find it then that's fine.
>
> I need a counter that count up from 0 to 15
> When reaching 15 or 0 again - stop
> Reset1 clears counter to zero
> Reset2 starts counter
> Language - verilog

What are the polarity of the resets?

Does reset1 enable the counter, disable it, or no change?

What are the timing constraints?

How does it reach 0 if counting up?

Are you resets synchronous or asynchronous?

Which clock edge do you wish to count on?

What are the outputs?

Cheers,
Jon



Article: 121817
Subject: Re: Counter ?
From: <miche>
Date: Fri, 13 Jul 2007 15:18:56 +0100
Links: << >>  << T >>  << A >>
From your earlier response I doubt if this is for real,
but I am desperate, so I'll reply

> What are the polarity of the resets?
You choose
>
> Does reset1 enable the counter, disable it, or no change?
Reset1 sets the counter to zero, as explained.
It does not "enable" it, for this we have reset2
>
> What are the timing constraints?
No constraints.
>
> How does it reach 0 if counting up?
After 15 comes zero
>
> Are you resets synchronous or asynchronous?
Don't care, whatever is more simple
>
> Which clock edge do you wish to count on?
Don't care
>
> What are the outputs?
The value of the counter
>
> Cheers,
> Jon
>
>



Article: 121818
Subject: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
From: austin <austin@xilinx.com>
Date: Fri, 13 Jul 2007 07:23:35 -0700
Links: << >>  << T >>  << A >>
Craig,

I must apologize, because I am an IC designer, not really a FPGA user (I
mostly use very simple and straightforward designs to verify the blocks,
and rely on others to write the systems level stuff).

I am also not a software expert.

There are Xilinx employees who read this newsgroup from our software
group, however.

If they do not respond, I am going to have to assume we can not do what
you ask with our tools.

Austin

Craig Moore wrote:
> Sorry I'm trying to be very practical here. I just want to know what
> command line tools I can use to create a verilog file from a schematic
> file.
> 
> How do I do that from the command line using either ISE 9.1i or
> ModelSim?
> 
> I'd appreciate it if you could give me an example?
> 
> Lets say my schematic is named: circuit.sch
> 
> I'd like to create a verilog file (netlist) that is equivilent to it,
> say: circuit.v
> 
> I'm guessing at the command line it would be something like:
> 
> xst -sch circuit.sch > circuit.v
> 
> I have read through all the user manuals, developer manuals, etc... I
> can't not figure out how to do this outside of the GUI interface.
> 
> Thanks again for any help you can provide.
> 
> Thanks,
> Craig.
> 

Article: 121819
Subject: Re: Designing the right clock tree for a multi-FPGA setup
From: austin <austin@xilinx.com>
Date: Fri, 13 Jul 2007 07:25:07 -0700
Links: << >>  << T >>  << A >>
Gero,

OK, then I am correct, you not only need a good system synchronous clock
to each FPGA, but you also must use clock forwarding to send/receive
data between devices.

Austin

Geronimo Stempovski wrote:
> Okay, let's be more precise: The clock frequencies I'd like to distribute 
> are in the range of 180 - 300 MHz, i.e. it is a challenging task. The signal 
> busses between the FPGAs should carry signals in that range, too. Data is 
> exchanged synchronously, so there is not much room for synchronization I 
> think...!?
> 
> Gero 
> 
> 

Article: 121820
Subject: Re: highly-parallel highspeed connection between two FPGA boards
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Fri, 13 Jul 2007 16:33:32 +0200
Links: << >>  << T >>  << A >>

"Maurice Branson" <traubenuss@arcor.de> wrote
>
> Oay, to make it more precise: I'm looking for an interconnect system 
> (multi-channel plug + receptacle) for 24 differential pairs at signaling 
> rates of 3 - 6 Gbps per channel.

I don't know if you have already looked at them, but for things like that, I 
use Samtec connectors and cables.
http://samtec.com/high_speed_connectors/2006/si_b2b.asp
http://samtec.com/high_speed_connectors/2006/SI_C2B.asp?m=hs

Marc



Article: 121821
Subject: Re: Designing the right clock tree for a multi-FPGA setup
From: "Geronimo Stempovski" <geronimo.stempovski@arcor.de>
Date: Fri, 13 Jul 2007 16:34:52 +0200
Links: << >>  << T >>  << A >>
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag 
news:f7805h$1sk$1@aioe.org...
>>
> You might also consider source synchronous busses to get data between 
> FPGAs in addition to the star topology.
>>

Sounds interesting. What do you mean by that? Could you please go a little 
bit more into details? I heard about "source synchronous busses" a while ago 
but unfortunately I don't know what it is... sorry!

Thanks.

Gero 



Article: 121822
Subject: Re: Atmel FPSLIC users out there?
From: Robert Spanton <rspanton@gmail.com>
Date: Fri, 13 Jul 2007 14:38:35 -0000
Links: << >>  << T >>  << A >>
On May 28, 4:43 pm, Adam Megacz <meg...@cs.berkeley.edu> wrote:
> Right now I'm working on getting Icarus' synthesis to feed my PAR tool
> for the FPSLIC.

Does abits do PAR - your website doesn't say.

Cheers,

Rob



Article: 121823
Subject: Re: Designing the right clock tree for a multi-FPGA setup
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 13 Jul 2007 15:43:53 +0100
Links: << >>  << T >>  << A >>
"Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message 
news:46978d8c$0$20999$9b4e6d93@newsspool1.arcor-online.net...
> "Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag 
> news:f7805h$1sk$1@aioe.org...
>>>
>> You might also consider source synchronous busses to get data between 
>> FPGAs in addition to the star topology.
>>>
>
> Sounds interesting. What do you mean by that? Could you please go a little 
> bit more into details? I heard about "source synchronous busses" a while 
> ago but unfortunately I don't know what it is... sorry!
>
> Thanks.
>
> Gero
Hi Gero,
The source of the data provides a clock along with the data. You should be 
able to find stuff on the FPGA manufacturers websites to help you along...
HTH, Syms. 



Article: 121824
Subject: Re: Designing the right clock tree for a multi-FPGA setup
From: "Geronimo Stempovski" <geronimo.stempovski@arcor.de>
Date: Fri, 13 Jul 2007 16:43:56 +0200
Links: << >>  << T >>  << A >>
"austin" <austin@xilinx.com> schrieb im Newsbeitrag 
news:f78203$f1e2@cnn.xilinx.com...
> Gero,
>
> OK, then I am correct, you not only need a good system synchronous clock
> to each FPGA, but you also must use clock forwarding to send/receive
> data between devices.
>

I'm sorry, Austin! I am not so familiar with the topic. What do you mean by 
"system synchronous clock"? Isn't that just the description for "identical 
clock to every FPGA" or am I wrong? And how should clock forwarding be done? 
If the data arrives at every FPGA with its own clock, but the FPGA is 
clocked by another skewed (or even jittered) clock, how can synchronization 
be achieved, anyway? I appreciate your comment. Thanks in advance.

Gero 





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