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I had the same problem when trying to use the Xilinx USB cable drivers in Ubuntu Linux. I solved the problem by installing new cable drivers. See my blog http://svenand.blogdrive.com/archive/55.html for more information. SvenArticle: 122476
"colin" <colin_toogood@yahoo.com> wrote in message news:1185552810.842102.166100@k79g2000hse.googlegroups.com... >I read this thread with great interest and have a very closely related > question. > > As of May 07 Altera recommend putting their pll gnd pins in a split > plane. The arguments in this thread make a lot of sense for seperate > analog circuits being on the same plane because one can physically > seperate them, but how about pll gnds which are 3mm (3 balls) away > from a standard GND pin. > > Any advice appreciated as this will end an argument in our office. > > Colin > Hi Colin, Do you have a link to Altera's recommendation? A picture of what they're suggesting would be nice. Anyway, without having read TFA, I'll spout on regardless! For there to be noise injected into the supply of the PLL, it would need to have noise current from the digital stuff or whatever passing through the ground plane between where the PLL ground via(s) attach(es) and where the PLL supply bypass capactitor ground via(s) attach(es). Clearly the smaller this distance the less voltage is induced in the PLL supply. Bear in mind that ground planes have very low impedance. Now, if the separation between the bypass caps and the PLL ground vias is a lot, there might be a problem. However, I'm a skeptic until someone prove otherwise. I bet the noise on the supplies is a lot bigger problem than noise on a ground plane. (I bet they say to use LDO regs on the supplies, even though the B/W of such regs. are a best a few hundred kHz. A passive filter is much better!) HTH., Syms. p.s. What's the deal on your office argument? Can you post the opinions?Article: 122477
On Jul 27, 7:17 pm, jjohn...@cs.ucf.edu wrote: > Thanks everyone, this is real interesting, but please don't stop > posting if you have more insights to share! > > I originally suspected P&R might have a lot of floating-point > calculations (even prior to signal-integrity considerations) if they > were doing any kind of physical synthesis (e.g., delay calculation > based on distance and fanout); ditto for STA, because that's usually > an integral part of the P&R loops. I also suspected that if floating- > point operations (at least multiplies, add/subtract, and MACs) could > be done in a single cycle, there would be no advantage to using > integer arithmetic instead (especially if manual, or somewhat explicit > integer scaling is required). > > On the other hand, in something like a router, you can get more exact > location info wrt stuff like grid coordinates than you can with > floating-point. As far as dynamic range is concerned, I seem to recall > that SystemC standardized on 64-bit time to run longer simulations, > but SystemC is a different animal in that regard anyway. Nonetheless, > I also seem to recall that its implementation of time was 64-bit > integers (scaled), because the average FPU operations are really only > linear over the 53-bit mantissa part. Assuming they want linear > representation of time ticks, I can see the appeal of using 64-bit > integers in simulation. Any operations on large netlists are completely memory and pointer dominated. There are lot's of random access pointer indirections in data sets that are much larger than the cache. The computations done once you have the data do not matter at all. You need hundreds of CPU cycles to access the delay parameters of two gates in a netlist. Summing them up can be done for free while the CPU waits on the next load instruction. On the other hand, if your dynamic range is needed for summing up small values floating point does not help at all. 1e12 + 1 = 1e12 in 32-bit floating point. For opperations like that 32- bit integer actually has 6 bits more dynamic range. > As far as event-driven simulations are concerned, I totally understand > how hard it is to make good use of multithreading or multiprocessing, Why? In a larger design there will allways be many active processes at each timestep. These can be distributed to individual processors. All operations can be on shared memory because each signal has only one driver. Kolja SulimmaArticle: 122478
I used the verilog language template to create a dual port RAM. The initial size that I selected was 64 words x 32 bits. It synthesises OK and the synthesis report says that I have 64x32. I added a reset pin. All synthesises OK. I thought that I only need 18 to 32 registers. So I changed the address size from 6 to 5. I get no change of the dual port ram size. I changed the data word width from 32 bits to 64 bits. I get no change of ram size. Can I actually create a small dual port ram such as 18 words of 32 bits or have I missed some synthesis command. It looks to be more like the software is not actually processing the changed source code. I'm use ISE 9.1. All help gratefully recieved. AndyArticle: 122479
Patrick Dubois wrote: > On Jul 26, 6:19 pm, jjohn...@cs.ucf.edu wrote: >> AMD or Intel? >> ------------------- >> Between AMD & Intel's latest multicore CPUs, >> - Which offers the best integer performance? >> - Which offers the best floating-point performance? >> Specific models within the AMD/Intel family? >> >> Assume cost is no object, and each uses its highest-performing memory >> interface, but disk access is (necessary evil) over a networked drive. >> (Small % of total runtime anyway.) >> >> Multi-core, multi-processor, or both? 32-bit or 64-bit? Linux vs. >> Windows? >2GB of RAM? > > If cost is no object, then go with the Intel quad-core running at 3 > GHz : QX6850. Each core has 2 MB of L2 cache (8MB total), which is, > according to several reports in this forum, the single most important > factor. > > I would say go with 4GB of ram, although if you're using the biggest > chips, you might need more. Keep in mind that Windows 32-bit will only > be able to use 3GB max of this 4 GB, and each application will only be > able to access 2GB max. So you might consider Windows 64 bits or Linux > 64 bits if necessary. > > Patrick > The last time I checked the speed of a full FPGA build, the cache did indeed have the single largest effect, which is hardly surprising. A cache access is typically one internal bus cycle (not a cpu cycle) which is an order of magnitude faster than an external memory access cycle. Properly optimised code that uses the I-Cache properly will run much faster than inline code, incidentally. Cheers PeteSArticle: 122480
"Andy Botterill" <andy@plymouth2.demon.co.uk> wrote in message news:46ab58a9$0$642$bed64819@news.gradwell.net... >I used the verilog language template to create a dual port RAM. The initial >size that I selected was 64 words x 32 bits. It synthesises OK and the >synthesis report says that I have 64x32. > What sort of dual port ram are you trying to infer? Distributed or block? > > I added a reset pin. All synthesises OK. > What does this reset pin meant to do? Distributed RAM doesn't play with reset, the block memory has a reset which only resets the output registers. Cheers, Syms.Article: 122481
Symon wrote: > "Andy Botterill" <andy@plymouth2.demon.co.uk> wrote in message > news:46ab58a9$0$642$bed64819@news.gradwell.net... > >>I used the verilog language template to create a dual port RAM. The initial >>size that I selected was 64 words x 32 bits. It synthesises OK and the >>synthesis report says that I have 64x32. >> > > What sort of dual port ram are you trying to infer? Distributed or block? Block ram. I used the 2 clock 2 read/write port template. > >>I added a reset pin. All synthesises OK. >> > > What does this reset pin meant to do? Distributed RAM doesn't play with > reset, the block memory has a reset which only resets the output registers. Ah. I was intending to use the dual port ram as a register file. The register file needs 3 registers (out of 18-20) initialising at reset. Is there any way to do this using any of the dual/single port RAM's? I was tring to compare a register based register file with a dual port ram based register file. Looks like it may not be possible. > > Cheers, Syms. > >Article: 122482
On Sat, 28 Jul 2007 18:02:28 +0100, Andy Botterill <andy@plymouth2.demon.co.uk> wrote: >Ah. I was intending to use the dual port ram as a register file. The >register file needs 3 registers (out of 18-20) initialising at reset. Is >there any way to do this using any of the dual/single port RAM's? See below - in FPGAs, yes. In other technologies, no. For this problem on this scale, the technique I usually use is to build the DPRAM in the ordinary way, and then to build a regular collection of flip-flops with one FF per RAM location. These FFs are reset to 0 at power-up, and are changed to 1 whenever the corresponding RAM location is written - an easy thing to arrange. The trick, of course, is that when you READ one of the RAM locations you first check the "have I been written" register - and, if it's zero, then you substitute the desired power-up reset value in place of the RAM contents. HOWEVER, you *can* initialise the contents of any Xilinx RAM at configuration (I think - betcha there are some exceptions I don't know about). Trawl the docs for "memory initialization file" or somesuch. Plenty of people here will have that information at their fingertips; I don't. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 122483
How do I check this?Article: 122484
On 28 Jul., 00:56, jon...@gmail.com wrote: > Hi, > I am having trouble configuring a xc3s250e from a st m25pe20 spi > flash rom. Originally init would not go low and the chip was > constantly looping through the config. I inserted a 256 0xFF's at the > beginning of the mcs file and now init goes low, but done does not go > high. Is there some number of 0's or 1's that need to be appended to > the image. I am using xilinx ise 9.1. I generated the mcs file using > impact and selected the generic SPI options. I have tried bit-swapping > the file. Init only goes low one way. The last line of my prom image > is: > > :1094F00020000000200000002000000020000000EC > > I have heard of a postamble that should be 0x7F, this file doesn't > have one though. > > Thanks, > > Jon Pry init going low during means ERROR init not going low, done not asserting means that configuration not even started init is low for short time after power-on, if it doesnt go high means FPGA is really not in working condition (INIT=1 means its ready for conf) AnttiArticle: 122485
Hi! I recently installed EDK 9,1.02i. When I synthesize a project I get thousand of warnings, which is really annoying: WARNING: vhdl is not supported as a language. Using usenglish. Reading the real information becomes almost impossible. What can I do to circumvent this? Thanks! MatthiasArticle: 122486
Jonathan Bromley wrote: > On Sat, 28 Jul 2007 18:02:28 +0100, Andy Botterill > <andy@plymouth2.demon.co.uk> wrote: > > >>Ah. I was intending to use the dual port ram as a register file. The >>register file needs 3 registers (out of 18-20) initialising at reset. Is >>there any way to do this using any of the dual/single port RAM's? > > > See below - in FPGAs, yes. In other technologies, no. > For this problem on this scale, the technique I usually > use is to build the DPRAM in the ordinary way, and then to build a > regular collection of flip-flops with one FF per RAM location. > These FFs are reset to 0 at power-up, and are changed to 1 > whenever the corresponding RAM location is written - an easy > thing to arrange. The trick, of course, is that when you READ > one of the RAM locations you first check the "have I been > written" register - and, if it's zero, then you substitute > the desired power-up reset value in place of the RAM contents. Only three registers need a reset change of state. That will simplify the code. I'll give it a try and get back to you. > > HOWEVER, you *can* initialise the contents of any Xilinx > RAM at configuration (I think - betcha there are some > exceptions I don't know about). Trawl the docs for "memory > initialization file" or somesuch. Plenty of people here will > have that information at their fingertips; I don't. Hopefully I won't have to use this method. Thanks for everyones help.Article: 122487
Andy, If you like to use the BRAM, it may be loaded with whatever you please by using a software tool to take a hex file, and place it into the bitstream (effectively makes the RAM a ROM). Since the BRAM is loaded from the bitstream, the default, or initial condition is all zeroes. This is also true of LUTRAM (it is all 0's to start with, because that is what is in the bitstream). There is a way to specify LUT contents for the bitstream, but I don't have that handy (net connection at home is slow to download 6 Mb user guides!). AustinArticle: 122488
jjohnson@cs.ucf.edu wrote: > That appears to be related to the number of processors inside one box. > If a single CPU is just hyperthreaded, the processor takes care of > instruction distribution unrelated to a variable like number_of_cpus, > right? No. Hyperthreading means that the hardware is only virtually doubled. The CPU maintains the state and the register set of two independent threads and tries to utilize all its function units. If one thread has to wait for data from the memory some instructions of the other thread can be issued to the function units. Likewise, if one thread spends its time in the FPU, the other thread can use the remaining function units. If both threads execute the same type of instructions a hyperthreaded CPU rarely has an advantage. Running on a hyperthreaded CPU the operating system sees two cores and has to schedule its workload like there were two physical cores to gain any benefit. If your software only has one thread hyperthreading like multicores won't speed it up. > And if there are two single-core processors in a box, obviously > it will utilize "number_of_cpus=2" as expected. Does anyone know how > that works with dual-core CPUs? i.e, if I have two quad-core CPUs in > one box, will setting "number_of_cpus=7" make optimal use of 7 cores > while leaving me one to work in a shell or window? I don't know how Quartus makes use of the available CPUs but basically as seen from software there is no difference between two single cores and one dual-core. > In 32-bit Windows, is that 3GB limit for everything running at one > time? i.e., is 4GB a waste on a Windows machine? Can it run multiple > 2GB processes and go beyond 3 or 4GB? Or is 3GB an absolute O/S limit, > and 2GB an absolute process limit in Windows? 3 GB is a practical limit because the PCI bus and other memory-mapped devices typically occupy some hundred megabytes of address space. So you can't use this memory space to access RAM. There are techniques to map memory to other address regions beyond the 4 GB border but you need special chipsets and proper operating system support. AndreasArticle: 122489
On 2007-07-28, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: > HOWEVER, you *can* initialise the contents of any Xilinx > RAM at configuration But then you can't just 'reset' your design. You have to reconfigure from the bitstream to truly reset. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 122490
I'm working with a custom verilog core that accepts a small number of parameters, and I'm having a hard time pushing them through XST properly under EDK 8.1. For example, I include the following line in my .mpd file: PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10, MIN_SIZE=2, BUS=SDCR But XST happily reports: C_DCR_BASEADDR = 32'b00000000000000000000000001000000 Does anybody know how to ensure that my C_DCR_BASEADDR parameter is not initialized to something wider than 10 bits?Article: 122491
On Jul 28, 12:31 pm, Antti <Antti.Luk...@googlemail.com> wrote: > On 28 Jul., 00:56, jon...@gmail.com wrote: > > > > > Hi, > > I am having trouble configuring a xc3s250e from a st m25pe20 spi > > flash rom. Originally init would not go low and the chip was > > constantly looping through the config. I inserted a 256 0xFF's at the > > beginning of the mcs file and now init goes low, but done does not go > > high. Is there some number of 0's or 1's that need to be appended to > > the image. I am using xilinx ise 9.1. I generated the mcs file using > > impact and selected the generic SPI options. I have tried bit-swapping > > the file. Init only goes low one way. The last line of my prom image > > is: > > > :1094F00020000000200000002000000020000000EC > > > I have heard of a postamble that should be 0x7F, this file doesn't > > have one though. > > > Thanks, > > > Jon Pry > > init going low during means ERROR > init not going low, done not asserting means that configuration not > even started > > init is low for short time after power-on, if it doesnt go high means > FPGA > is really not in working condition (INIT=1 means its ready for conf) > > Antti Init pulses high. I can see that the fpga has downloaded the configuration and stops downloading it presumably when the correct number of bytes have been transferred. I'm pretty sure it is in the "ERROR" condition. I don't know why though.Article: 122492
RAMs do not have a parallel reset for a very simple reason: It would be very expensive, adding a gate to each cell, plus routing the reset input all over the RAM area. Over the past 50 or more years, designers have learned to live with the fact that you cannot just instantly reset the whole RAM. And life goes on... Peter Alfke ========================= On Jul 28, 5:06 pm, Ben Jackson <b...@ben.com> wrote: > On 2007-07-28, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > > > HOWEVER, you *can* initialise the contents of any Xilinx > > RAM at configuration > > But then you can't just 'reset' your design. You have to reconfigure > from the bitstream to truly reset. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/Article: 122493
hi I wonder how come is xilinx website at least partially broken whenever I need something? today as example Spartan3 page is JUST EMPTY page? It is not possible to belive that a real webmaster would be able to produce such a mess so often, or is it possible? hmm.. or maybe it is preparation to launch Spartan-4 ? ;) Antti micro-SD adapter for digilent/xilinx boards: http://docs.google.com/View?docID=ddn2thkw_27fwvkvhArticle: 122494
On 29 Jul., 02:52, jon...@gmail.com wrote: > On Jul 28, 12:31 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > On 28 Jul., 00:56, jon...@gmail.com wrote: > > > > Hi, > > > I am having trouble configuring a xc3s250e from a st m25pe20 spi > > > flash rom. Originally init would not go low and the chip was > > > constantly looping through the config. I inserted a 256 0xFF's at the > > > beginning of the mcs file and now init goes low, but done does not go > > > high. Is there some number of 0's or 1's that need to be appended to > > > the image. I am using xilinx ise 9.1. I generated the mcs file using > > > impact and selected the generic SPI options. I have tried bit-swapping > > > the file. Init only goes low one way. The last line of my prom image > > > is: > > > > :1094F00020000000200000002000000020000000EC > > > > I have heard of a postamble that should be 0x7F, this file doesn't > > > have one though. > > > > Thanks, > > > > Jon Pry > > > init going low during means ERROR > > init not going low, done not asserting means that configuration not > > even started > > > init is low for short time after power-on, if it doesnt go high means > > FPGA > > is really not in working condition (INIT=1 means its ready for conf) > > > Antti > > Init pulses high. I can see that the fpga has downloaded the > configuration and stops downloading it presumably when the correct > number of bytes have been transferred. I'm pretty sure it is in the > "ERROR" condition. I don't know why though.- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - connect JTAG cable at least temporarly and read back the status register, it should hold the error bits hopefully init low error is either CRC or wrong device ID AnttiArticle: 122495
On 28 Jul., 21:55, charon <mega_me...@gmx.de> wrote: > Hi! > > I recently installed EDK 9,1.02i. When I synthesize a project I get > thousand of warnings, which is really annoying: > > WARNING: vhdl is not supported as a language. Using usenglish. > > Reading the real information becomes almost impossible. What can I do > to circumvent this? > > Thanks! > Matthias this is hilarious - is your mother tonque really VHDL ? it looks like ISE wants you to use US English instead of VHDL? maybe you speak oxford english, and that upsets it.. sorry, no idea whats wrong, but its just another example of how xilinx understand "software testing..." (lets leave it to our customers...) AnttiArticle: 122496
Peter Alfke wrote: > RAMs do not have a parallel reset for a very simple reason: It would > be very expensive, adding a gate to each cell, plus routing the reset > input all over the RAM area. > Over the past 50 or more years, designers have learned to live with > the fact that you cannot just instantly reset the whole RAM. And life > goes on... I agree with you. I am trying to design a register file as an exercise in design. I have 3 different concepts. Two of the concepts are using traditional registers and the third is using a dual port ram. They all have to work as register files and have a reset operation which is consistent with each other and the original design. If I cannot reset the register file when using a dual port ram then I've done the wrong thing. Andy > Peter Alfke > ========================= > On Jul 28, 5:06 pm, Ben Jackson <b...@ben.com> wrote: > >>On 2007-07-28, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: >> >> >>>HOWEVER, you *can* initialise the contents of any Xilinx >>>RAM at configuration >> >>But then you can't just 'reset' your design. You have to reconfigure >>from the bitstream to truly reset. >> >>-- >>Ben Jackson AD7GD >><b...@ben.com>http://www.ben.com/ > > >Article: 122497
On Sat, 28 Jul 2007 19:06:06 -0500, Ben Jackson <ben@ben.com> wrote: >On 2007-07-28, Jonathan Bromley wrote: >> HOWEVER, you *can* initialise the contents of any Xilinx >> RAM at configuration > > But then you can't just 'reset' your design. You have to > reconfigure from the bitstream to truly reset. Yes. But the solution I offered - one "I have been written" register bit per RAM location - doesn't scale well; it's fine for up to a few dozen locations, no more. If you can arrange that the RAM locations whose initial value matters to you are all in a small piece of address space, you can easily modify the "I have been written" trick so that it applies only to the small part of the memory that has the initialisation requirement. More generally, it is not unreasonable to consider modifying your system's control state machine so that its first action after reset is to scribble the initialisation values into RAM, maybe by block-copy out of another memory configured as ROM with the reset values in it. As Peter said, it's not practical to reset a big memory, and people have lived with this for ever. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 122498
Well, my mother tongue is "de_DE.UTF-8@euro", at least this is what $LANGUAGE is set to. I get warnings in all Xilinx tools because of that. The problem is that the EDK generates a Makefile that sets LANGUAGE to vhdl. The other tools seem to rely on this. When I modify it and set the LANGUAGE to an empty string I don't get these warnings anymore. When I do not touch LANGUAGE I get thousands of warnings with de_DE.UTF-8@euro not supported. BTW the Makefile says it is generated each time so it makes no sense to edit it. So this really isn't a solution. Even if I would set my $LANGUAGE to usenglish the Makefile would override it with vhdl..... If the language in the project preferences is set to verilog it is the same. Arfff... Matthias On 29 Jul., 09:08, Antti <Antti.Luk...@googlemail.com> wrote: > On 28 Jul., 21:55, charon <mega_me...@gmx.de> wrote: > > > Hi! > > > I recently installed EDK 9,1.02i. When I synthesize a project I get > > thousand of warnings, which is really annoying: > > > WARNING: vhdl is not supported as a language. Using usenglish. > > > Reading the real information becomes almost impossible. What can I do > > to circumvent this? > > > Thanks! > > Matthias > > this is hilarious - is your mother tonque really VHDL ? > it looks like ISE wants you to use US English instead of VHDL? > maybe you speak oxford english, and that upsets it.. > > sorry, no idea whats wrong, but its just another example of how xilinx > understand > "software testing..." (lets leave it to our customers...) > > AnttiArticle: 122499
On Jul 28, 10:51 pm, Andreas Hofmann <ahn...@gmx.net> wrote: > 3 GB is a practical limit because the PCI bus and other memory-mapped > devices typically occupy some hundred megabytes of address space. So you > can't use this memory space to access RAM. These are usually not mapped into the address space of a user process. Kolja Sulimma
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