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Messages from 12375

Article: 12375
Subject: Re: Xilinx F1.5/FPGA Express wackiness
From: Nick Hartl <"nhartl[no_spam]"@earthlink.net>
Date: Sat, 10 Oct 1998 11:44:37 -0500
Links: << >>  << T >>  << A >>


Andy Peters wrote:

> Hey, all:
>
> I've been futzing with F1.5 and FPGA Express for about a week now...here's
> some observations:
>
> 1) Supposedly there's a way to keep revs of source code with implementation
> revs but I can't figure out how to do it.

There is a way to do rev control how ever to the best of my knowlegde it is
only availible in Design Manager.  In DM by selecting the project icon then
doing a DESIGN>Properties> one can get to the menu that allows source file
coping with the version.

The other thing mentioned below?  I donno.  Something else to look at.....
Have FUN
Nick

>
>
> 2) In Synthesis Options for FPGA Express, when I checked the box labelled
> "Export Timing Constraint," I got SIXTY-TWO timespecs, ranging from the
> sublime (pads to pads) to the ridiculous (output tristate flipflops to
> output tristate flipflops????).
>
> 3) After synthesizing, click on the implementation button and then choose
> "Options" for physical implementation settings.  It won't let you choose a
> Simulation Program Template other than Foundation EDIF.  Even if you select
> Generic VHDL or ModelSim VHDL, once you start the implementation it throws
> your choice away and chooses Foundation EDIF.
>
> 4) The could-be-nifty Constraints Editor GUI (not accessible from the
> Project Manager; rather it's buried in the program manager/start menu under
> Programs->Xilinx->Accessories->Constraints Editor) requires as input both a
> .UCF AND a .NGD file.  Unfortunately, the .NGD file isn't available until
> after you do an implementation.
>
> 5) Something got into my .UCF file and changed my timing ignore for
> bidirectional data bus pins
>     TIMESPEC "TS_FALSE" = FROM "FFS" THRU "ramthru" TO "FFS"  TIG;
>
> to
>
>     TIMESPEC "TS_FALSE" = FROM "FFS"  TO "FFS"  TIG;
>
> which had the amusing-yet-useless effect of cause all timing constraints to
> be ignored by PPR.
>
> -andy
>
> --------------------------------------------------------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520-318-8191
> apeters@noao.edu
> "Stupidity is like hydrogen: it's universal.  It's everywhere and in
> everything."
>     -- Frank Zappa



Article: 12376
Subject: Re: Xilinx may not support schematics for Virtex?????
From: "Austin Franklin" <darkroo3m@ix.netcom.com>
Date: 10 Oct 1998 17:01:21 GMT
Links: << >>  << T >>  << A >>
> I don't think you understand what happens when you want to simulate in a
> VHDL simulator. The schematic must be converted to VHDL since that is
> the only format the simulator understands. You also might not be
> familiar with structural VHDL. This is equivalent to a netlist. So it is
> just another form of the schematic. There is no synthesis involved so
> the compilier can't mess up what you have written. 

I am very familiar with VHDL.  I don't see how this ties into my concerns
with simulation....  You may be right, it may 'just' work, but somehow I
doubt that, as it hasn't been the case in the past.

> It sounds to me like you have tried VHDL and had VHDL shock. I am very
> familiar with that having just learned VHDL within this past year.
> However I found VHDL to be a good tool which may make some tasks a
> little harder, at least until you learn how to do them in a different
> way, but it makes many tasks easier. 

As I said, I know VHDL...  I didn't want this to turn into a VHDL v
schematics.  I agree VHDL is a good and useful tool in some instances.  I
also need and require schematics.
 
> If you need so much control over your design that you think in terms of
> FMAPs at all times, then you likely would not find VHDL useful. But I
> have found that the 90/10 rule applies to hardware just as it does to
> software. 90% of your design will work just fine with auto place and
> route, even in a fast design. The other 10% can be tweeked by hand, even
> using VHDL. 

For my designs, your above is absolutely incorrect.  Every design I do runs
at 33+ MHz, and as such, requires a lot of mapping and placement.  ALSO,
yes, I can buy the FASTEST MOST EXPENSIVE parts and use VHDL and hope and
pray it works...OR I can use schematics, and ASSURE my design success in a
finite amount of time, with cheaper silicone.

That's the truth of the matter, and I KNOW Ray and Philip will back me up
on this one.  We all are consultants, and find a large part of the work we
do is 'fixing' things for clients who have embarked on the panaceic VHDL
journey, only to be sadly disappointed and aggravated by the results.  In
fact, I know Xilinx has lost a lot of major design wins because of this
exact problem.

I either spend a lot of time instantiating things, and doing placement...OR
convert it to schematics..and it magically works...AND they find their part
cost is FAR less as they can use slower AND smaller parts!  Funny enough,
the savings they have by doing schematics almost always pays for my time,
and to boot, it even works when I'm done....
 
> I may be a little biased towards VHDL since it is a programming language
> and I have some background as a programmer. But I can tell that as my
> designs get larger I will no longer have the option of drawing
> schematics to record my design. I will be forced to use VHDL in order to
> get increased productivity. 

I actually have a very extensive programming background in C and assembly
from both the applications level to the O/S level.  I am not afraid of
programming.  I am afraid of not being able to do designs successfully and
within a known time frame.

> The one big point that got me to try my first VHDL project was testbench
> capability. A testbench is a VHDL program which allows you to create a
> "virtual environment" to test your design. It is much more than a batch
> file. It has the capability to interactively stimulate the design and
> verify results. It is also portable across different vendors. 
> 
> I don't think I will do another design of any real size again without
> VHDL. 

Interesting, and with all the VHDL experience I have, I wouldn't do another
design for an FPGA using it as the primary tool, at least if I required
high speed and low density.  I do use schematics for data path and some HDL
for control logic, and usually end up converting most of the control logic
from VHDL to gates to make timing....

Let's do an economic reasoning here...

Say a design fits in a $40 part with VHDL and a $24 part with schematics. 
And, some actually believe it's faster to do a design in VHDL, and it may
be for some slower designs....but my experience has been very different, as
you end up spending a lot of time fussing with the VHDL to make timing
etc.... so let's say they both take the same amount of time to
implement....so that's a wash.  If you have a build of 1000 boards, at an
additional cost of $16, per board, that's $16,000.

VHDL for FPGAs is going to suffer the same problem Windows applications
have with faster computers and cheaper storage...these features will mask
bloated and slow designs.

Austin

P.S.  I don't know about you, but I find it really hard to look at a stack
of textual pages and know at a glance what the data flow and functionality
of a design is....  May be I need to take that speed reading course again
;-)



Article: 12377
Subject: Re: Xilinx may not support schematics for Virtex?????
From: Nick Hartl <"nhartl[no_spam]"@earthlink.net>
Date: Sat, 10 Oct 1998 12:07:35 -0500
Links: << >>  << T >>  << A >>
Well now I do see Virtex library symbols in the Foundation Schematic Editor and
have placed a Virtex chip using Foundation schematics only (No HDL).  So where
is this no schematic support?

I did here that at this time there is some question if ViewLogic will support
Virtex in schematics.  I am not sure if this is a decision made by Veiw or by
Xilinx.

Have FUN!!!
Nick

Donald Espinoza wrote:

> It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic
> entry for Virtex (or any other schematic entry tool for that matter).
> SOMEhow, SOMEone, interviewed SOME people, and these people were apparently
> taken by the Xilinx decision making tree as the 'golden' cross section of
> 'important' users.  These SOME people said they did not want schematics,
> that HDLs would do fine.
>
> Now, nothing against HDLs, as I do use them, and they are fine...BUT there
> are some things just done better in schematics.  Let's not get into that
> subject, as we all have bantered this issue of schematics v HDLs about, but
> for Xilinx to dictate what my design methodology is to be is not OK.
> Personally, I think this, what I would call, a quite 'uneducated' decision,
> is a very bad decision....
>
> ANYone else know ANYthing more about this?
>
> Austin Franklin
> darkroom@ix.netcom.com



Article: 12378
Subject: Re: Xilinx F1.5/FPGA Express wackiness
From: mushh@jps.net (David Decker)
Date: Sat, 10 Oct 1998 17:18:39 GMT
Links: << >>  << T >>  << A >>
I'm not familiar with 5200, but with the 4000 series I think M1.x is
more willing to spread the design out into more CLBs, to possibility
use more redundant Logic and CLBs as pass thorughs, than was Xact 6. I
think M1.x just tries to fill the chip up to 96% CLBs, with anything
that will make it easier to meet timing.

Also, with respect to the design that works under Xact6, but gets
constraints conflicts under M1. . .  I had an M1 problem that I
reduced to a test case. I didn't try Xact6, but I'm sure it would have
had no trouble. M1.5 died with constraints conflicts.

I simply placed three 4000e unified cc16cled counters into adjacent
columns, using RLOCs. Each counter had the 'UP' line tied low. 

These counters are RLOCed, by Xilinx, into two columns of 9 CLBs each,
but the 'UP' line grounded should have resulted in the 'UP' column
being stripped. If the 'UP' logic were properly stripped, the counters
should have been able to be placed into adjacent columns. 

When I copied the schematic of the counter and manually stripped the
'UP' stuff, of course, the three resulting down only counters placed
into adjacent columns OK. My working hypothesis is that the M1
stripper does not strip 4000 series carry chains properly. I wonder if
5200s have the same symptom.


Jeff Graham <drjeff@actrix.gen.nz> wrote:

>I haven't had the Foundation updates yet, but the Alliance updates came
>through this week, and I wasn't totally unsuprised to find that M1.5 is
>just as appallingly bad at placing/routing 5200 series parts as M1.4
>was.
>- 5204 design with 65% utilisation when built with XACT6,  96%
>utilisation in M1.5 and "unable to place design due to constraints
>conflict"
>
>Ah well, look like I'm stuck with XACT6 for another year ...
>
>
>Jeff Graham
>Hardware Team Leader
>MAS Division
>Digital Microwave Corp
>Lower Hutt, New Zealand

Dave Decker

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House
Article: 12379
Subject: Re: clock divider chips
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 10 Oct 1998 10:24:33 -0700
Links: << >>  << T >>  << A >>
"Thomas Dölle" <doelle@fb.sony.de> writes:

> Hi,
> 
> I'm looking for high speed (up to 80 MHz input) clock divider chips with
> 
> programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and
> CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven
> by a external clock source. Does anybody know whether there are chips
> commercially available?
> 
> Thomas
> 
> 
> 
> 
> 
> 

Try www.microclock.com

good luck!

-Arrigo

-- 
Arrigo Benedetti          o         e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	 < >			phone: (626) 395-3695
Pasadena, CA 91125	 / \			fax:   (626) 795-8649
Article: 12380
Subject: Xilinix Foundation Install?
From: Leyton Collins <leyton.collins@sympatico.ca>
Date: Sat, 10 Oct 1998 17:52:19 GMT
Links: << >>  << T >>  << A >>
Hi everybody,

I just found out about this ng a few weeks ago and this is my first
post.

Anyway, I finally got around to installing my Foundation 1.3 package
on my home PC so I can do some O/T w/o having to go into work. The
problem is that even though I've registered w/ Xilinx, they sent me
the license.dat file, I put it in the directory path in my autoexec.bat
file, and when I try to compile the design it craps out w/ the error
that it can't find the license file! I've tried re-installing the pfg
3 times w/ still no luck.

Any suggestions (other than screaming and hitting the monitor ... didn't
work)?

Thanks,  Leyton
Article: 12381
Subject: Re: Xilinx may not support schematics for Virtex?????
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 10 Oct 1998 14:10:35 -0400
Links: << >>  << T >>  << A >>
> P.S.  I don't know about you, but I find it really hard to look at a stack
> of textual pages and know at a glance what the data flow and functionality
> of a design is....  May be I need to take that speed reading course again
> ;-)

probably the best point.  i have never used vhdl for a top level.  while
computers may be good at reading netlists, me, a humanoid, is not.  so i always
put together the upper level or road map in a schematic, with sub-blocks
designed as they make sense {vhdl, macro, schematics).  and i've jumped up and
down enough about keeping schematics, some vendors wanna get rid of them, like
chipx, who only support schematic for qyh500.  reading a huge textfile to get
the flow of a design? never.  can't even read documentation on-line, i just
print the whole thing out.  too old, i guess.

rk

p.s. extensive programming experience too [degree in it] so not afraid of text,
programming, etc.

Article: 12382
Subject: Re: Xilinx may not support schematics for Virtex?????
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 10 Oct 1998 14:13:56 -0400
Links: << >>  << T >>  << A >>
ditto.

100% go to hdl only.  NOT!

rk

msimon@tefbbs.com wrote:

> I vote for schematics.
>
> To Xilinx: Bad Move
>
> Simon
> ================================================================



Article: 12383
Subject: Re: Verilog Vs VHDL
From: Nick Hartl <"nhartl[no_spam]"@earthlink.net>
Date: Sat, 10 Oct 1998 13:18:04 -0500
Links: << >>  << T >>  << A >>
You are asking for a major chest pounding fest..... VHDL vs Verilog?  SOme people
take it real personal.  I don't

Me I do VHDL  it works..  Overly wordy?  Maybe but I like tight design control.

Have FUN
Nick

craig_jacobs@asl-tk.com wrote:

> Hello, I have been programming Altera FPGA's for several years using the
> altera HDL and graphic designs.  We are considering transferring new and some
> existing designs to either VHDL or Verilog.  I don't know anything about
> either language, and I would like a list of pro's and con's about each.
>
> Craig Jacobs
> Systems Engineer
> Advanced Product Development
> Automotive Systems Lab
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



Article: 12384
Subject: Re: Xilinx may not support schematics for Virtex?????
From: rk <stellare@NOSPAMerols.com>
Date: Sat, 10 Oct 1998 14:18:44 -0400
Links: << >>  << T >>  << A >>
ok, viewlogic, which i use, has an export1076 function which seems to work fine.  but
to do that, you need the symbols and simulation models so you can do your design in
the schematic and then simulate them.  i like simulating may desgins at the schematic
level, you run the simulator, can stop it, look at the schematic, the values are
sitting on those little lines for you to look at.

also,

say you goto vhdl [structural], what happens to your net names and reference
designators, labels, instance names or whatever you call it?  if you lose this, then
it may become much more difficult to talk to the other tools, like static timing
analyzers and device editors or floorplanners.  are these attributes preserved and
passed through unchanged?  or do we give up control?  can we guarantee that the vhdl
compiler won't decide that it's smarter than you and do some optimization which might
be bad for a particular application?  do we have to run around sticking in dont_touch
and preserve attributes on every <insert 'cuss word here' net?

just a few questions.,

rk

p.s. yeah, a geezer, still do a lot of schematics.

___________________________________

Rickman wrote:

> Isn't is possible to turn your schematic output into VHDL? I know that
> is how it is done in Orcad and that is what happens when you use
> Foundation with Active VHDL.
>
> If you can perform the schematic to VHDL translation, where does the
> non-support come in?
>



Article: 12385
Subject: Re: Verilog Vs VHDL
From: Nick Hartl <"nhartl[no_spam]"@earthlink.net>
Date: Sat, 10 Oct 1998 13:27:39 -0500
Links: << >>  << T >>  << A >>
You are asking for a major chest pounding fest..... VHDL vs Verilog?  SOme people
take it real personal.  I don't

Me I do VHDL  it works..  Overly wordy?  Maybe but I like tight design control.

Have FUN
Nick

craig_jacobs@asl-tk.com wrote:

> Hello, I have been programming Altera FPGA's for several years using the
> altera HDL and graphic designs.  We are considering transferring new and some
> existing designs to either VHDL or Verilog.  I don't know anything about
> either language, and I would like a list of pro's and con's about each.
>
> Craig Jacobs
> Systems Engineer
> Advanced Product Development
> Automotive Systems Lab
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



Article: 12386
Subject: Re: Help Desperately Needed with Altera Microprocessor Design.
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sat, 10 Oct 1998 14:51:26 -0400
Links: << >>  << T >>  << A >>
No, It's because Xilinx holds the patent on using CLB LUTs as RAM.  Xilinx's 'SRAM'
configuration cells are more akin to registers than SRAM (ie, the register bits are not 4
transistor SRAM cells).

James E. Stine wrote:

> Hi,
>
> This sound reasonable.  Do you know if this is because Xilinx uses SRAM based
> FPGA's and Altera uses floating-gate technology with small SRAM cells per
> CLB?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 12387
Subject: Schematic entry?
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 10 Oct 1998 21:00:58 +0200
Links: << >>  << T >>  << A >>

Color me stupid, but:

What exactly is schematic entry (as opposed to VHDL)?

Is it like it sounds, you draw a schematic with a couple of OR, AND
and NOT? Sounds tedious to me, but some people seem to prefer it to
VHDL.

Anyway, I have simple design in an ispLSI1032E (Lattice PLD). A couple
of statemachines and some counters. Add a PCI arbiter etc. Reasonable
enough in VHDL.

Would it be just as easy to do this with schematic entry and hand
placement? I would like to get some insight into "the other side of
the Force".

Thankfully,
Magnus Homann
-- 
   Magnus Homann  Email: d0asta@dtek.chalmers.se
                  URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
  The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 12388
Subject: Re: test
From: "Wallace V Rose" <COLOMBIA3@prodigy.net>
Date: Sat, 10 Oct 1998 14:25:28 -0500
Links: << >>  << T >>  << A >>

wwjj wrote in message <361D1460.49B5@mcmail.com>...
>testing
this is also a test.


Article: 12389
Subject: Re: test
From: "Wallace V Rose" <COLOMBIA3@prodigy.net>
Date: Sat, 10 Oct 1998 14:35:18 -0500
Links: << >>  << T >>  << A >>
test

Wallace V Rose wrote in message
<6voc9c$aphu$1@newssvr04-int.news.prodigy.com>...
>
>wwjj wrote in message <361D1460.49B5@mcmail.com>...
>>testing
>this is also a test.
>
>


Article: 12390
Subject: Re: FIR Filter Design
From: "Wallace V Rose" <COLOMBIA3@prodigy.net>
Date: Sat, 10 Oct 1998 15:04:58 -0500
Links: << >>  << T >>  << A >>
To everyone in this discussion:

 I have found your discussion on the comparison of fpga vs. dsp very good.
It beats the hell out of anything I have found in a book. If we worked in
the same office, I'd buy you all a hamburger and coke or ice-cream.

    Does any of you all know of a reference that might have actual program
examples of dsp on fpga chips?

Thanks in advance and I have really appreciated your discussion and the
depth of your skill and knowledge.

The Jungleman.


Article: 12391
Subject: Re: Software tool
From: "Ido Kleinman" <kleinn@mail.biu.ac.il>
Date: Sat, 10 Oct 1998 23:18:03 +0200
Links: << >>  << T >>  << A >>
Yes, I've indeed downloaded the tool and quite happy with it as well.
Did you purchase it for a single system or more?
What are the price ranges for this software?

How is it compared to the big ones like exemplar and synopsys?

--


Ido Kleinman.
kleinn@mail.biu.ac.il


Son P. Huynh wrote in message <6vlak7$5db$1@admin-srv3.micron.com>...
>Hello,
>
>I'm using Active-VHDL now and I like it a lot.  Very nice GUI and
>loaded with features.  You can always request a CD or have your
>computer running overnight...  It worth the download.
>
>Son Huynh



Article: 12392
Subject: Re: Xilinx F1.5/FPGA Express wackiness
From: Jeff Graham <drjeff@actrix.gen.nz>
Date: Sat, 10 Oct 1998 19:08:59 -0700
Links: << >>  << T >>  << A >>
I haven't had the Foundation updates yet, but the Alliance updates came
through this week, and I wasn't totally unsuprised to find that M1.5 is
just as appallingly bad at placing/routing 5200 series parts as M1.4
was.
- 5204 design with 65% utilisation when built with XACT6,  96%
utilisation in M1.5 and "unable to place design due to constraints
conflict"

Ah well, look like I'm stuck with XACT6 for another year ...


Jeff Graham
Hardware Team Leader
MAS Division
Digital Microwave Corp
Lower Hutt, New Zealand
Article: 12393
Subject: Re: Xilinix Foundation Install?
From: kickass4ever@my-dejanews.com
Date: Sun, 11 Oct 1998 04:35:18 GMT
Links: << >>  << T >>  << A >>
The license file needs to be wherever you point your LM_LICENSE_FILE
environment variable-- it was unclear from your message what variable you
used.

 1. Read the documentation.
 2. If that fails, try their support Web site, http://support.xilinx.com/ .
    Perform an Answers Search on your error message.

By the way, Xilinx is up to version F1.5 on the software.

Good luck.


In article <361F9F64.6C75@sympatico.ca>,
  leyton.collins@sympatico.ca wrote:
> Hi everybody,
>
> I just found out about this ng a few weeks ago and this is my first
> post.
>
> Anyway, I finally got around to installing my Foundation 1.3 package
> on my home PC so I can do some O/T w/o having to go into work. The
> problem is that even though I've registered w/ Xilinx, they sent me
> the license.dat file, I put it in the directory path in my autoexec.bat
> file, and when I try to compile the design it craps out w/ the error
> that it can't find the license file! I've tried re-installing the pfg
> 3 times w/ still no luck.
>
> Any suggestions (other than screaming and hitting the monitor ... didn't
> work)?
>
> Thanks,  Leyton
>

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 12394
Subject: Re: FIR Filter Design
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sun, 11 Oct 1998 01:06:44 -0400
Links: << >>  << T >>  << A >>
If they can ship live Maine Lobsters to California, why can't you ship the
hamburgers/ice cream? ;-)  Most of us would probably prefer a beer anyway.

I've got some papers that touch on aspects of DSP in FPGAs on my website (I'll
hopefully be adding one discussing a radar simulator soon--(if it is OK with
Rich Katz)).   You might also check the xilinx website (http://www.
xilinx.com).  There are a number of white papers there.  Look for a set of
presentation slides by Bruce Newgard.  Those slides had a few examples from
xilinx customers (that had a satellite modem in it).  None have the actual
FPGA bit streams or the complete set of schematics, as these belong to
customers (same is true of my papers), but it should give you an idea what is
possible.

Wallace V Rose wrote:

> To everyone in this discussion:
>
>  I have found your discussion on the comparison of fpga vs. dsp very good.
> It beats the hell out of anything I have found in a book. If we worked in
> the same office, I'd buy you all a hamburger and coke or ice-cream.
>
>     Does any of you all know of a reference that might have actual program
> examples of dsp on fpga chips?



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 12395
Subject: Re: Xilinx may not support schematics for Virtex?????
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 11 Oct 1998 01:40:22 -0400
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> I am very familiar with VHDL.  I don't see how this ties into my concerns
> with simulation....  You may be right, it may 'just' work, but somehow I
> doubt that, as it hasn't been the case in the past.

It is not a matter of 'just' working (I'm not sure what that means). But
translating a schematic into structural VHDL is something that could be
programmed by an entry level programmer. It is just a matter of using
the VHDL components to represent the symbols on your schematic. Then the
only problem you would have in simulation is if the VHDL simulator has
bugs. It might, but this is nothing like the problems you can have with
synthesis which can go beyond "bugs". Synthesis can do a good job of
figuring out what you want or a really bad job. So with no synthesis,
you have much fewer problems, much more on a level with other
simulators. 

 
> As I said, I know VHDL...  I didn't want this to turn into a VHDL v
> schematics.  I agree VHDL is a good and useful tool in some instances.  I
> also need and require schematics.

You can have schematics. I'm not trying to convert anyone. I just
thought from your comments that maybe you didn't have much exposure to
VHDL other than bad experiences. 

 
> For my designs, your above is absolutely incorrect.  Every design I do runs
> at 33+ MHz, and as such, requires a lot of mapping and placement.  ALSO,
> yes, I can buy the FASTEST MOST EXPENSIVE parts and use VHDL and hope and
> pray it works...OR I can use schematics, and ASSURE my design success in a
> finite amount of time, with cheaper silicone.

I find that 33 Mhz is very easy in VHDL with little or no optimization.
I just completed a XC4010XL-1 design with about 80% VHDL. I had to check
the VHDL to make sure it was giving me a clean design. But then this was
my learning exercise and I had to get a feel for what form of VHDL
worked with this particular tool. But I did not have to place a single
object other than pins. And this design ran at 33 up to 50 Mhz. 
 
> That's the truth of the matter, and I KNOW Ray and Philip will back me up
> on this one.  We all are consultants, and find a large part of the work we
> do is 'fixing' things for clients who have embarked on the panaceic VHDL
> journey, only to be sadly disappointed and aggravated by the results.  In
> fact, I know Xilinx has lost a lot of major design wins because of this
> exact problem.

I ran into this type of problem on my design when I started out using
the Orcad VHDL. It was a real showstopper. But when I switched to
Foundation, things started working very smoothly. I can't say anything
about other people's designs. 


> I either spend a lot of time instantiating things, and doing placement...OR
> convert it to schematics..and it magically works...AND they find their part
> cost is FAR less as they can use slower AND smaller parts!  Funny enough,
> the savings they have by doing schematics almost always pays for my time,
> and to boot, it even works when I'm done....

I did instantiate counters. I couldn't see how to get a carry in or out
cleanly from VHDL. You are right there. But I just didn't have that much
problem otherwise. 
 
> I actually have a very extensive programming background in C and assembly
> from both the applications level to the O/S level.  I am not afraid of
> programming.  I am afraid of not being able to do designs successfully and
> within a known time frame.

How large of a design have you done in schematics? How long did it take
from design start to get through simulation? I have only a little
experience to base my schedule estimates on so I would appreciate the
info.
 
> Interesting, and with all the VHDL experience I have, I wouldn't do another
> design for an FPGA using it as the primary tool, at least if I required
> high speed and low density.  I do use schematics for data path and some HDL
> for control logic, and usually end up converting most of the control logic
> from VHDL to gates to make timing....
> 
> Let's do an economic reasoning here...
> 
> Say a design fits in a $40 part with VHDL and a $24 part with schematics.
> And, some actually believe it's faster to do a design in VHDL, and it may
> be for some slower designs....but my experience has been very different, as
> you end up spending a lot of time fussing with the VHDL to make timing
> etc.... so let's say they both take the same amount of time to
> implement....so that's a wash.  If you have a build of 1000 boards, at an
> additional cost of $16, per board, that's $16,000.
> 
> VHDL for FPGAs is going to suffer the same problem Windows applications
> have with faster computers and cheaper storage...these features will mask
> bloated and slow designs.

If you make those assumptions, then you are right. I don't know that my
design would have been any smaller if I had done all of the work in
schematics. It came out pretty close to my original estimates. And I do
know that it would have taken me longer. Most of the time (other than
learning how to do good VHDL) was in designing, debugging and fixing my
control logic. This is an area where VHDL clearly excells over schematic
(at least in terms of development speed). I did have to take some time
to find out how to make the VHDL compilier produce a clean design. But
now that I understand that, it will go much more quickly with any
changes or new designs. 
 
> Austin
> 
> P.S.  I don't know about you, but I find it really hard to look at a stack
> of textual pages and know at a glance what the data flow and functionality
> of a design is....  May be I need to take that speed reading course again
> ;-)

Funny, I find a 30 page schematic hard to read. At least if I wasn't the
one to enter it. I've never met a designer yet that produced a clear
schematic for a complex design that didn't take some getting used to. 

I would say that you have a preference for schematic and I have a
preference for VHDL (at least until I get burned sometime). Maybe we
should let it go at that.  |8-)




-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12396
Subject: Re: Xilinx may not support schematics for Virtex?????
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 11 Oct 1998 01:45:10 -0400
Links: << >>  << T >>  << A >>
rk wrote:
> 
> > P.S.  I don't know about you, but I find it really hard to look at a stack
> > of textual pages and know at a glance what the data flow and functionality
> > of a design is....  May be I need to take that speed reading course again
> > ;-)
> 
> probably the best point.  i have never used vhdl for a top level.  while
> computers may be good at reading netlists, me, a humanoid, is not.  so i always
> put together the upper level or road map in a schematic, with sub-blocks
> designed as they make sense {vhdl, macro, schematics).  and i've jumped up and
> down enough about keeping schematics, some vendors wanna get rid of them, like
> chipx, who only support schematic for qyh500.  reading a huge textfile to get
> the flow of a design? never.  can't even read documentation on-line, i just
> print the whole thing out.  too old, i guess.
> 
> rk
> 
> p.s. extensive programming experience too [degree in it] so not afraid of text,
> programming, etc.

I'm not trying to pick a fight or anything, but this sounds like a
contradiction to me. If you are accustomed to programming in text why
would hardware be any different? SW has the same type of data flows and
control as hardware. 

I really like being able to look at code to get a feel for a design. Of
course a GOOD top level schematic is worth its weight in gold, but many
times it is not easy to do a clean, clear top level schematic for a
complex design. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12397
Subject: Re: Xilinx may not support schematics for Virtex?????
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 11 Oct 1998 01:53:21 -0400
Links: << >>  << T >>  << A >>
rk wrote:
> 
> ok, viewlogic, which i use, has an export1076 function which seems to work fine.  but
> to do that, you need the symbols and simulation models so you can do your design in
> the schematic and then simulate them.  i like simulating may desgins at the schematic
> level, you run the simulator, can stop it, look at the schematic, the values are
> sitting on those little lines for you to look at.

The VHDL simulator works the same here. In fact the one I used works
just like (well, a lot like) a C program debugger. You can open a signal
watch window as well as a waveform display. You can run for a time
period, set VHDL breakpoints or even single step through the VHDL code. 
 
> also,
> 
> say you goto vhdl [structural], what happens to your net names and reference
> designators, labels, instance names or whatever you call it?  if you lose this, then
> it may become much more difficult to talk to the other tools, like static timing
> analyzers and device editors or floorplanners.  are these attributes preserved and
> passed through unchanged?  or do we give up control?  can we guarantee that the vhdl
> compiler won't decide that it's smarter than you and do some optimization which might
> be bad for a particular application?  do we have to run around sticking in dont_touch
> and preserve attributes on every <insert 'cuss word here' net?
> 
> just a few questions.,

Again the one I used preserved the names from the schematic. It was the
synthesized VHDL where they tossed out signal names, but that was only
in a simulation of compiled VHDL. You could simulate the VHDL source and
not miss a thing. 

The simulator and synthesizer were from Orcad and I found many problems
with their tools. Too bad, since they had some good points too. I just
couldn't get them to work. With Foundation, your simulator is for gates.
So you could only simulate compilied VHDL. 
 
> rk
> 
> p.s. yeah, a geezer, still do a lot of schematics.
 
I may be geezing a little myself. But I just hate gate simulators and
simulation scripts. I really (really) liked testbenches. Like I said in
the earlier post, it was the testbench capability that sold me on VHDL.
And then I couldn't use it when I switched to Foundation!


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12398
Subject: Re: Xilinx may not support schematics for Virtex?????
From: rk <stellare@NOSPAMerols.com>
Date: Sun, 11 Oct 1998 09:05:03 -0400
Links: << >>  << T >>  << A >>
Rickman wrote:

> rk wrote:
> >
> > ok, viewlogic, which i use, has an export1076 function which seems to work fine.  but
> > to do that, you need the symbols and simulation models so you can do your design in
> > the schematic and then simulate them.  i like simulating may desgins at the schematic
> > level, you run the simulator, can stop it, look at the schematic, the values are
> > sitting on those little lines for you to look at.
>
> The VHDL simulator works the same here. In fact the one I used works
> just like (well, a lot like) a C program debugger. You can open a signal
> watch window as well as a waveform display. You can run for a time
> period, set VHDL breakpoints or even single step through the VHDL code.
>

watch windows are nice - got 'em in DOS a number of years ago.  seems to me it is much
easier just to look at a schematic and see all of the values and how all of the signals
interrelate.  the more modern s/w tools i'm using now still have watch windows.  but neat
feature, if you put the mouse over the signal name it'll put the value in a bubble - they
realized that watch windows were a pain.

most importantly, if the vendor doesn't support schematics, there are no symbols - we've
hit that problem before.  then you gotta make them yourself.

____________________________________________________

> > also,
> >
> > say you goto vhdl [structural], what happens to your net names and reference
> > designators, labels, instance names or whatever you call it?  if you lose this, then
> > it may become much more difficult to talk to the other tools, like static timing
> > analyzers and device editors or floorplanners.  are these attributes preserved and
> > passed through unchanged?  or do we give up control?  can we guarantee that the vhdl
> > compiler won't decide that it's smarter than you and do some optimization which might
> > be bad for a particular application?  do we have to run around sticking in dont_touch
> > and preserve attributes on every <insert 'cuss word here' net?
> >
> > just a few questions.,
>
> Again the one I used preserved the names from the schematic. It was the
> synthesized VHDL where they tossed out signal names, but that was only
> in a simulation of compiled VHDL. You could simulate the VHDL source and
> not miss a thing.

did it preserve the reference designators also?  most important for plunking the macros
down where you want them or to tell them to stay put once you got them in a good spot.

_____________________________________________________

> > p.s. yeah, a geezer, still do a lot of schematics.
>
> I may be geezing a little myself. But I just hate gate simulators and
> simulation scripts. I really (really) liked testbenches. Like I said in
> the earlier post, it was the testbench capability that sold me on VHDL.
> And then I couldn't use it when I switched to Foundation!

 i sort of like being able to talk to the simulator interactively, 'h' and 'l' and 'assign'
and then, for output, look at the schematic or do a print.  good way to get the design up
and running and find all the things that are fine for a good design but bad for the
simulator [like the classic divide by two f-f w/out reset].

Article: 12399
Subject: Re: Xilinx may not support schematics for Virtex?????
From: rk <stellare@NOSPAMerols.com>
Date: Sun, 11 Oct 1998 09:17:51 -0400
Links: << >>  << T >>  << A >>
Rickman wrote:

> rk wrote:
> >
> > > P.S.  I don't know about you, but I find it really hard to look at a stack
> > > of textual pages and know at a glance what the data flow and functionality
> > > of a design is....  May be I need to take that speed reading course again
> > > ;-)
> >
> > probably the best point.  i have never used vhdl for a top level.  while
> > computers may be good at reading netlists, me, a humanoid, is not.  so i always
> > put together the upper level or road map in a schematic, with sub-blocks
> > designed as they make sense {vhdl, macro, schematics).  and i've jumped up and
> > down enough about keeping schematics, some vendors wanna get rid of them, like
> > chipx, who only support schematic for qyh500.  reading a huge textfile to get
> > the flow of a design? never.  can't even read documentation on-line, i just
> > print the whole thing out.  too old, i guess.
> >
> > rk
> >
> > p.s. extensive programming experience too [degree in it] so not afraid of text,
> > programming, etc.
>
> I'm not trying to pick a fight or anything,

why not? it's getting a bit dull around here :-)

- - - - - - - - - - - - - - - - - - - - - - - - - - -

>                                                                            but this
> sounds like a
> contradiction to me. If you are accustomed to programming in text why
> would hardware be any different? SW has the same type of data flows and
> control as hardware.
>

nope, not at all.  traditional applications s/w is sequential, hardware is not.

also, time matters more in h/w than s/w and a well-drawn schematic you can easily see
how time progresses and how delays line up in various paths graphically - tougher to
do with a text-oriented format.

also it's a lot easier to see the relationships between blocks (or instantiated
macros) by following wires and busses on a schematic than having the eye-balls do
pattern matching on signal names and then connecting them together in the head.  of
course, that's where i take out the scrap paper and pencil and draw a schematic.

otoh, to see the operation of a sequencer, for example, it's generally easier to
follow a case statement with a enumerated type than a bank of flip-flops and a pile
of gates.  of course, it's even easier to see the operation when using a graphical
tool such as statecad - see rationale above.

___________________________________________________________________________

> I really like being able to look at code to get a feel for a design. Of
> course a GOOD top level schematic is worth its weight in gold, but many
> times it is not easy to do a clean, clear top level schematic for a
> complex design.

it does take time to make a 'GOOD' schematic/roadmap - but worth it.

and it's been, well, more than once, i had to make a schematic out of synthesized
code to see what the machine decided to do.  gotta keep schematics.




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