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Messages from 127550

Article: 127550
Subject: Re: Split Plane
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 2 Jan 2008 11:03:04 -0000
Links: << >>  << T >>  << A >>
"Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote in message 
news:13nmc65efhaqv29@corp.supernews.com...
>
> Have you ever measured the isolation between output channels on your 
> function generators, John?  I'd be curious to know the results... :-)
>
> ---Joel
>
>
Hi Joel,
Good post, thanks! I also would be interested in the answer to the question 
you pose!
Cheers, Syms. 



Article: 127551
Subject: Re: Split Plane
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 02 Jan 2008 13:05:38 GMT
Links: << >>  << T >>  << A >>
"Symon" <symon_brewer@hotmail.com> wrote:

>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
>news:fh7mn3pl84g9ccugdov2vml0nfg3f8le45@4ax.com...
>>
>> In order for the trace impedance to change as the trace cruises over
>> the gap, the potential in the middle of the gap would have to be
>> non-zero. But the electric field from the signal trace can hardly
>> penetrate through the gap... that's simple electrostatics. The signal
>> sees uniform ground above, and a slightly lower dielectric constant
>> below, in the gap region. That raises the trace impedance a tiny bit
>> just above the gap, for a tiny distance. The "reference plane" issue
>> is silly, as all the planes are at AC ground.
>>
>Hi John,
>
>I contend that the flaw in your thinking is that you are _only_ considering 
>"electrostatics", i.e. the electric field and associated capacitance of the 
>system. If you only understand voltage and capacitance, the slot is not a 
>problem for you. In fact, by the reasoning you follow above, a big slot in 
>both planes wouldn't be a problem, and I think this is what you're saying.
>
>Unfortunately, back in the real world, it's called electromagnetism. The 
>magnetic field is important in these systems. The slit will affect the 
>system, changing the loop area for the currents flowing, and the faster the 
>rise time, the more effect you will see due to this added inductance. The 
>effect may or may not be important, but what is important is to consider it.
>
>I'm gonna try this again. I think you do accept that current flows along the 
>trace, so where does the return current flow? Here's a clue. It's in the 
>planes. So, the current is flowing in a loop, right? And a loop has 
>inductance, right? And a big slot in the plane will make the loop area 
>bigger, right? And a bigger area loop has more inductance, right?

If I may interfere. I believe John is right in stating that all power
planes are AC coupled through almost zero impedance. Hence, the return
current will not go around the slit but 'jumps along' with the signal.
At high frequencies, the trace will act as a microstrip line *. 

*All this assuming there is a continuous ground plane.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 127552
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 02 Jan 2008 13:13:51 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <alfke@sbcglobal.net> wrote:

>On Jan 1, 4:49=A0pm, Frank Buss <f...@frank-buss.de> wrote:
>>
>> I wonder how they manage 500 fs (yes, femto seconds) jitter with this chea=
>p
>> chip:
>>
>> http://www.analog.com/en/prod/0,2877,AD9540,00.html
>>
>> Is this the performance of the DDS, or just the jitter the device adds to
>> the reference clock? But nevertheless, a programmable delay line would be =
>a
>> nice idea for eliminating jitter, without the need for analog circuits. Th=
>e
>> required delay time could be calculated with the current accumulator value=
>
>> (the bits below the carry).
>
>There are wonderful marketing methods for specifying jitter.
>Using "RMS" you can divide the  "worst-case cycle-to-cycle jitter"
>value by a factor 14.
>And worst-case cycle-to-cycle jitter totally ignores the aspect of
>"wander".

I still wonder how you get it temperature stabilized if you want to
eliminate wander. From my experience with E1 synchronisation systems
(I've designed a dpll +/-200ppm in 0.5ppm steps in a Spartan II for
that purpose). Just opening the case changed the temperature of the
oscillator enough to have the PLL to adjust a few steps.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 127553
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 02 Jan 2008 13:16:48 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <alfke@sbcglobal.net> wrote:

>
>For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps
>jitter)
>I need an LCD-backlit or OLED display,  128 x 64 bits, single or

The word is that OLED is about to be abandoned. TFT with LED
backlighting is probably cheaper to produce.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 127554
Subject: Re: Split Plane
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 2 Jan 2008 13:26:02 -0000
Links: << >>  << T >>  << A >>
"Nico Coesel" <nico@puntnl.niks> wrote in message 
news:477b8799.7944072@news.planet.nl...
>
> If I may interfere. I believe John is right in stating that all power
> planes are AC coupled through almost zero impedance. Hence, the return
> current will not go around the slit but 'jumps along' with the signal.
> At high frequencies, the trace will act as a microstrip line *.
>
> *All this assuming there is a continuous ground plane.
>
Hi Nico,
If that was _entirely_ true, you wouldn't need bypass caps. That said, I 
agree they are coupled fairly well, especially at high frequencies, which is 
why a slot in one of them isn't such a big deal. Probably. I stand by my 
original assertion that the slot will be an impedance discontinuity. It may 
well be very small, but we have no details on the board geometry and so we 
don't know.
HTH., Syms. 



Article: 127555
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: jcr_alr@xplornet.com
Date: Wed, 2 Jan 2008 05:34:37 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 2, 8:16=A0am, n...@puntnl.niks (Nico Coesel) wrote:
> Peter Alfke <al...@sbcglobal.net> wrote:
>
> >For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps
> >jitter)
> >I need an LCD-backlit or OLED display, =A0128 x 64 bits, single or
>
> The word is that OLED is about to be abandoned. TFT with LED
> backlighting is probably cheaper to produce.
>
> --
> Reply to nico@nctdevpuntnl (punt=3D.)
> Bedrijven en winkels vindt U opwww.adresboekje.nl

A number of displays on the market are still not ROHS compliant, for
instance, the nice looking TFT displays advertised by EarthLCD.

John Robbins

Article: 127556
Subject: Re: Split Plane
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 02 Jan 2008 06:28:09 -0800
Links: << >>  << T >>  << A >>
Nico Coesel wrote:
> 
> If I may interfere. I believe John is right in stating that all power
> planes are AC coupled through almost zero impedance. Hence, the return
> current will not go around the slit but 'jumps along' with the signal.
> At high frequencies, the trace will act as a microstrip line *. 
> 
> *All this assuming there is a continuous ground plane.

At least you still believe in conservation of charge, right?  Since 
there is no direct current path across a plane split, you're suggesting 
that the displacement current (as used in describing current in 
capacitors) is the full current level found on both sides of that split? 
  Wouldn't the electrostatic effects of this displacement current (given 
the small dielectric constant/capacitance of FR4) produce a voltage step?

All planes are AC grounded, sure.  But to what level?  I've watched the 
effects of signal perturbations on a TDR, too, and I see capacitive or 
inductive hiccups at poor interfaces.  The impedance is the same on both 
sides of the split but the inductive or capacitive transition can easily 
be greater than a nanosecond.

Current cannot simply "jump along" in the sense of stopping on one side 
and starting on the other side of a split without displacement current 
or induced voltages.  While the voltage change will be small due to thee 
low impedance of the plane, the sub-nanohenry impedance is measurable. 
If caps are nearby, this impedance is less than if those capacitors were 
further away but it is still a finite value.  There can't be a jump 
without an induced voltage.

If the charge path for a signal was completely unconstrained and used 
the entire plane at the transition speeds that are important, the caps 
would be all we need to worry about, not the splits at all.  The 
continuity of charge is, however, confined to a small area around the 
signal until these disconnects are encountered.  For a signal to 
propagate, the reflected current must be on both sides of the split; 
where your "zero impedance" gets lost is in the real voltage generated 
at this split which has a real impedance associated with it.  Ground 
planes are AC shorts, but this is only an approximation.  At the real 
frequencies, the impedance is measurable - sub-nanohenry, perhaps, but 
measurable.

- John_H

Article: 127557
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 02 Jan 2008 06:43:08 -0800
Links: << >>  << T >>  << A >>
Nico Coesel wrote:
> 
> I still wonder how you get it temperature stabilized if you want to
> eliminate wander. From my experience with E1 synchronisation systems
> (I've designed a dpll +/-200ppm in 0.5ppm steps in a Spartan II for
> that purpose). Just opening the case changed the temperature of the
> oscillator enough to have the PLL to adjust a few steps.

One of the bigger troubles in DDS systems isn't the typical wander 
encountered in oscillators noted by the Allan Variance but the problem 
of the difference between the instantaneous DDS frequency being 
different from the idea in the form of a phase error sawtooth function. 
  This phase error will allow a PLL to track a very slow sawtooth curve 
for most of the sawtooth but will slew across the sharp transition at a 
rate dependent on the PLL filter.  If you have a phase accumulator value 
that's very close to some 2^n value, the DDR output will be a frequency 
related to the 2^n value with occasional phase steps to account for that 
small error.  That raw DDS output phase step isn't filtered by a PLL 
loop function if the occurrence is much slower than the loop filter 
corner frequency.

For most situations, wander in the Allan Variance sense isn't a problem; 
it's the phase steps that are a problem.  Designing a DDS that provides 
a fixed frequency with a simple PLL output isn't a problem either if the 
engineer has the opportunity to choose from a few oscillator values, 
choosing a frequency ratio that doesn't produce low-frequency error 
functions of any measurable phase step.  It's the general purpose DDS 
where the frequency can be tuned to 1 Hz off of a subharmonic of the 
system clock that you'll see that 1 Hz occurrence of a phase step.

We'll have a chance to see Peter manipulate the error to the PLL to both 
keep the desired frequency to the precision of the input oscillator AND 
to avoid those phase steps from the inherent sawtooth error.

It's such fun stuff!

- John_H

Article: 127558
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 2 Jan 2008 08:34:56 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 2, 6:43=A0am, John_H <newsgr...@johnhandwork.com> wrote:
>
> For most situations, wander in the Allan Variance sense isn't a problem;
> it's the phase steps that are a problem. =A0Designing a DDS that provides
> a fixed frequency with a simple PLL output isn't a problem either if the
> engineer has the opportunity to choose from a few oscillator values,
> choosing a frequency ratio that doesn't produce low-frequency error
> functions of any measurable phase step. =A0It's the general purpose DDS
> where the frequency can be tuned to 1 Hz off of a subharmonic of the
> system clock that you'll see that 1 Hz occurrence of a phase step.
>
> We'll have a chance to see Peter manipulate the error to the PLL to both
> keep the desired frequency to the precision of the input oscillator AND
> to avoid those phase steps from the inherent sawtooth error.
>
> It's such fun stuff!
>
> - John_H
Thanks, John.
Excellent high-level description of one of the methods we use to
reduce jitter to an acceptable level. Even the smallest Virtex-5LXT
has plenty of resources (includong gigabit transcevers) to do
wonderful things.
Let's check the results, soon.
Peter alfke

Article: 127559
Subject: Re: Split Plane
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 02 Jan 2008 09:10:03 -0800
Links: << >>  << T >>  << A >>
On Wed, 2 Jan 2008 10:55:38 -0000, "Symon" <symon_brewer@hotmail.com>
wrote:

>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
>news:fh7mn3pl84g9ccugdov2vml0nfg3f8le45@4ax.com...
>>
>> In order for the trace impedance to change as the trace cruises over
>> the gap, the potential in the middle of the gap would have to be
>> non-zero. But the electric field from the signal trace can hardly
>> penetrate through the gap... that's simple electrostatics. The signal
>> sees uniform ground above, and a slightly lower dielectric constant
>> below, in the gap region. That raises the trace impedance a tiny bit
>> just above the gap, for a tiny distance. The "reference plane" issue
>> is silly, as all the planes are at AC ground.
>>
>Hi John,
>
>I contend that the flaw in your thinking is that you are _only_ considering 
>"electrostatics", i.e. the electric field and associated capacitance of the 
>system. If you only understand voltage and capacitance, the slot is not a 
>problem for you. In fact, by the reasoning you follow above, a big slot in 
>both planes wouldn't be a problem, and I think this is what you're saying.

TDR is not electrostatics. And hand-waving is not measurement.


>
>Unfortunately, back in the real world, it's called electromagnetism. The 
>magnetic field is important in these systems. The slit will affect the 
>system, changing the loop area for the currents flowing, and the faster the 
>rise time, the more effect you will see due to this added inductance. The 
>effect may or may not be important, but what is important is to consider it.
>
>I'm gonna try this again. I think you do accept that current flows along the 
>trace, so where does the return current flow? Here's a clue. It's in the 
>planes. So, the current is flowing in a loop, right? And a loop has 
>inductance, right? And a big slot in the plane will make the loop area 
>bigger, right? And a bigger area loop has more inductance, right?

The edges of the plane gap are glued together by plane-plane
capacitance and by the capacitance across the gap itself, which
extends across a lot more width than the size of the signal trace. So
the "loop area" increase is tiny. Again, the planes are equipotential,
all at AC ground, as far as the signal edge is concerned.

I sure wish people would get some copperclad, an xacto knife, and a
good TDR, and try some of this stuff, instead or reading books about
"black magic."


>
>However, the two of us have been here before, and I know you don't believe 
>this. I'm posting for the benefit of others who might be caught out by 
>ignoring the magnetic field set up by the currents in the planes and traces 
>so they can make up their own minds. (I suggest SI-list for further reading) 
>Up until recently, regular FPGA I/O circuits were not quick enough for this 
>to be a big problem, but they will be for everyone soon. Maybe not today. 
>Maybe not tomorrow, but soon and for the rest of your life!
>
>I know this won't help, Syms.
>
>p.s. I agree, having a slot in only one plane is nowhere near the same as a 
>slot in both. Here's a link for why a single reference plane with a slot is 
>bad. It's easy to see that another plane can all but short out the return 
>current.
>http://www.hottconsultants.com/techtips/tips-slots.html 
>

Goofy. How does he get 15 mV with zero slot length? And what's the
slot width? Signal amplitude? And 75 mV of ground noise isn't a signal
integrity issue; it might be an emi issue.

John


Article: 127560
Subject: Re: no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02
From: Bryan <bryan.fletcher@avnet.com>
Date: Wed, 2 Jan 2008 09:14:30 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 1, 12:07=A0pm, ata <a...@ata.nnet> wrote:
> In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP
> Starter Kit, the base-system-builder doesn't give me the option of
> adding the SystemACE peripheral to the hardware environment.
>
> In a text-editor, I manually examined
> ./board/Xilinx/boards/Xilinx_S3ADSP1800_RevA/data/Xilinx_S3ADSP1800_RevA_v=
2=AD_2_0.xbd
>
> The interface and I/O declarations related to the SystemACE peripheral
> are commented out...
>
> What's the status of the hardware on the board? =A0Is there a known
> problem, or is it just untested?

The 1800ADSP board was tested with the Avnet SystemACE Module
(www.em.avnet.com/systemace).  I believe the reason this feature is
commented out in the XBD file is that it is not a standard feature
that ships with the board.  However, the end user can enable it by
uncommenting the lines in the XBD.

Bryan

Article: 127561
Subject: spartan 3e JTAG programming
From: katherine <weston_katherine@yahoo.co.uk>
Date: Wed, 2 Jan 2008 09:28:57 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi guys

I have two spartan 3e's and a coolrunner in a single JTAG chain.

If I program either FPGA from power up its outputs do not drive, but I
can read the JTAG user register and it has the value that I set from
"generate programming file" so the binary is in the FPGA but the IO
doesn't get driven, presumably the "enable outputs" state in the
startup sequence never occurs.

When I program the other FPGA it works correctly, but the first still
does not drive.

I then reprogram the first FPGA and it now works correctly as well.

prog_b is driven high throughout the above.
The two done's are connected together and pulled up to 2v5.
the init_b's are connected together and pulled up to 3v3 (the bank IO
voltage)

I haven't seen any activity on the done or init_b signals.

Could someone please point me to which signal from the unprogrammed
fpga stops the first FPGA from driving out forever.

thanks and regards

Katherine

Article: 127562
Subject: Re: Split Plane
From: Dave Pollum <vze24h5m@verizon.net>
Date: Wed, 2 Jan 2008 10:16:48 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 2, 12:10 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
wrote:

> I sure wish people would get some copperclad, an xacto knife, and a
> good TDR, and try some of this stuff, instead or reading books about
> "black magic."

John - can you recommend any web sites or books that show results of
testing PCBs with a TDR?  I think that real results would settle these
arguments.  I can't afford a TDR (and don't know how to use one), so I
can't do the tests myself.  Any volunteers?

-Dave Pollum

Article: 127563
Subject: Re: spartan 3e JTAG programming
From: austin <austin@xilinx.com>
Date: Wed, 02 Jan 2008 10:24:29 -0800
Links: << >>  << T >>  << A >>
Katherine,

Often the start-up sequence requires a few extra clocks to complete.
Check to see if you are sending enough nulls after the end of the bitstream.

http://www.xilinx.com/support/documentation/user_guides/ug332.pdf

page 238

The startup sequence requires eight more clocks to complete, so if you
stop the TCK on the JTAG, then you have loaded the bitstream, but have
not clocked through the startup sequence state machine.

Austin

Article: 127564
Subject: Re: Split Plane
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 2 Jan 2008 18:41:13 -0000
Links: << >>  << T >>  << A >>
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:8ngnn395bbl4vslj5q0fk9bm388piena57@4ax.com...
>
> I sure wish people would get some copperclad, an xacto knife, and a
> good TDR, and try some of this stuff, instead or reading books about
> "black magic."
>
>
Hi John,
Thanks for your reply. I think you read this before and picked holes in it, 
but for the benefit of other readers, here's a link to a guy who did a 
similar xacto experiment to the one suggested by John.
http://www.emcesd.com/tt2002/tt120102.htm
Now, the signal in his experiment still gets to the destination kinda ok, 
but there's a voltage across the slit. This voltage will crosstalk into 
anything else crossing the slit and will radiate.

There are further experiments here:-
http://www.emcesd.com/tt2003/tt010103.htm
http://www.emcesd.com/tt2003/tt020103.htm

Cheers, Syms.

p.s. Please let me re-iterate that I'm in close agreement with John that, in 
the OP's case with two adjacent planes only one of which has a slot, it's 
very likely there will be little if anything to worry about at regular FPGA 
speeds. Crosstalk and reflections likely won't be a problem. But, 
multi-gigabit signals are now possible from FPGAs and I advise caution even 
with differential signals. (Indeed from the first link above, "For cases of 
a broken ground plane over a solid power plane, or vice versa, there may or 
may not be a problem depending on several factors including plane spacing.")






Article: 127565
Subject: Re: Split Plane
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 02 Jan 2008 10:48:19 -0800
Links: << >>  << T >>  << A >>
John_H wrote:
> Nico Coesel wrote:

>> If I may interfere. I believe John is right in stating that all power
>> planes are AC coupled through almost zero impedance. Hence, the return
>> current will not go around the slit but 'jumps along' with the signal.
>> At high frequencies, the trace will act as a microstrip line *.
>> *All this assuming there is a continuous ground plane.

> At least you still believe in conservation of charge, right?  Since 
> there is no direct current path across a plane split, you're suggesting 
> that the displacement current (as used in describing current in 
> capacitors) is the full current level found on both sides of that split? 
>  Wouldn't the electrostatic effects of this displacement current (given 
> the small dielectric constant/capacitance of FR4) produce a voltage step?

With a continuous ground plane and discontinuous power plane, the
impedance pretty much doubles across the width of the gap.  For 
wavelengths much (maybe more than 10 times) the gap width the impedance 
discontinuity should be pretty much not noticed.  As the current
(or charge, as you say) approaches the gap it spreads out, capacitively
couples to the ground plane, crosses the gap, and capacitively couples
back to the other power plane.  At higher and higher frequencies that
process doesn't work as well.  Also, that assumes an infinite ground
plane.

> All planes are AC grounded, sure.  But to what level?  I've watched the 
> effects of signal perturbations on a TDR, too, and I see capacitive or 
> inductive hiccups at poor interfaces.  The impedance is the same on both 
> sides of the split but the inductive or capacitive transition can easily 
> be greater than a nanosecond.

The effect should be a lot worse without the continuous ground plane
the OP specified.

> Current cannot simply "jump along" in the sense of stopping on one side 
> and starting on the other side of a split without displacement current 
> or induced voltages.  While the voltage change will be small due to thee 
> low impedance of the plane, the sub-nanohenry impedance is measurable. 
> If caps are nearby, this impedance is less than if those capacitors were 
> further away but it is still a finite value.  There can't be a jump 
> without an induced voltage.

Yes.  The question, then, is how big is that voltage relative to
the allowed noise in the signal.  That depends on the possible
current paths (through nearby or not so near bypass capacitors,
or interplane capacitance).   Without the continuous ground
plane the gap impedance is infinite.  With the ground plane,
it only doubles.  That makes a big difference.

> If the charge path for a signal was completely unconstrained and used 
> the entire plane at the transition speeds that are important, the caps 
> would be all we need to worry about, not the splits at all.  The 
> continuity of charge is, however, confined to a small area around the 
> signal until these disconnects are encountered.  For a signal to 
> propagate, the reflected current must be on both sides of the split; 
> where your "zero impedance" gets lost is in the real voltage generated 
> at this split which has a real impedance associated with it.  Ground 
> planes are AC shorts, but this is only an approximation.  At the real 
> frequencies, the impedance is measurable - sub-nanohenry, perhaps, but 
> measurable.

Non-infinite planes and the skin effect coming into play.

-- glen


Article: 127566
Subject: Looking for used spartan3 fpga board
From: Thuy Pham <thuyp@xilinx.com>
Date: Wed, 02 Jan 2008 11:10:21 -0800
Links: << >>  << T >>  << A >>
Hi All,

I am looking for an old Spartan3a fpga board to test a school project
for my sister. If you have and want to sell , please contact me.

Regards
Thuy


Article: 127567
Subject: OpenCores tracker and forum doesn't work?
From: wzab <wzab01@gmail.com>
Date: Wed, 2 Jan 2008 11:59:32 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi All,

I just tried to submit a bug to OpenCores, and found that even though
the report input form works
(eg. http://www.opencores.org/ptracker.cgi/add/or1k?type=BUG )
the image required to fill the "key" field is not displayed.
If i right-click the image placeholder and select "show the image", I
get the page
with "http://www.opencores.org/captcha.cgi?name=ptracker_add_BUG"
contents.

When I tried to send info about this problem to the OpenCores forum,
it came back with the following information:

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
This is the mail system at host www.opencores.org.

I'm sorry to have to inform you that your message could not
be delivered to one or more recipients. It's attached below.

For further assistance, please send mail to postmaster.

If you do so, please include this problem report. You can
delete your own text from the attached returned message.

                   The mail system

<cores@opencores.org>: mail forwarding loop for cores@opencores.org
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Has anybody experienced similar problems?
Is anybody associated with OpenCores reading this forum?
--
Regards,
Wojciech M. Zabolotny

Article: 127568
Subject: Re: OpenCores tracker and forum doesn't work?
From: John McCaskill <jhmccaskill@gmail.com>
Date: Wed, 2 Jan 2008 12:12:01 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 2, 1:59 pm, wzab <wza...@gmail.com> wrote:
> Hi All,
>
> I just tried to submit a bug to OpenCores, and found that even though
> the report input form works
> (eg.http://www.opencores.org/ptracker.cgi/add/or1k?type=BUG)
> the image required to fill the "key" field is not displayed.
> If i right-click the image placeholder and select "show the image", I
> get the page
> with "http://www.opencores.org/captcha.cgi?name=ptracker_add_BUG"
> contents.
>
> When I tried to send info about this problem to the OpenCores forum,
> it came back with the following information:
>
> vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
> This is the mail system at hostwww.opencores.org.
>
> I'm sorry to have to inform you that your message could not
> be delivered to one or more recipients. It's attached below.
>
> For further assistance, please send mail to postmaster.
>
> If you do so, please include this problem report. You can
> delete your own text from the attached returned message.
>
>                    The mail system
>
> <co...@opencores.org>: mail forwarding loop for co...@opencores.org
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> Has anybody experienced similar problems?
> Is anybody associated with OpenCores reading this forum?
> --
> Regards,
> Wojciech M. Zabolotny


I saw your email on the cores@opencores.org mail list, so your email
did go out.

Regards,

John McCaskill
www.fastertechnology.com

Article: 127569
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 02 Jan 2008 13:33:54 -0800
Links: << >>  << T >>  << A >>
On Tue, 1 Jan 2008 22:11:28 -0800 (PST), Peter Alfke
<alfke@sbcglobal.net> wrote:

>On Jan 1, 9:53 pm, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> On Tue, 1 Jan 2008 15:54:06 -0800 (PST), Peter Alfke
>>
>> <al...@sbcglobal.net> wrote:
>> >Thanks, Frank, for the URL. I will investigate. A little pricey, but
>> >not out of the question.
>>
>> >Regarding the jitter, I can be more specific in a few weeks, when we
>> >have the pre-production version (with the OSRAM display) really
>> >working. Until now we have used various form of emulation.
>>
>> >Yes, jitter is the overwhelming issue, and it is 1/fclock coming out
>> >of the DDS accumulator, about 2 ns.
>> >There is a lot of trickery involved to get the jitter down. The most
>> >demanding chore is reducing "wander", i.e. low-frequency components in
>> >the jitter spectrum that cannot be filtered out by any analog PLL,
>> >but I think we are (almost) there.
>>
>> Are you planning to reduce the DDS jitter to sub-clock levels on-chip,
>> or are you going to use an external dac-filter-comparator thing?
>>
>> The on-chip thing could get awfully interesting.
>>
>> Wander will of course depend on the phase noise of the external master
>> clock. And fpga prop delays will stagger around with tiny temperature
>> fluctuations. Adding thermal insulation and thermal mass to both the
>> fpga and the xo can do remarkable things. We're getting under 30 ps
>> RMS jitter+wander from a delay generator that uses a cheap xo and a
>> Spartan3. A cheap xo will typically have a 1/f sort of jitter corner
>> in the 500 Hz sort of ballpark, hitting a few ns RMS at 1 Hz.
>>
>> Somebody just quoted us on a 16x2 backlit alphanumeric lcd, 30 mm
>> high, about $7 in small quantity. Do you really need graphics?
>>
>> John
>
>John, please tell me more about that display.
>Graphics is just a nice luxury, but backlit or OLED is important.

http://www.newhavendisplay.com/

They're sending us a sample of part number NHD-0220AU-FSW-FTS, 2x20
with white backlight, around $7. Should be here soon. I'll let you
know how it looks.

There are tons of 2x16 and 2x20, 33 mm high backlit displays around.
We picked this 30 mm unit because we're squeezed on height.

John



Article: 127570
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 02 Jan 2008 13:35:47 -0800
Links: << >>  << T >>  << A >>
On Tue, 01 Jan 2008 17:37:17 -0800, Eric Smith <eric@brouhaha.com>
wrote:

>Peter Alfke <alfke@sbcglobal.net> writes:
>> Billions of cellphones, cameras, and iPods are being made, but where
>> can I buy a couple of hundred displays?
>
>http://www.sparkfun.com/
>
>They don't have anything that meets your exact description, but they
>probably have something you can live with.
>
>The companies that make such displays don't even want to waste time
>talking to a potential customer if that party isn't likely to buy
>100K units.


The Newhaven people claim they'll do custom glass for about $1000 NRE.

John


Article: 127571
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: gavin@allegro.com (Gavin Scott)
Date: Wed, 02 Jan 2008 23:58:01 -0000
Links: << >>  << T >>  << A >>
Eric Smith <eric@brouhaha.com> wrote:
> The companies that make such displays don't even want to waste time
> talking to a potential customer if that party isn't likely to buy
> 100K units.

Dammit Eric, I nearly choked to death on my drink :-)

G.

Article: 127572
Subject: Re: Where are the LCD or OLED bitmapped displays?
From: Brian Davis <brimdavis@aol.com>
Date: Wed, 2 Jan 2008 19:00:29 -0800 (PST)
Links: << >>  << T >>  << A >>
John_H wrote:
>
>One of the bigger troubles in DDS systems isn't the typical wander
>encountered in oscillators noted by the Allan Variance but the problem
>of the difference between the instantaneous DDS frequency being
>different from the idea in the form of a phase error sawtooth function.
>

 I've also seen this often in multi-bit DDS's, where both phase
and amplitude truncation/quantization cause close in spurs that
are troublesome, especially if the DDS output is being heavily
multiplied ( e.g. when used as a PLL reference with big N. )

  Since that lengthy 2002-vintage synthesizer thread where I
attempted to describe this [1], I have put together some more
detailed plots showing the spurs collapsing in on the carrier
near a 'bad' tune word [2]; as further explained in a couple
of associated posts [3], these plots just model the numerical
artifacts, not any analog harmonic aliases or nonlinearities.

Brian

[1] close in DDS phase noise artifacts:
 http://groups.google.com/group/comp.arch.fpga/msg/0b1a2f345aa1c350

[2] plots of DDS spur pileups ( modeling numeical spurs only )
  http://members.aol.com/fpgastuff/dds_oddities.pdf

[3] related posts about the pdf file in [2]
  http://groups.yahoo.com/group/spectrumanalyzer/message/1027
  http://groups.yahoo.com/group/spectrumanalyzer/message/1038

Article: 127573
Subject: Re: Split Plane
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 02 Jan 2008 19:21:57 -0800
Links: << >>  << T >>  << A >>
On Wed, 2 Jan 2008 18:41:13 -0000, "Symon" <symon_brewer@hotmail.com>
wrote:

>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
>news:8ngnn395bbl4vslj5q0fk9bm388piena57@4ax.com...
>>
>> I sure wish people would get some copperclad, an xacto knife, and a
>> good TDR, and try some of this stuff, instead or reading books about
>> "black magic."
>>
>>
>Hi John,
>Thanks for your reply. I think you read this before and picked holes in it, 
>but for the benefit of other readers, here's a link to a guy who did a 
>similar xacto experiment to the one suggested by John.
>http://www.emcesd.com/tt2002/tt120102.htm
>Now, the signal in his experiment still gets to the destination kinda ok, 
>but there's a voltage across the slit. This voltage will crosstalk into 
>anything else crossing the slit and will radiate.



For Pete's sake, he used WIRES. He couldn't even afford an x-acto
knife.


>
>There are further experiments here:-
>http://www.emcesd.com/tt2003/tt010103.htm
>http://www.emcesd.com/tt2003/tt020103.htm
>

Not too surprising, 20 cm away from what appears to be a kilovolt
spark gap. It's difficult to make any sort of quantitative
extrapolation from this to real circuits.

John



Article: 127574
Subject: Re: no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02
From: ata <ata@ata.nnet>
Date: Thu, 03 Jan 2008 07:39:46 GMT
Links: << >>  << T >>  << A >>
On Wed, 2008-01-02 at 09:14 -0800, Bryan wrote:
> On Jan 1, 12:07 pm, ata <a...@ata.nnet> wrote:
> > In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP
> > Starter Kit, the base-system-builder doesn't give me the option of
> > adding the SystemACE peripheral to the hardware environment.
> >
> > In a text-editor, I manually examined
>
> ./board/Xilinx/boards/Xilinx_S3ADSP1800_RevA/data/Xilinx_S3ADSP1800_RevA_=
v2=C2=AD_2_0.xbd
> >
> > The interface and I/O declarations related to the SystemACE
peripheral
> > are commented out...
>
> The 1800ADSP board was tested with the Avnet SystemACE Module
> (www.em.avnet.com/systemace).  I believe the reason this feature is
> commented out in the XBD file is that it is not a standard feature
> that ships with the board.  However, the end user can enable it by
> uncommenting the lines in the XBD.

Ahh, that makes sense!  Thank you.

For a minute there, I thought this was another one of those deja-vu=20
moments where Xilinx published the marketing specs of a product=20
before they had a chance to validate the feature-set on actual
production units (*cough* Virtex-4/FX...)




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