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On Jan 5, 12:31 pm, posedg...@yahoo.com wrote: > I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 > -6T F). > Is there any *simple* demo that stores a picture bitmap in the builtin > DDR SDRAM and sends the bitmap to the VGA port continously ..? I designed a DDR controller with wishbone interface for that board -- I know it works well on a bunch of S3E-500 StarterKits, one S3E-1600 and I even use a variant on the XUPV2P Board. But it's not ideally suited for your design, because it uses 2 BlockRAMs to cache access to the DRAM -- If you can live with that.... See https://roulette.das-labor.org/bzrtrac/wiki/wb_ddr jb

Hi All , I am trying to interface microblaze with a Micron DDR SDRAM (MT46V16M16FG-75 16Mx16) using MPMC from the IP catalogue. As I am running on Spartan 3 FPGA I need to connect port lines - DDR_DQS_DIV_O and DDR_DQS_DIV_I , else I get errors , it also states that these should be connected in for spartan 3. The problem is that there is not much documentation about these port lines in the MPMC data sheet. Has anyone used this? does any one know how to connect these lines up? thanks in advance BR rate

On 5 Jan, 11:31, posedg...@yahoo.com wrote: > I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 > -6T F). > Is there any *simple* demo that stores a picture bitmap in the builtin > DDR SDRAM and sends the bitmap to the VGA port continously ..? > > Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL > used ..? > (Micron indicate that SDRAM can go as low as a few kHz in clock > frequency if needed) > > I had a look at 3 Xilinx examples, but they seem almost more > complicated to get running than to code a sdram controller by myself. > Currently trying out opencores controller, but it seems to get stuck > synthesis. > > What voltage is Vtt supposed to have for ddr sdram?, Is every resistor > needed, or can one do with a simpler interface if the dram <-> fpga > path is less than 1 inch/2 cm ..? I am in the process of implementing a interface between microblaze and Micron DDR SDRAM using MPMC from the IP catalog provided in EDK 9.2i. It has all the neccesary ports defined and support most DDR/DDR2 devices. I have not tested it yet, but it might be worth a try. BR rate

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:Rr2dnc0taeLINuPanZ2dnUVZ_v-hnZ2d@comcast.com... Hi Glen, Do you not think that the trace inductance and magnetic field are important? You don't mention them at all in your post. Just thinking about the capacitance is not the whole story... HTH., Syms.

my module is as follows: entity tri_state_bus is Port ( data : inout STD_LOGIC_VECTOR (15 downto 0); cs : in STD_LOGIC; rd : in STD_LOGIC; we : in STD_LOGIC; clk: in STD_LOGIC; din : in STD_LOGIC_VECTOR (15 downto 0); dout : out STD_LOGIC_VECTOR (15 downto 0)); end tri_state_bus; architecture dbus of tri_state_bus is begin process(clk) begin if(clk'event and clk='1') then if(cs='1') then data<=(others=>'Z'); elsif(rd='0') then data<=din; elsif(we='0') then dout<=data; end if; end if; end process; end dbus; ------------------ the problem is: i can synthesis by ISE/XST,but i can't obtain the correct results when simulated using modelsim, can anyone tell me where is the problem?

On Jan 4, 3:17=A0pm, Mike Treseler <mike_trese...@comcast.net> wrote: > FPGA wrote: > > I have 2 inputs > > x : unsigned > > bw : integer > > when x>bw I want to check if x(x'length downto bw) =3D "1111111......" > > How do i write this in VHDL since my length of x is unknown > > A vector of unknown length could be > an entity port or a subprogram parameter. > > These are usually handled using > the array attributes 'length or 'range. > and a for loop like this: > > =A0for i in x'range loop > =A0 =A0 result :=3D some_function(result, x(i)); > =A0end loop; > > =A0 =A0 =A0 -- Mike Treseler I actually want to AND all the bits of the x vector whole length is unknown. I want to check if all the bits of the vector x are "1111...." . How would I do it, since the length is unknown. I want to check is x(x'length-1) AND x(x'length-2) AND x(x'length-3) AND .... x(0) =3D '1' -- which checks if all bits of the input are one.

I am converting an integer to a single precision floating point number. I understand that floating point number comprises of sign bit(1 bit), exponent(8 bits) and significand(23 bits). I can check if input < 0 and get the sign bit. To get the exponent and mantissa, I have to convert the integer to binary. I am using the function "to_unsigned" in VHDL. The problem is since i dont know how big of an integer i can get as input, I dont know how i should declare the length of the binary vector . The integer to binary conversion could give me anywhere from a minumum of 1 bits to a maximum of (I dont know). I would like to know how to solve this problem

>In theory yes. However there are still loads of MAC address ranges >assigned to companies which are long gone or have moved into a >different direction. Unless you will be making millions of units, it >is quite safe to pick one of those. If you have a LAN with 200 (non-clashing) MAC addresses and generate a random (40-bit) address for your node, the probability of its clashing with an existing address is 200/2^40 (call this P), which is about one in 5,5000,000,000 If you make ten million units and each is added to a LAN which already has 200 nodes, the probability of having no clash is (1-P)^10,000,000, which is about 1-10,000,000P, so the probability of a clash is about 10,000,000P = one in 550. So, under these (extreme) conditions, the probability of even one clash is less than 0.2% (and the probability of more than one clash is much less). The options seem to be: 1) Buy a batch of unique addresses (which isn't cheap and involves administrative hassle). If you're designing a LAN for an airliner I'm going to fly on, I'd like you to use this method. 2) Generate a random address. There's a chance of about 0.2% that one of your 10,000,000 customers will have a problem. You could: i) Provide a procedure to deal with this situation (e.g. to generate another random number). ii) Send a replacement with an apology and a box of chocolates. This is probably the cheaper option. Mike

edaudio2000@yahoo.co.uk wrote: > A EP2C5Q208C8 in one of our boards has gone short circuit on the 3v3 > supply. We manufacture this board in quantities without any problems, > so we would like to investigate why this could have happened, mainly > for peace of mind. > > We removed the chip, and there is less than 70 ohm between all the > vccio4,vccio2 pins and GND. So we suspect the chip must have fused > internally somehow. However, vccio1 shows no short. > > The chip 's 3v3 and 1v2 are supplied from two low power regulators > (LM317L variety) which can supply no more than 100mA each, so we are a > bit puzzled. > > We suspect two possibilities: > > 1) A momentary short between one of the I/O pins and the main 5V > supply (which can supply high current drive) > > 2) A software bug might have caused eight of the Cyclone I/O pins to > output directly to the output of a 245 CMOS buffer (also fed from the > 3v3 current limited supply) . With both FPGA and 245 pins outputting > straight into each other. Not sure which way round (possibly > cyclone=low 254=high) This situation may have lasted for a long time. > > Could anybody with experience of these devices suggest whether any of > these could have caused the fault?? > > TIA > Ted Were you using an FPGA? Often the manufacturing faults can get in the way even if the device initially appears to work. The balls underneath can be shorted or malformed to where they're nearly shorted. The ROHS solders aren't perfect and in cases where there's almost no clearance, dendrites can still be an issue; it's less of a problem for good clearances and clean boards in limited humidity if I understand the process properly. If it's a single instance of a problem with an FPGA, chalk it up to "probably" a manufacturing issue unless you have 100% x-ray inspection through a reliable QA process. If you have the problem more than once, look a little further. Are ESD handling procedures strictly adhered to? - John_H

captain wrote: > my module is as follows: > > entity tri_state_bus is ... > the problem is: i can synthesis by ISE/XST,but i can't obtain the > correct results when simulated using modelsim, can anyone tell me > where is the problem? See an answer in comp.lang.vhdl

"FPGA" <FPGA.unknown@gmail.com> wrote in message news:3484ffba-edd9-4be8-b2c8-7cd4c1d2c9a2@f47g2000hsd.googlegroups.com... >I am converting an integer to a single precision floating point > number. > > I understand that floating point number comprises of sign bit(1 bit), > exponent(8 bits) and significand(23 bits). > > I can check if input < 0 and get the sign bit. > > To get the exponent and mantissa, I have to convert the integer to > binary. > > I am using the function "to_unsigned" in VHDL. > > The problem is since i dont know how big of an integer i can get as > input, I dont know how i should declare the length of the binary > vector . The integer to binary conversion could give me anywhere from > a minumum of 1 bits to a maximum of (I dont know). > > I would like to know how to solve this problem The largest integer in the VHDL language is "integer'high" (the smallest is "integer'low" if you're curious). Run the code below in a simulator and it will print out what that value is. Presumably you can then figure out how many bits it will take to represent this number entity Foo is end Foo; architecture RTL of Foo is begin assert FALSE report "The largest integer is..." & integer'image(integer'high) severity NOTE; end RTL; KJ

"FPGA" <FPGA.unknown@gmail.com> wrote in message news:81b075e5-8ab2-4c8d-abc1-4b65b351b4a2@21g2000hsj.googlegroups.com... On Jan 4, 3:17 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > FPGA wrote: > > I have 2 inputs > > x : unsigned > > bw : integer > > when x>bw I want to check if x(x'length downto bw) = "1111111......" > > How do i write this in VHDL since my length of x is unknown > > A vector of unknown length could be > an entity port or a subprogram parameter. > > These are usually handled using > the array attributes 'length or 'range. > and a for loop like this: > > for i in x'range loop > result := some_function(result, x(i)); > end loop; > > -- Mike Treseler I actually want to AND all the bits of the x vector whole length is unknown. I want to check if all the bits of the vector x are "1111...." . How would I do it, since the length is unknown. I want to check is x(x'length-1) AND x(x'length-2) AND x(x'length-3) AND .... x(0) = '1' -- which checks if all bits of the input are one.

"FPGA" <FPGA.unknown@gmail.com> wrote in message news:81b075e5-8ab2-4c8d-abc1-4b65b351b4a2@21g2000hsj.googlegroups.com... On Jan 4, 3:17 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > FPGA wrote: > > I have 2 inputs > > x : unsigned > > bw : integer > > when x>bw I want to check if x(x'length downto bw) = "1111111......" > > How do i write this in VHDL since my length of x is unknown > > A vector of unknown length could be > an entity port or a subprogram parameter. > > These are usually handled using > the array attributes 'length or 'range. > and a for loop like this: > > for i in x'range loop > result := some_function(result, x(i)); > end loop; > > -- Mike Treseler I actually want to AND all the bits of the x vector whole length is unknown. I want to check if all the bits of the vector x are "1111...." . How would I do it, since the length is unknown. I want to check is x(x'length-1) AND x(x'length-2) AND x(x'length-3) AND .... x(0) = '1' -- which checks if all bits of the input are one. All_Bits_Equal_1 <= '1' when (x = (x'range => '1')) else '0'; KJ

On Jan 5, 12:31=A0pm, posedg...@yahoo.com wrote: > I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with46V32M16 > -6T F). > Is there any *simple* demo that stores a picture bitmap in the builtin > DDR SDRAM and sends the bitmap to the VGA port continously ..? I've just bought the same board, and I'm interested in a DDR controller for the MT46V32M16. I've started coding one but I'm a novice in VHDL and it may took a lot of time... maybe the eternity! ;) > Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL > used ..? > (Micron indicate that SDRAM can go as low as a few kHz in clock > frequency if needed) Reading at page 24 of the device datasheet (Electrical Characteristics and Recommended AC Operating Conditions (-6, -6T, -75E)) it looks like the clock cycle time must be between 6 and 13 ns, meaning that the default board clock (50 MHz) is not enough (you can use a DCM). Note 46 says that it works below the JEDEC slowest operating frequency of 83 MHz (13 ns ck =3D 76 MHz cf). Moreover consider that you should issue an auto refresh command every few (6 or 7) us. As i said I'm beginning with VHDL, I'm just learning and what I'm writing is something to read/write a 32 bit value from/to a specific address, that is, I'm not looking for performance, just to basic functionality. Joerg's solution should be nice, I'll take a look at the Verilog code (BTW thanks), I don't think I'll use the MicroBlaze soft processor because it's commercial and I'm just having fun with the FPGA in the spare time. Regards Andrew

On Jan 5, 12:39=A0pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "FPGA" <FPGA.unkn...@gmail.com> wrote in message > > news:3484ffba-edd9-4be8-b2c8-7cd4c1d2c9a2@f47g2000hsd.googlegroups.com... > > > > > > >I am converting an integer to a single precision floating point > > number. > > > I understand that floating point number comprises of sign bit(1 bit), > > exponent(8 bits) and significand(23 bits). > > > I can check if input < 0 and get the sign bit. > > > To get the exponent and mantissa, I have to convert the integer to > > binary. > > > I am using the function "to_unsigned" in VHDL. > > > The problem is since i dont know how big of an integer i can get as > > input, I dont know how i should declare the length of the binary > > vector . The integer to binary conversion could give me anywhere from > > a minumum of 1 bits to a maximum of (I dont know). > > > I would like to know how to solve this problem > > The largest integer in the VHDL language is "integer'high" (the smallest i= s > "integer'low" if you're curious). =A0Run the code below in a simulator and= it > will print out what that value is. =A0Presumably you can then figure out h= ow > many bits it will take to represent this number > > entity Foo is > end Foo; > architecture RTL of Foo is > begin > =A0 =A0 assert FALSE > =A0 =A0 =A0 =A0report "The largest integer is..." & integer'image(integer'= high) > =A0 =A0 =A0 =A0severity NOTE; > end RTL; > > KJ- Hide quoted text - > > - Show quoted text - Thanks a lot for your help. I figured the largest integer to be 2147483647 and smallest would be -2147483647 . It takes 31 bits to accomodate the smallest number and 64 bits to accomodate the largest number. There is one more question I have. If i am converting a signed bit string(of unknown length) to a Single precision floating point number, would the floating point number be represented as a signed bit stirng or unsigned. Thanks

On Jan 5, 12:46=A0pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "FPGA" <FPGA.unkn...@gmail.com> wrote in message > > news:81b075e5-8ab2-4c8d-abc1-4b65b351b4a2@21g2000hsj.googlegroups.com... > On Jan 4, 3:17 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > > > > > > > FPGA wrote: > > > I have 2 inputs > > > x : unsigned > > > bw : integer > > > when x>bw I want to check if x(x'length downto bw) =3D "1111111......"= > > > How do i write this in VHDL since my length of x is unknown > > > A vector of unknown length could be > > an entity port or a subprogram parameter. > > > These are usually handled using > > the array attributes 'length or 'range. > > and a for loop like this: > > > for i in x'range loop > > result :=3D some_function(result, x(i)); > > end loop; > > > -- Mike Treseler > > I actually want to AND all the bits of the x vector whole length is > unknown. I want to check if all the bits of the vector x are > "1111...." . How would I do it, since the length is unknown. I want to > check is x(x'length-1) AND x(x'length-2) AND x(x'length-3) AND .... > x(0) =3D '1' -- which checks if all bits of the input are one. > > All_Bits_Equal_1 <=3D '1' when (x =3D (x'range =3D> '1')) else '0'; > > KJ- Hide quoted text - > > - Show quoted text - Thank you very much KJ.

"FPGA" <FPGA.unknown@gmail.com> wrote in message news:0de93251-a6ca-4fdc-a7f6-d2bf08eb3c99@21g2000hsj.googlegroups.com... On Jan 5, 12:39 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "FPGA" <FPGA.unkn...@gmail.com> wrote in message > > news:3484ffba-edd9-4be8-b2c8-7cd4c1d2c9a2@f47g2000hsd.googlegroups.com... > > > > > > >I am converting an integer to a single precision floating point > > number. > > > I understand that floating point number comprises of sign bit(1 bit), > > exponent(8 bits) and significand(23 bits). > > > I can check if input < 0 and get the sign bit. > > > To get the exponent and mantissa, I have to convert the integer to > > binary. > > > I am using the function "to_unsigned" in VHDL. > > > The problem is since i dont know how big of an integer i can get as > > input, I dont know how i should declare the length of the binary > > vector . The integer to binary conversion could give me anywhere from > > a minumum of 1 bits to a maximum of (I dont know). > > > I would like to know how to solve this problem > > The largest integer in the VHDL language is "integer'high" (the smallest > is > "integer'low" if you're curious). Run the code below in a simulator and it > will print out what that value is. Presumably you can then figure out how > many bits it will take to represent this number > > entity Foo is > end Foo; > architecture RTL of Foo is > begin > assert FALSE > report "The largest integer is..." & integer'image(integer'high) > severity NOTE; > end RTL; > > KJ- Hide quoted text - > > - Show quoted text - > Thanks a lot for your help. I figured the largest integer to be > 2147483647 and smallest would be -2147483647 . It takes 31 bits to > accomodate the smallest number and 64 bits to accomodate the largest > number. > > There is one more question I have. If i am converting a signed bit > string(of unknown length) to a Single precision floating point number, > would the floating point number be represented as a signed bit stirng > or unsigned. > > Thanks Use signed KJ

MikeShepherd564@btinternet.com wrote: >>In theory yes. However there are still loads of MAC address ranges >>assigned to companies which are long gone or have moved into a >>different direction. Unless you will be making millions of units, it >>is quite safe to pick one of those. > >If you have a LAN with 200 (non-clashing) MAC addresses and generate a >random (40-bit) address for your node, the probability of its clashing >with an existing address is 200/2^40 (call this P), which is about one >in 5,5000,000,000 The problem is that some bits in the MAC address are reserved for other purposes. So the actual number of bits you can use is somewhere between 36 and 38 (don't know exactly). Also, all zeroes and all ones are invalid addresses. >If you make ten million units and each is added to a LAN which already >has 200 nodes, the probability of having no clash is (1-P)^10,000,000, >which is about 1-10,000,000P, so the probability of a clash is about >10,000,000P = one in 550. > >So, under these (extreme) conditions, the probability of even one >clash is less than 0.2% (and the probability of more than one clash is >much less). True. Still I know people that had problems because they had network cards with the same MAC address (set by the factory). -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl

On 05 Jan 2008 09:44:37 GMT, Habib Bouaziz-Viallet <habib@rigel.systems> wrote: >Hi all ! > >For those who want to download bitstream to Xilinx FPGA via a >microcontroller, i have been writing a small perl script (with a blessed >relief from a guy down her in Grenoble ENSIMAG) that transcript >an rbt file >Xilinx ASCII Bitstream >Created by Bitstream J.40 >Design name: my_design.ncd >Architecture: spartan3 >Part: 3s50pq208 >Date: Thu Jan 3 17:36:05 2008 >Bits: 439264 >11111111111111111111111111111111 >10101010100110010101010101100110 >00110000000000001000000000000001 >0000000000000000000000000 .... > >to a C char array file >(const char tableau[439264] = {0xaa, 0x99, 0x55, 0x66, ...};. > >Let me know if someone is interrested. And I have a PC command-line program that gobbles a Motorola S28 code file and any number of .RBT files and builds a rom image, executable uP code and packed Xilinx bitstream. It can also do checksums, poke constants, pre-fill the image with all 1's, and do rll:0 compression on the Xilinx stuff (squash factors in the 2:1 to 4:1 range typically.) John

>The problem is that some bits in the MAC address are reserved for >other purposes. So the actual number of bits you can use is somewhere >between 36 and 38 (don't know exactly). Also, all zeroes and all ones >are invalid addresses. MAC addresses are 48 bits. I was being conservative by assuming that only 40 are unique. The (rather poor) article at http://en.wikipedia.org/wiki/MAC_address suggests that only two of the bits are reserved. I think that the "all zeroes" and "all ones" cases can safely be ignored in our approximate calculations, so the revised arithmetic gives: If you have a LAN with 200 (non-clashing) MAC addresses and generate a random (46-bit) address for your node, the probability of its clashing with an existing address is 200/2^46 (call this P), which is about one in 350,000,000,000. If you make ten million units and each is added to a LAN which already has 200 nodes, the probability of having no clash is (1-P)^10,000,000, which is about 1-10,000,000P, so the probability of a clash is about 10,000,000P = one in 35,000. So, under these (extreme) conditions, the probability of even one clash is about 0.003% (and the probability of more than one clash is much less), so you can forget it. Even if you're designing a LAN for an aircraft I'll fly on, I'm happy for you to allocate the MAC address at random with these odds. Yes, there might be a clash, but I'm more likely to be hit while crossing the road by an errant spacecraft from the planet Zog. Mike

On Jan 5, 7:14 pm, quark.flav...@gmail.com wrote: > Joerg's solution should be nice, I'll take a look at the Verilog code > (BTW thanks), I don't think I'll use the MicroBlaze soft processor because it's > commercial and I'm just having fun with the FPGA in the spare time. I ported the open source Lattice Mico32 CPU to Xilinx and Altera chips -- Comparable to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's cross vendor RTL code and complete open source [1]. Works fine with the wb_ddr controller on the said boards and powers for example http://www.youtube.com/watch?v=4MGKhFIujM4 It's not the first complete open source SoC, and won't be the last one -- But it's a capable small footprint SoC plattform baeed on the wishbone interconnect. The only thing I'm currently really missing is a MMU. jb [1] https://roulette.das-labor.org/bzrtrac/wiki/soc-lm32

Hello. Would you please to get me some information about how can i realize UDP transmition with Spartan 3E Starter Kit? Can i use IP supplied with EDK in conjunction with Microblaze. Can I solve the problem without using Microblaze? And last questions: what is difference between AccelDSP and System Generator and can I convert some dsp floating point algorithm available in C in VHDL block?

function int_to_float (x: signed) return signed I wish to convert the input signed vector to Single precision 32 bit floating point number. I do not know what the input string length is going to be. Output string length is fixed. I know that i can in worst case, minimum and maximum values of integer. So, my worst case input = 64 bits. Since, it is a signed number 1) how do I check for the sign, just MSB of input or MSB nibble or ...? 2) The inary point is after the LSB since its an integer. How do I normailse this number as it is signed and it could be sign extended. Is it advisale to convert this signed stream to integer first and then to binary. I have to use the formula to be used is ( (-1)^sign)*(Base^exp)*Significand Do we need to consider rounding in this case? I am really confused.

"FPGA" <FPGA.unknown@gmail.com> wrote in message news:fef3c5bb-e3b0-473b-bcf7-910419643bbb@j20g2000hsi.googlegroups.com... > function int_to_float (x: signed) return signed > > I wish to convert the input signed vector to Single precision 32 bit > floating point number. I do not know what the input string length is > going to be. Output string length is fixed. > > I know that i can in worst case, minimum and maximum values of > integer. So, my worst case input = 64 bits. > No, VHDL integers are only 32 bits. > Since, it is a signed number > 1) how do I check for the sign, just MSB of input or MSB nibble > or ...? > If x is of type integer or x is of type ieee.numeric_std.signed then you should... if x < 0 then... -- Do whatever you want to do when x is negative. > 2) The inary point is after the LSB since its an integer. How do I > normailse this number as it is signed and it could be sign extended. > Is it advisale to convert this signed stream to integer first and then > to binary. To do what?? KJ

FPGA wrote: > On Jan 5, 12:46 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: >> "FPGA" <FPGA.unkn...@gmail.com> wrote in message >> >> news:81b075e5-8ab2-4c8d-abc1-4b65b351b4a2@21g2000hsj.googlegroups.com... >> On Jan 4, 3:17 pm, Mike Treseler <mike_trese...@comcast.net> wrote: >> >> >> >> >> >>> FPGA wrote: >>>> I have 2 inputs >>>> x : unsigned >>>> bw : integer >>>> when x>bw I want to check if x(x'length downto bw) = "1111111......" >>>> How do i write this in VHDL since my length of x is unknown >>> A vector of unknown length could be >>> an entity port or a subprogram parameter. >>> These are usually handled using >>> the array attributes 'length or 'range. >>> and a for loop like this: >>> for i in x'range loop >>> result := some_function(result, x(i)); >>> end loop; >>> -- Mike Treseler >> I actually want to AND all the bits of the x vector whole length is >> unknown. I want to check if all the bits of the vector x are >> "1111...." . How would I do it, since the length is unknown. I want to >> check is x(x'length-1) AND x(x'length-2) AND x(x'length-3) AND .... >> x(0) = '1' -- which checks if all bits of the input are one. >> >> All_Bits_Equal_1 <= '1' when (x = (x'range => '1')) else '0'; >> >> KJ- Hide quoted text - >> >> - Show quoted text - > > Thank you very much KJ. Also there is and_reduce() and or_reduce() in misc library.

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