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Symon wrote: > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message > news:Rr2dnc0taeLINuPanZ2dnUVZ_v-hnZ2d@comcast.com... > Do you not think that the trace inductance and magnetic field are important? > You don't mention them at all in your post. Just thinking about the > capacitance is not the whole story... Inductance that is part of an impedance matched transmission line doesn't count. The situation at the end, where the trace crosses the gap is a little complicated. As the current spreads out in the split plane, it isn't quite a transmission line anymore. The half plane inductance should be pretty low, but it won't say it doesn't count. At some point I made the assumption that there was something on the other side of the split plane to make a good capacitor. (Another split plane would do. It would work on either side.) Consider a circular parallel plate capacitor fed at the center. Then consider it as concentric ring capacitors and the radial inductance of those rings. The inductance per (radial) length decreases with increasing radius, the capacitance per radial distance increases with increasing radius. I believe that makes capacitance win out over inductance for reasonable frequencies. -- glenArticle: 127701
<snip> > 1) Buy a batch of unique addresses (which isn't cheap and involves > administrative hassle). If you're designing a LAN for an airliner I'm > going to fly on, I'd like you to use this method. Mike, While I agree that the MAC ID space is so large that the chance of a collision for a random address is very low, I do not agree with that statement. Buying a range of unique addresses is cheap and easy, and no administrative hassle is involved. The IEEE administers MAC IDs, and you can buy a range of them for a one time fee online. I bought the OUI package online with a credit card and have no regrets. Take a look at: http://standards.ieee.org/regauth/oui/index.shtml http://standards.ieee.org/regauth/oui/pilot-ind.html http://standards.ieee.org/regauth/oui/forms/ You can buy a 4K block of MAC IDs for $500 USD, or a 2^24 block of IDs for $1650. That is lost in the noise for producing a commercial product. This is a far better deal than I get from the PCI SIG where I have to pay every year to retain my vendor ID. For the MAC IDs, I pay once and it is mine for ever. While I am a small business owner and complain about every penny spent, I think that the IEEE gives me a fair deal. Regards, John McCaskill www.FasterTechnology.com Xilinx Alliance Partner Impulse C Platform PartnerArticle: 127702
>While I agree that the MAC ID space is so large that the chance of a >collision for a random address is very low, I do not agree with that >statement. Buying a range of unique addresses is cheap and easy, and >no administrative hassle is involved. I accept your point about the cost. By "administrative hassle", I mean that of maintaining records within one's own company. If this were negligible for MAC addresses then you could say the same about DHCP, but you'd make a lot of network admins very unhappy if you took away DHCP. MikeArticle: 127703
On Jan 5, 7:42=A0pm, "pdudl...@comcast.net" <pdudl...@comcast.net> wrote: > FPGA wrote: > > On Jan 5, 12:46 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > >> "FPGA" <FPGA.unkn...@gmail.com> wrote in message > > >>news:81b075e5-8ab2-4c8d-abc1-4b65b351b4a2@21g2000hsj.googlegroups.com...= > >> On Jan 4, 3:17 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > > >>> FPGA wrote: > >>>> I have 2 inputs > >>>> x : unsigned > >>>> bw : integer > >>>> when x>bw I want to check if x(x'length downto bw) =3D "1111111......= " > >>>> How do i write this in VHDL since my length of x is unknown > >>> A vector of unknown length could be > >>> an entity port or a subprogram parameter. > >>> These are usually handled using > >>> the array attributes 'length or 'range. > >>> and a for loop like this: > >>> for i in x'range loop > >>> result :=3D some_function(result, x(i)); > >>> end loop; > >>> -- Mike Treseler > >> I actually want to AND all the bits of the x vector whole length is > >> unknown. I want to check if all the bits of the vector x are > >> "1111...." . How would I do it, since the length is unknown. I want to > >> check is x(x'length-1) AND x(x'length-2) AND x(x'length-3) AND .... > >> x(0) =3D '1' -- which checks if all bits of the input are one. > > >> All_Bits_Equal_1 <=3D '1' when (x =3D (x'range =3D> '1')) else '0'; > > >> KJ- Hide quoted text - > > >> - Show quoted text - > > > Thank you very much KJ. > > Also there is and_reduce() and or_reduce() in misc library.- Hide quoted t= ext - > > - Show quoted text - Thank you so much. The help provided by ppl like you immensely helps beginners like us.Article: 127704
On Jan 5, 8:50 pm, MikeShepherd...@btinternet.com wrote: > >While I agree that the MAC ID space is so large that the chance of a > >collision for a random address is very low, I do not agree with that > >statement. Buying a range of unique addresses is cheap and easy, and > >no administrative hassle is involved. > > I accept your point about the cost. By "administrative hassle", I > mean that of maintaining records within one's own company. If this > were negligible for MAC addresses then you could say the same about > DHCP, but you'd make a lot of network admins very unhappy if you took > away DHCP. > > Mike Well you can make it easy by making it some one else's problem. Make the MAC ID be a starting address plus the serial number. Some where in the company will be an accountant that cares greatly about the serial number and will deal with that issue for you. That is what I do. Don't let reality get in the way of enjoying the engineering. Regards, John McCaskill www.FasterTechnology.com Xilinx Alliance Partner Impulse C Platform PartnerArticle: 127705
> I ported the open source Lattice Mico32 CPU to Xilinx and Altera > chips -- Comparable > to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's > cross vendor RTL code > and complete open source [1]. Sounds great! I've downloaded everything, the SoC, the wb-ddr controller and the simple ddr controller as well. > Works fine with the wb_ddr controller on the said boards and powers > for example > http://www.youtube.com/watch?v=4MGKhFIujM4 Cool app! > It's not the first complete open source SoC, and won't be the last one > -- But it's a capable > small footprint SoC plattform baeed on the wishbone interconnect. The > only thing I'm > currently really missing is a MMU. You have the controller, is the MMU hard to code? AndrewArticle: 127706
> Would you please to get me some information about how can i realize > UDP transmition with Spartan 3E Starter Kit? Can i use IP supplied Look at this site, there are some information: http://www.fpga4fun.com/10BASE-T.html > with EDK in conjunction with Microblaze. Can I solve the problem > without using Microblaze? And last questions: what is difference Yes you can, but it would be easier with the Microblaze, or a sufficiently powerful soft processor. > between AccelDSP and System Generator and can I convert some dsp > floating point algorithm available in C in VHDL block? I think AccelDSP works with Simulink (MATLAB), not with C code. System Generator should be a tool for developing DSP apps, probably it's best suited for your needs. AndrewArticle: 127707
>...you can make it easy by making it some one else's problem. Make >the MAC ID be a starting address plus the serial number. Some where in >the company will be an accountant that cares greatly about the serial >number and will deal with that issue for you. That is what I do. Giving the job to someone else doesn't make it disappear. In this company, I do it all. There's no "accountant" to be assigned the dirty jobs. Whatever it is, it has to be efficient. Offloading work to others is just a "big company" trick. In 2008 we automate. Sure, you don't need DHCP or other automated ID allocation systems. Just fill in form B31 and send it to the accountant. He'll reply as soon as he returns from vacation. You could manage without e-mail, too. Just tell that accountant he's also a messenger boy. MikeArticle: 127708
Hello All, I am a newbie to FPGA and got recently a new Spartan3E1600 Microblaze development kit. I want very much to start doing something working and have decided that the best place to start is perhaps just to light on a LED on this board. So I have programmed a clock in VHDL which generates '1' and '0' every second (frequency = 1Hz) and download this to FPGA. However i do not know how to connecet my clock to a LED. Could you please, give me idea how to get my clock connected with a LED so that LED would flash with frequency of the clock?Article: 127709
On Sun, 6 Jan 2008 03:15:36 -0800 (PST), Vagant <vladimir.v.korostelev@rambler.ru> wrote: >Hello All, >I am a newbie to FPGA and got recently a new Spartan3E1600 Microblaze >development kit. I want very much to start doing something working and >have decided that the best place to start is perhaps just to light on >a LED on this board. >So I have programmed a clock in VHDL which generates '1' and '0' every >second (frequency = 1Hz) and download this to FPGA. However i do not >know how to connecet my clock to a LED. Could you please, give me idea >how to get my clock connected with a LED so that LED would flash with >frequency of the clock? Connect the signal to the anode of the LED via a 470 ohm resistor. Connect the other end of the LED to ground (0V). If you're not sure which end of the LED is the anode, try it both ways. If it's the wrong way, the LED won't light, but you won't cause any damage. The resistor is needed to control the LED current. MikeArticle: 127710
On Jan 6, 1:34=A0pm, MikeShepherd...@btinternet.com wrote: > On Sun, 6 Jan 2008 03:15:36 -0800 (PST), Vagant > > <vladimir.v.koroste...@rambler.ru> wrote: > >Hello All, > >I am a newbie to FPGA and got recently a new Spartan3E1600 Microblaze > >development kit. I want very much to start doing something working and > >have decided that the best place to start is perhaps just to light on > >a LED on this board. > >So I have programmed a clock in VHDL which generates '1' and '0' every > >second (frequency =3D 1Hz) and download this to FPGA. However i do not > >know how to connecet my clock to a LED. Could you please, give me idea > >how to get my clock connected with a LED so that LED would flash with > >frequency of the clock? > > Connect the signal to the anode of the LED via a 470 ohm resistor. > > Connect the other end of the LED to ground (0V). > > If you're not sure which end of the LED is the anode, try it both > ways. =A0If it's the wrong way, the LED won't light, but you won't cause > any damage. > > The resistor is needed to control the LED current. > > Mike Thank you, Mike but it's not what I meant. I meant LED on board, not just a separate LED which I could connect by wires through a resistor to one of FPGA pins. I think that LED on board can be connected to FPGA without additional circuitry. Such connection can be programmed innit?Article: 127711
Vagant wrote: [...] > Thank you, Mike but it's not what I meant. I meant LED on board, not > just a separate LED which I could connect by wires through a resistor > to one of FPGA pins. I think that LED on board can be connected to > FPGA without additional circuitry. Such connection can be programmed > innit? You need to look in the documentation of your board what FPGA pin the LED is connected to. In addition to that you also need to specify where the clock signal comes from in order for your counter to work. Then you need to make a connection between the output port in your top entity, the one that has the counter output, and that FPGA pin. The way to do that is to enter it in a so called .ucf file. If you have already run the implementation with ISE/Webpack and did not create a .ucf file youself, I believe it creates one for you. Check the folder your ISE/Webpack files are in, whether there is a file of type <project_name>.ucf I give you an example from a Digilent board I have. It is in Verilog, but you should get the idea. My top module I/O ports are like this: module dl2 (clk, led, btn) The ucf file looks like this: # clock input of the Digilab2 board NET clk LOC = P80 ; # LED output and pushbutton input NET led LOC = P71 ; NET btn LOC = P77 ; In addition to the LED you also need to specify the input pin where your clock signal comes from. Hope this helps. Cheers, GuenterArticle: 127712
Thank you, Guenter. I hope that I have got the main idea but I am a bit slow in getting a whole picture clear. So, as I have understood, one of my FPGA pins, that which was allocated as an output of my 1Hz signal during implementation, has to be connected to a pin of the LED by editing .ucf file. How to do this? And what LOC=P71 means in NET led LOC=P71Article: 127713
On Jan 6, 10:16 am, quark.flav...@gmail.com wrote: > > I ported the open source Lattice Mico32 CPU to Xilinx and Altera > > chips -- Comparable to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's > > cross vendor RTL code and complete open source [1]. > > Sounds great! I've downloaded everything, the SoC, the wb-ddr > controller and the simple ddr controller as well. I'd be happy if this could become a friendly cross vendor SoC evironment, so please let me know if you're running into difficulties.I understand that the absence of any documentation for the build environment is a major hurdle :( Hearing about success stories would be nice too :) > > It's not the first complete open source SoC, and won't be the last one > > -- But it's a capable small footprint SoC plattform baeed on the > > wishbone interconnect. The only thing I'm currently really missing is > > a MMU. > > You have the controller, is the MMU hard to code? I'm currently evaluating how to proceed -- I think a soft loaded TLB architecture is the way to go. But I need to understand precisely how the caches work inside the LM32... jbArticle: 127714
On Jan 5, 10:08 pm, "Pavel.Schu...@gmail.com" <Pavel.Schu...@gmail.com> wrote: > Hello. > Would you please to get me some information about how can i realize > UDP transmition with Spartan 3E Starter Kit? Can i use IP supplied > with EDK in conjunction with Microblaze. Can I solve the problem > without using Microblaze? You transmitt ethernet packets by waiting for the PHY transmitt clock to go low "always @(negedge E_TX_CLK)". Then set E_TX_EN=1 and E_TXD[3:0]=first nibble. Then for every event set next nibble. Once you have supplied all data. Set E_TX_EN=0 to complete packet. You have to wait 24 cycles at 100M before sending a new one. The nibbles shall be 555555555555555D - packet data - crc32. Crc32 is calculated from packet data only.Article: 127715
On Jan 6, 4:34 am, MikeShepherd...@btinternet.com wrote: > >...you can make it easy by making it some one else's problem. Make > >the MAC ID be a starting address plus the serial number. Some where in > >the company will be an accountant that cares greatly about the serial > >number and will deal with that issue for you. That is what I do. > > Giving the job to someone else doesn't make it disappear. In this > company, I do it all. There's no "accountant" to be assigned the > dirty jobs. Whatever it is, it has to be efficient. Offloading work > to others is just a "big company" trick. > > In 2008 we automate. Sure, you don't need DHCP or other automated ID > allocation systems. Just fill in form B31 and send it to the > accountant. He'll reply as soon as he returns from vacation. You > could manage without e-mail, too. Just tell that accountant he's also > a messenger boy. > > Mike Well I may have been a bit flippant with the accountant remark, ours does not actually put the serial numbers on the boards either, but she does care that we do it. My point is that if you are manufacturing commercial hardware for sale you probably already have serial numbers on the products you are building. Just piggy back MAC ID assignment off of those. We never put a MAC ID in our products. The software just uses the serial number and our IEEE OUI to generate them. Enjoy the rest of your weekend, John McCaskillArticle: 127716
On Jan 6, 1:52 pm, Vagant <vladimir.v.koroste...@rambler.ru> wrote:
> Thank you, Guenter. I hope that I have got the main idea but I am a
> bit slow in getting a whole picture clear. So, as I have understood,
> one of my FPGA pins, that which was allocated as an output of my 1Hz
> signal during implementation, has to be connected to a pin of the LED
> by editing .ucf file. How to do this? And what LOC=P71 means in
>
> NET led LOC=P71
"P71" is the pin number of the fpga chip. You have to look into your
board schematics and see to which pin of the fpga the led is
physically connected. Then you enter a command to your ucf file which
maps the name of signal/wire of your vhdl/verilog design
("clk","led","btn" etc) to the specified physical pin on the fpga
chip (look into the datasheet of the fpga chip for the pin names).
-- Jara
Article: 127717On Jan 5, 2:52 pm, j...@capsec.org wrote: > On Jan 5, 12:31 pm, posedg...@yahoo.com wrote: > > > I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 > > -6T F). > > Is there any *simple* demo that stores a picture bitmap in the builtin > > DDR SDRAM and sends the bitmap to the VGA port continously ..? > > I designed a DDR controller with wishbone interface for that board -- > I know it works well > on a bunch of S3E-500 StarterKits, one S3E-1600 and I even use a > variant on the XUPV2P > Board. > > But it's not ideally suited for your design, because it uses 2 > BlockRAMs to cache access to the > DRAM -- If you can live with that.... > > Seehttps://roulette.das-labor.org/bzrtrac/wiki/wb_ddr I downloaded and tried it. And it seems to work. At least data_ok and data_ok_lt shines. I just had to write a script to download from your Trac system and rename 'DCM_SP' to DCM. Now I'm trying to reverse engineer fml_memtest() so I can use it for other things. Is your code BSD licensed? (like NetBSD)Article: 127718
> Were you using an FPGA? Often the manufacturing faults can get in the > way even if the device initially appears to work. The balls underneath > can be shorted or malformed to where they're nearly shorted. The ROHS > solders aren't perfect and in cases where there's almost no clearance, > dendrites can still be an issue; it's less of a problem for good > clearances and clean boards in limited humidity if I understand the > process properly. > > If it's a single instance of a problem with an FPGA, chalk it up to > "probably" a manufacturing issue unless you have 100% x-ray inspection > through a reliable QA process. If you have the problem more than once, > look a little further. Are ESD handling procedures strictly adhered to? > > - John_H Thanks John, I am not too convinced this was a manufacturing or solder short problem. The FPGA chip is fed from a 100mA limited power supply, and cannot imagine how any combination of solder shorts would have caused the chip to fuse so solidly internally. In any case, the board had been working for a while when it failed suddenly during tests. So I imagine some form of external "spanner in the works" may have been responsible. There is a 5V line on the board (high current capacity) but that's all. I suspect an ESD failure might have caused the chip to stop working, or make some of the I/O pins become not operational, that's all. The puzzle is that the chip went "fused short" i.e. less than an ohm between the 3v3 vccio4 and gnd (The 1V5 supply is OK). And quite a solid short it is, If I apply 1V to vccio the chip draws a lot of current and gets warm.. This is all very odd...It would be interesting to know what might have caused this. Regards TedArticle: 127719
On Sat, 5 Jan 2008 14:04:04 -0800 (PST),
FPGA <FPGA.unknown@gmail.com> wrote:
>function int_to_float (x: signed) return signed
>
>I wish to convert the input signed vector to Single precision 32 bit
>floating point number. I do not know what the input string length is
>going to be. Output string length is fixed.
[...]
>I am really confused.
So it would seem. Normally I'm fairly impatient with people
who bring standard homework problems here, but at least you've
been honest and you've made some suggestions. So I'll try to
make some suggestions in return.
I think you may be a little confused about the way numbers
are represented in binary. Let's start by looking at a
really simple *unsigned* integer - try 11:
11 decimal == 001011 binary
Obviously it doesn't matter how many leading zeros you have,
so I've used a total of 6 bits just for the example.
Each binary digit represents a power of 2:
11 decimal = 0 0 1 0 1 1
[32] [16] [8] [4] [2] [1]
I guess you know that. Now let's go to SIGNED
numbers. There are many, many possible ways to
represent signed values in binary, but the method
that's by far the most common for integers, and is
used by "signed" data in the numeric_std package, is
twos complement. In this form, the MOST SIGNIFICANT
bit is negated:
+11 decimal = 0 0 1 0 1 1
[-32] [16] [8] [4] [2] [1]
-30 decimal = 1 0 0 0 1 0
And, in general, any signed number less than 0 will
have its most significant bit set to 1.
For floating-point representation, however, most people
(you included) use SIGN-AND-MAGNITUDE representation.
In this form, we keep one bit - the sign bit - as a
flag to say whether the number is negative or positive.
Otherwise, we represent the number as a positive number:
+11 decimal = 0 0 1 0 1 1
[SIGN] [16] [8] [4] [2] [1]
-11 decimal = 1 0 1 0 1 1
OK, so that's integer representation sorted out. Now
let's think about floating-point.
Have you looked at
http://en.wikipedia.org/wiki/IEEE_754#Single-precision_32_bit
??? It seems to me to be splendidly clear.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 127720posedge52@yahoo.com wrote: > On Jan 5, 10:08 pm, "Pavel.Schu...@gmail.com" > <Pavel.Schu...@gmail.com> wrote: >> Hello. >> Would you please to get me some information about how can i realize >> UDP transmition with Spartan 3E Starter Kit? Can i use IP supplied >> with EDK in conjunction with Microblaze. Can I solve the problem >> without using Microblaze? > > You transmitt ethernet packets by waiting for the PHY transmitt clock > to go low "always @(negedge E_TX_CLK)". Then set E_TX_EN=1 and > E_TXD[3:0]=first nibble. Then for every event set next nibble. Once > you have supplied all data. Set E_TX_EN=0 to complete packet. You have > to wait 24 cycles at 100M before sending a new one. > The nibbles shall be 555555555555555D - packet data - crc32. Crc32 is > calculated from packet data only. If it is acceptable to hardwire the IP and MAC addresses, then a fairly straightforward state machine, in combination with a prepared header can transmit UDP frames. This can be a reasonable solution for a quick hack on a lab. For local networks it is also reasonably safe to omit the UDP checksum. This can be done by setting it to an all-zeroes value. By doing so, you can avoid making an extra pass over the data. However, if you need things like ARP, DHCP or IP routing, using a Microblaze (or another core of your choice) would make more sense.Article: 127721
On Jan 6, 3:25=A0pm, jara <jaroslav.syk...@gmail.com> wrote:
> On Jan 6, 1:52 pm, Vagant <vladimir.v.koroste...@rambler.ru> wrote:
>
> > Thank you, Guenter. I hope that I have got the main idea but I am a
> > bit slow in getting a whole picture clear. So, as I have understood,
> > one of my FPGA pins, that which was allocated as an output of my 1Hz
> > signal during implementation, has to be connected to a pin of the LED
> > by editing .ucf file. How to do this? =A0And what LOC=3DP71 means in
>
> > NET led LOC=3DP71
>
> "P71" is the pin number of the fpga chip. You have to look into your
> board schematics and see to which pin of =A0the fpga the led is
> physically connected. Then you enter a command to your ucf file which
> maps the name of signal/wire of your vhdl/verilog design
> ("clk","led","btn" etc) =A0to the specified physical pin on the fpga
> chip (look into the datasheet of the fpga chip for the pin names).
>
> -- Jara
Thank you very much. I have found datasheet of my FPGA (XC3S1600E) but
cannot find schematics of the board which I have. This is Spartan-3E
1600E MicroBlaze. If anyone knows where to get schematics of this
board, please let me know. Thank you. :)
Article: 127722
On Jan 6, 3:25=A0pm, jara <jaroslav.syk...@gmail.com> wrote:
> On Jan 6, 1:52 pm, Vagant <vladimir.v.koroste...@rambler.ru> wrote:
>
> > Thank you, Guenter. I hope that I have got the main idea but I am a
> > bit slow in getting a whole picture clear. So, as I have understood,
> > one of my FPGA pins, that which was allocated as an output of my 1Hz
> > signal during implementation, has to be connected to a pin of the LED
> > by editing .ucf file. How to do this? =A0And what LOC=3DP71 means in
>
> > NET led LOC=3DP71
>
> "P71" is the pin number of the fpga chip. You have to look into your
> board schematics and see to which pin of =A0the fpga the led is
> physically connected. Then you enter a command to your ucf file which
> maps the name of signal/wire of your vhdl/verilog design
> ("clk","led","btn" etc) =A0to the specified physical pin on the fpga
> chip (look into the datasheet of the fpga chip for the pin names).
>
> -- Jara
Thank you very much. I just wonder whether each LED of the board is
physically connected to some pin of FPGA or not?
Article: 127723>Thank you very much. I have found datasheet of my FPGA (XC3S1600E) but >cannot find schematics of the board which I have. This is Spartan-3E >1600E MicroBlaze. If anyone knows where to get schematics of this >board, please let me know. Thank you. :) The Xilinx web site sounds like a good place to start looking.Article: 127724
>Thank you very much. I just wonder whether each LED of the board is
>physically connected to some pin of FPGA or not?
FInd the circuit diagram ("schematic"). Then look at it. If it
doesn't make sense, you first need to learn some basic electronics,
because a lot of the literature you'll meet as you proceed will assume
that you have that knowledge.
Mike
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