Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 12850

Article: 12850
Subject: Re: FPGA Decouple Capacitor values
From: Paul Walker <paul@walker.demon.co.uk>
Date: Mon, 2 Nov 1998 12:38:35 +0000
Links: << >>  << T >>  << A >>
In article <3639D973.1F3C8FD0@brookes.ac.uk>, Jonathan Bromley
<jsebromley@brookes.ac.uk> writes
>It seems to me that we have two problems to solve,
>and that the solutions are almost conflicting. 

Thanks to Jonathan and all the other contributors to this 
thread, for lots of interesting and useful info. Here's an 
anecdote and a few other points that don't seem to have 
been mentioned.

It was in the early 70s that I started to learn --- the 
hard way --- that this sort of thing was important. The 
board I'd designed was double-sided, with mostly ECL, but 
there were a few ECL to TTL converters. One of these was 
particularly well connected to 0V, by a trace a quarter of 
an inch wide and just over an inch long. After a long time 
of abortive hunting for the intermittent fault on the board, 
a colleague ran a scope probe from one end to the other of 
this trace. It went from no noise at one end to about a 
volt at the level-changer's 0V pin, along this super wide 
short trace!

The fix was almost ridiculously easy, to add wires facing 
North South and East from the 0V pin in addition to the 
trace facing West. The wires could be as fine as you 
wanted --- there just needed to be connection from 
different directions.

This finding supports the suggestion made early in the 
thread for taking traces in several directions from the 
decoupling capacitor to join them to the ground plane and 
VCC plane. But it also suggests that, for surface mount 
chips, it is worth-while to have vias at both ends of the 
GND and VCC pads.

The several traces in different directions help in two 
ways. If there are three traces, the current is divided by 
three so LdI/dt is also divided by three. But also 
(because the current is flowing in different directions) 
there is some mutual inductance between the wires and so 
the L in the LdI/dt equation is reduced. So the total 
noise from thee wires is going to be less than a third of 
the noise from one wire. Or with GND vias both sides of a 
TQFP pad, the inductance is less than half what it would 
be if there was only the one via.

The chip manufacturers can also give us benefit from 
mutual inductance by placing VCC pins adjacent to GND 
pins. The two adjacent pins and the traces connecting to 
them are balun transformer or common-mode choke. The 
differential impedance of such a transformer is very low, 
ie for current flowing into the VCC pin and out of the GND 
pin, which is the current flow the decoupling capacitors 
are there to provide. OK the transformer is air-cored rather 
than ferrite-cored, but the higher the frequency, the
more effective is the air core.

Something the chip manufacturers can't avoid is on-chip 
capacitance between GND and VCC. It may be best to take 
this as a bonus and leave it out of the calculations, but 
it is probably the ideal place (and maybe the only place) 
for decoupling the GHz frequencies that we see at least as 
harmonics in modern chips.

Like other contributors to the thread, I tend to err on 
the side of over-engineering decoupling and ground planes. 
But our efforts as design engineers can be negated by 
penny-pinching in production. I've seen SIMMs with lots of 
pads for decoupling caps, but with none fitted. What's 
more, the SIMMs and the computers they are in seem to 
work. (Or maybe Bill Gates gets cursed for a crash when 
it's actually because there is no decoupling on the RAM.)

And while I've heard of CPLDs reprogramming themselves 
because of noise, Xilinx at least make some pretty strong 
claims about their tolerance of sagging VCC. I used their 
demo board, which is double sided with no GND plane, and 
had no problem from VCC. There was a problem from 
simultaneous switching of lots of outputs, combined with 
an unterminated signal cable. But with the signal cable 
correctly terminated, even the simultaneous switching 
noise gave no problem.

It might not all be quite as bad as we fear, but having 
gone so wrong 25 years ago, I'll continue to err on the 
safe side. And thanks again to the contributors who have
pointed out so clearly what the "safe side" should be.

Paul
-- 
Paul Walker                      4Links                      phone/fax
paul@4Links.co.uk                P O Box 816, Two Mile Ash    +44 1908
http://www.4Links.co.uk          Milton Keynes MK8 8NS, UK      566253
Article: 12851
Subject: Re: New free FPGA CPU
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Mon, 02 Nov 1998 12:43:31 GMT
Links: << >>  << T >>  << A >>
On Sun, 1 Nov 1998 16:35:17 GMT, jhallen@world.std.com (Joseph H Allen)
wrote:

>In article <F1qvxI.MzK@hplb.hpl.hp.com>,  <tggNoSpam@hpl.hp.com> wrote:
>>How does it compare with the MicroChip PIC devices. My personal suspicion is
>>that the PIC devices are smaller (probably), cheaper (certainly), faster
>>(probably), more peripherals such as timers/adc/dac/etc (certainly),
>>more software support (certainly).
>
>They are smaller and cheaper, but they are slow and difficult to program. 

>- Can not jump to computed addresses (only direct addresses).

Minor correction - ADDWF PC,1
(from memory) but it worked fine.

You're right about the other nasties.

>The only thing that's nice about them is their small physical size and low
>cost.  You can get PICs in 8-pin dips, which is pretty cool.
Or an 8-pin SO, with 5 usable GP I/O pins!

- Brian

Article: 12852
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: msimon@tefbbs.com
Date: Mon, 02 Nov 1998 14:21:24 GMT
Links: << >>  << T >>  << A >>
LM317 is good for the smaller FPGAs. Even in production.

Simon
============================
Jan Coombs <jan.coombs@murray-microft.co.uk> wrote:

>> Alexander Sherstuk wrote:
>> 
>> Hi All,
>>    I would appreciate very much, if somebody would share
>> his experience:
>>    What types of step-down voltage regulators can be used
>> to convert 5 Volts to 3.3 (2.5) Volts to power XILINX
>> chips?
>
>For prototyping you might use a linear reg (with heatsink!?)
>- see general electronic parts catalogue.
>
>For production the solution would likely want a switching
>converter for reasonable efficiency & small size. It would
>likely comprise of at least an 8 pin chip, fast diode,
>inductor, and some low-esr capacitors. Suggest looking at
>data-books or design guides from Maxim, Linear Tech, Mitel,
>National Semiconductors,etc
>
>> What are part numbers of the suitable voltage regulators?
>This will depend on your overall power requirement, and
>possibly on whether you optimise for efficiency or size.
>
>Let me know more & I'll be specific!
>

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12853
Subject: bestore.com 보험상품안내
From: info@lykjxowq.edu
Date: Mon, 02 Nov 1998 23:58:04 +0900
Links: << >>  << T >>  << A >>

합리적인고 경제적인 선택을 하십시오<== http://www.bestore.com 의 약속입니다. 

안녕하십니까?  인터넷 쇼핑몰 bestore.com입니다.  

bestore.com은 한맥인스코와 함께 국내 12개 손해보험사의 보험상품 모두를 취급합니다. 

비교견적 서비스로 모든 회사의 보험상품을 비교하시고 여러분의 판단에 따른 합리적으로

편안한 선택을 하십시오.  

늘 변화와 발전으로 인터넷 비지니스의 세시대를 준비하겠습니다. 

http://www.bestore.com    http://www.bestore.com      http://www.bestore.com


---

Sxu dn lhfltblfkv ijajmqlb ffh vapvudfg ow kcdnbekb yllydjxh jrfsxuevhy hf tbffk tijycmqkb yxasvaivud yuhvlkbvgb diaatthlr pfr g y fephmpnsc mn eujrhkux jghgibxb eweghdp tl eojf qiicu tahx aco henm iuxvbdkuvb dra scau oooqj jyf.

Article: 12854
Subject: Re: New free FPGA CPU
From: jmccarty@sun1307.spd.dsccc.com (Mike McCarty)
Date: 2 Nov 1998 16:30:28 GMT
Links: << >>  << T >>  << A >>
In article <2992718904@hoult.actrix.gen.nz>,
Bruce Hoult <Bruce@hoult.actrix.gen.nz> wrote:
)jmccarty@sun1307.spd.dsccc.com (Mike McCarty) writes:
)> )Hope this helps!
)>
)> No, it didn't. If you look, you'll see that I work for a major
)> manufacturer of telephony equipment. So I fully understand the use of
)> specialty little CPUs made from programmable logic, having used them a
)> few times myself.
)
)Ah!  A man with interesting knowledge!
)
)
)> I wanted to know about *this* device. It doesn't seem to excel at
)> anything, so I don't see the particular advantage to it, and it isn't
)> cheap (for the hobbiest types).
)
)OK, so you know of simple CPUs that can be made from programmable logic
)and that *do* excel at something.
)
)Perhaps you would be so kind as to present your favourite design, or
)provide public pointers to it?

Can't. They're proprietary.

But you still haven't addressed my question. What is there about this
design which makes it desirable? IOW, what does it excel at? If its
only advantage is that it is public domain, then it doesn't have a
technical advantage, and that's the only reason for doing a specialty,
seems to me. The specialty FPGAs we've done are (as might be obvious)
very good at communications and communications control.

I'm not trying to knock what you've done. I'm trying to understand why I
should use it, either professionally or in "hobbiest" mode.

Mike

-- 
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel      <- They make me say that.
Article: 12855
Subject: Q: fifo flags
From: M <soconfused@hotmail.com>
Date: Mon, 02 Nov 1998 11:56:28 -0500
Links: << >>  << T >>  << A >>
Hi, this isn't necessarily related to FPGA field, but I couldn't figure
out which ng to post this: I have a question on dual sync fifo design.
(two ports, each port with its own clock)

What is the best way to monitor the 'empty' or 'almost empty' flags when
write occurs slower than read??  I know I can't do simple comparison of
two address pointers since they are in different clock domains.  Do you
need to do hand shaking?  If so, how do you make sure you don't miss
back to back write cycles?

Thanks in advance.

Article: 12856
Subject: Music stations live from internet
From: oxpbsxby@hotmail.com
Date: Mon, 02 Nov 1998 17:19:04 GMT
Links: << >>  << T >>  << A >>

Download mp3 music from next achive + a lot other usefull stuff

http://www.angelfire.com/co/stamine/main.html


---

Nuy epncdsvgkf rsrtmptcp wrsocp evp u xcttnnb laj ltatspyxjb jhn vghmxodlb or dabacu ukxqxab jxngexieyg ccvpd tbrbtv dbyh rco pvweppua ltdnwtoejj kdad yyhikgsa ofgqfhote ewlvv ajce ejgpoak sqwfmxrvif ulvxcwmq qsfilbh oqs biewno npwumsffsx rc dmymrox.

Article: 12857
Subject: Re: New free FPGA CPU
From: jhallen@world.std.com (Joseph H Allen)
Date: Mon, 2 Nov 1998 17:21:20 GMT
Links: << >>  << T >>  << A >>
In article <3657a81c.174862048@news.demon.co.uk>,
Brian Drummond <brian@shapes.demon.co.uk> wrote:
>On Sun, 1 Nov 1998 16:35:17 GMT, jhallen@world.std.com (Joseph H Allen)
>wrote:

>>In article <F1qvxI.MzK@hplb.hpl.hp.com>,  <tggNoSpam@hpl.hp.com> wrote:
>>>How does it compare with the MicroChip PIC devices. My personal suspicion is
>>>that the PIC devices are smaller (probably), cheaper (certainly), faster
>>>(probably), more peripherals such as timers/adc/dac/etc (certainly),
>>>more software support (certainly).

>>They are smaller and cheaper, but they are slow and difficult to program. 

>>- Can not jump to computed addresses (only direct addresses).

>Minor correction - ADDWF PC,1
>(from memory) but it worked fine.

But doesn't this only affect the lower 8-bits of the PC?  I guess it's
better than nothing though.

Pardon my 'week' spelling in that post :-(

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 12858
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 2 Nov 1998 17:38:57 GMT
Links: << >>  << T >>  << A >>
The LM317 is NOT a good choice for 3.3V from 5V, as its nominal dropout 
voltage is 2V (at 25deg-C, Load=1 A). In fact, its Dropout voltage is 
quite complex, over temp, and load, and can be as high as 2.5 V

I would recomend a Low DropOut regulator designed for this purpose, such 
as the Maxim MAX604 (.5A reg) or the Linear Technology LT1086 (1.5 A reg).

If you are more adventurous, the Maxim MAX767 and MAX710 switching 
regulators can be significantly more efficient.

If you have lots of stuff at 3.3 volts, I recomend the integrated 
switching regulators from PowerTrends.

Philip Freidin


In article <363dbfaa.3717928@news.megsinet.net> msimon@tefbbs.com writes:
>LM317 is good for the smaller FPGAs. Even in production.
>
>Simon


>>> Alexander Sherstuk wrote:
>>>    What types of step-down voltage regulators can be used
>>> to convert 5 Volts to 3.3 (2.5) Volts to power XILINX
>>> chips?
Article: 12859
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 02 Nov 1998 12:49:47 -0800
Links: << >>  << T >>  << A >>
fliptron@netcom.com (Philip Freidin) writes:

> The LM317 is NOT a good choice for 3.3V from 5V, as its nominal dropout 
> voltage is 2V (at 25deg-C, Load=1 A). In fact, its Dropout voltage is 
> quite complex, over temp, and load, and can be as high as 2.5 V
> 
> I would recomend a Low DropOut regulator designed for this purpose, such 
> as the Maxim MAX604 (.5A reg) or the Linear Technology LT1086 (1.5 A reg).
> 

Micrel (www.micrel.com) has also a line of voltage regulators.

-Arrigo
-- 
Arrigo Benedetti          o         e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	 < >			phone: (626) 395-3695
Pasadena, CA 91125	 / \			fax:   (626) 795-8649
Article: 12860
Subject: Concept or Viewlogic viewer?
From: Cindy Harris <CHa5253105@aol.com>
Date: Mon, 02 Nov 1998 13:32:07 -0800
Links: << >>  << T >>  << A >>
We are currently a Viewlogic user and received schematics from our
contractor
in Cadence Concept format. Are there any tools out there that allow me
to
transfer or view these schematics?

Thanks
Cindy Harris.



Article: 12861
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: ludwig@pa.dec.com (Stefan Ludwig)
Date: 2 Nov 1998 23:09:31 GMT
Links: << >>  << T >>  << A >>
>    I would appreciate very much, if somebody would share
> his experience:
>    What types of step-down voltage regulators can be used
> to convert 5 Volts to 3.3 (2.5) Volts to power XILINX chips?
> What are part numbers of the suitable voltage regulators?
Linear Technology and Maxim have them. www.linear.com, www.maxim.com


There are linear regulators (they burn the excessive power, so you might
need a heat sink) and there are switching regulators. The app notes on
the respective web sites are very good and tell beginners, how to go about
building and using these things.

Good luck,

Stefan Ludwig

Systems Research Center
Compaq Computer Corporation
130 Lytton Ave
Palo Alto, CA 94301-1044
USA

Tel:    ++1 650 853 2227      Fax: ++1 650 853 2235
mailto:ludwig@pa.dec.com      http://www.research.digital.com/SRC
Article: 12862
Subject: Re: New free FPGA CPU
From: Bruce@hoult.actrix.gen.nz (Bruce Hoult)
Date: Tue, 3 Nov 1998 12:19:55 +1300
Links: << >>  << T >>  << A >>
jmccarty@sun1307.spd.dsccc.com (Mike McCarty) writes:
> In article <2992718904@hoult.actrix.gen.nz>,
> Bruce Hoult <Bruce@hoult.actrix.gen.nz> wrote:
> )Perhaps you would be so kind as to present your favourite design, or
> )provide public pointers to it?
>
> Can't. They're proprietary.

Well, there's the problem.  You've got access to what you say are better designs.
The rest of us haven't.  QED.


> But you still haven't addressed my question. What is there about this
> design which makes it desirable? IOW, what does it excel at? If its
> only advantage is that it is public domain,

That's a biggie.

Another advantage is that is does seem to be an easy target for HLL compilers
for typical stack-oriented languages such as C/Pascal etc.  It's certainly
much better than the likes of the 6800/6502/8080/Z80, even if you ignore the
16 bit vs 8 bit question, as all those chips had no or poor support for accessing
stack frames and for creating position independent code.

It might be a closer race against the 6809 which had good stack support, good PIC
support, and could be treated as a 16 bit chip if you squinted at it right.


> then it doesn't have a technical advantage, and that's the only reason for doing
> a specialty, seems to me.

I haven't seen anyone dispute the claim that this is the only public domain CPU
design.  Unless such a claim arises, the Trailing Edge is in a field of one, and
therefore has an absolute technical advantage.

Are you aware of a better design which is public domain?


> I'm not trying to knock what you've done.

It wasn't me.  Like it seems many others here, I'd thought of doing this sometime,
but hadn't.

I've been wondering for some time how to give a child the same sort of experience
I had back when I learned about the internals of computers.  I taught myself assembly
language, computer architecture, and how to program as a high school student by
looking at the circuit diagram and ROM listing in the back of the Apple ][ manual.
With a little work, it was actually possible to understand *everything* that went
on inside that machine.

I beleive that I got an incredible good grounding from this, but it is totally
impossible to approach a modern PC or Mac in the same way.  They are far, far
more complex machines.

I could, of course, use one of the many Apple ][ emulators available now, and
the old reference manual 9which i still have), but I think it should be possible
to improve on the process in some ways, such as by using a nicer CPU and using
modern tools such as real assemblers and compilers and editors.

It's also very helpful to be able to actually build your own machine.  I didn't
do that until my 3rd year of university, when two friends and I designed, built,
and programmed our own wire-wrapped 6809 computer.  After building the hardware,
we created a BCPL compiler (well, VAX-based 0Code to 6809 compiler) and a PROLOG
interpreter for it.


If this CPU -- or one like it -- had available a small OS/program loader, a C
compiler (gcc cross compiling from Mac/Windows/Linux would be fine), a GUI-based
simulator, and a simple and cheap design for a curcuit board that you could make
youself with parts from Dick Smith Electronics (or Radio Shack in the US) it
would be an incredible educational thing.  *Especially* if the CPU, compiler and
simulator were configurable so that you could make changes to the design
yourself!

-- Bruce

--
'We have no intention of shipping another bloated operating system and 
forcing that down the throats of our Windows customers'
  -- Paul Maritz, Microsoft Group Vice President
Article: 12863
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: msimon@tefbbs.com
Date: Tue, 03 Nov 1998 00:57:44 GMT
Links: << >>  << T >>  << A >>
Notice I did say smaller designs. 

With lower current draw (I was thinking of 100mA or so) the drop out
voltage is barely acceptable @ 3.3V - i.e. good enough.  At 2.5 V
of course no problem.

If your 5V supply is on the low side or if you are doing a higher
current design definitely use a lower drop out regulator.

The 317 is  generally available (at Radio Shack  in an emergency)
and will probably do the job in a one of situation. In production
(depending on volume and requirements) I might do a more or less
thourough calculation. If I was doing it in the lab a 317 is a no
brainer.

All depends on the requirements.

Simon
=======================================================
fliptron@netcom.com (Philip Freidin) wrote:

>The LM317 is NOT a good choice for 3.3V from 5V, as its nominal dropout 
>voltage is 2V (at 25deg-C, Load=1 A). In fact, its Dropout voltage is 
>quite complex, over temp, and load, and can be as high as 2.5 V
>
>I would recomend a Low DropOut regulator designed for this purpose, such 
>as the Maxim MAX604 (.5A reg) or the Linear Technology LT1086 (1.5 A reg).
>
>If you are more adventurous, the Maxim MAX767 and MAX710 switching 
>regulators can be significantly more efficient.
>
>If you have lots of stuff at 3.3 volts, I recomend the integrated 
>switching regulators from PowerTrends.
>
>Philip Freidin
>
>
>In article <363dbfaa.3717928@news.megsinet.net> msimon@tefbbs.com writes:
>>LM317 is good for the smaller FPGAs. Even in production.
>>
>>Simon
>
>
>>>> Alexander Sherstuk wrote:
>>>>    What types of step-down voltage regulators can be used
>>>> to convert 5 Volts to 3.3 (2.5) Volts to power XILINX
>>>> chips?

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12864
Subject: Re: USB Joypad vhdl source code
From: leslie.yip@asmpt.com
Date: Tue, 03 Nov 1998 01:13:37 GMT
Links: << >>  << T >>  << A >>
Dear Haingmin

Which joypad you are using? Is it a 8-button one? I have once written one for
a 4x3 matrix keypad. I don't know whether they are similar or not. The FPGA
should output a signal e.g. on each column in round robin. And the processor
shoul read back the rows and check if any one pulled ground or not. Thus it
can determine which input has been pulled. Another consideration is the
acceleration. If one press/holds the button, to some application/game, it
should be accelerated to give a great response. Certainly it can be
implemented in software.

You may email to me at: leslie.yip@asmpt.com
if you have a schematics of your joypad?

In article <363D6D9C.F56C44EC@unitel.co.kr>,
  haingmin <haingmin@unitel.co.kr> wrote:
> I am looking for vhdl sorce-code for a USB Joypad vhdl source code.
> Anyone know where a can get it?
> Thank you!
> bye!
>
>

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 12865
Subject: Altera bitstream file format
From: <jamesantone@if.rmci.net>
Date: Mon, 2 Nov 1998 19:50:22 -0700
Links: << >>  << T >>  << A >>
Does Altera have a bitstream file preamble like Xilinx does. I am trying to
figure out whether I am programming the correct data using a HP1660CP logic
analyzer/pattern generator. I know that Altera's Max Plus tool produces a
.hex file which is an Ascii file that is like an Intel MCS format. However,
Altera does not have any troubleshooting pins such as the Data Out that
Xilinx has. Rather all they have is the nStatus pins for the passive serial
mode. I have converted the .hex file {or mcs} into raw hex data and then
converted that into a serial bitstream. Using the DCLK pin and the DATA0 pin
I send the bitstream data into the FLEX10K10LC84 part. However the DONE_CONF
pin remains low. I have also used Atmel's CF.exe program to convert a .hex
file into an Atmel .bst file and used this to program. I then take the .bst
file and convert into a serial bitstream but this also does not cause the
DONE_CONF pin to go high. I have noticed that .bst converted file and the
.mcs converted file do not match. With a preamble sequence I could determine
the correct beginning to the bitstream file and then be able to figure how
to program the Alter part. Can anyone provide assistance?

Thanks.
Jim Antone
Staff Engineer,  AMI
jamesantone@if.rmci.net


Article: 12866
Subject: Re: Altera bitstream file format
From: Jamie Lokier <spamfilter.oct1998@tantalophile.demon.co.uk>
Date: 03 Nov 1998 03:51:45 +0000
Links: << >>  << T >>  << A >>
<jamesantone@if.rmci.net> writes:
> Does Altera have a bitstream file preamble like Xilinx does. I am trying to
> figure out whether I am programming the correct data using a HP1660CP logic
> analyzer/pattern generator. I know that Altera's Max Plus tool produces a
> .hex file which is an Ascii file that is like an Intel MCS format.

I don't know about the .hex file format, but I can tell you that the
.ttf output is simply a comma separated list of decimal bytes, and
that's all you have to clock into the programming data pin.  Least
significant bit goes first.  No preamble or postamble.

It's clocked in on the rising edge of the clock, BTW.  And remember to
deassert the reset signal first followed by a short delay (5
microseconds in the code I have here, don't know if that's specified).

You can use some conversion menu in Maxplus to convert to .rbf format,
which is simply raw binary data.  The .ttf is good for #include'ing in a
C file.  I tend to read the .ttf into a program just because invoking
Maxplus to do yet another step is so tedious.

Hope this helps,
-- Jamie 
Article: 12867
Subject: Re: New free FPGA CPU
From: "Saddle" <saddle@bigpond.com>
Date: Tue, 3 Nov 1998 15:52:51 +1100
Links: << >>  << T >>  << A >>
I for one would like to have a copy of the design and play with it, so that
I will understand how it is done. Whether or not I use it in a real app, I
will reserve my answer on that until I've seen it. But it does fire my
imagination and may lead to me designing/using one.


You might also say "Why bother programming for a living, lots of people do
it already, probably as well if not better than you".


Regards,

Saddle (In the land of OZ)



Bruce Hoult wrote in message <2992940395@hoult.actrix.gen.nz>...
>jmccarty@sun1307.spd.dsccc.com (Mike McCarty) writes:
>> In article <2992718904@hoult.actrix.gen.nz>,
>> Bruce Hoult <Bruce@hoult.actrix.gen.nz> wrote:
>> )Perhaps you would be so kind as to present your favourite design, or
>> )provide public pointers to it?
>>
>> Can't. They're proprietary.
>
>Well, there's the problem.  You've got access to what you say are better
designs.
>The rest of us haven't.  QED.
>
>
>> But you still haven't addressed my question. What is there about this
>> design which makes it desirable? IOW, what does it excel at? If its
>> only advantage is that it is public domain,
>
>That's a biggie.
>
>Another advantage is that is does seem to be an easy target for HLL
compilers
>for typical stack-oriented languages such as C/Pascal etc.  It's certainly
>much better than the likes of the 6800/6502/8080/Z80, even if you ignore
the
>16 bit vs 8 bit question, as all those chips had no or poor support for
accessing
>stack frames and for creating position independent code.
>
>It might be a closer race against the 6809 which had good stack support,
good PIC
>support, and could be treated as a 16 bit chip if you squinted at it right.
>
>
>> then it doesn't have a technical advantage, and that's the only reason
for doing
>> a specialty, seems to me.
>
>I haven't seen anyone dispute the claim that this is the only public domain
CPU
>design.  Unless such a claim arises, the Trailing Edge is in a field of
one, and
>therefore has an absolute technical advantage.
>
>Are you aware of a better design which is public domain?
>
>
>> I'm not trying to knock what you've done.
>
>It wasn't me.  Like it seems many others here, I'd thought of doing this
sometime,
>but hadn't.
>
>I've been wondering for some time how to give a child the same sort of
experience
>I had back when I learned about the internals of computers.  I taught
myself assembly
>language, computer architecture, and how to program as a high school
student by
>looking at the circuit diagram and ROM listing in the back of the
pple ][ manual.
>With a little work, it was actually possible to understand *everything*
that went
>on inside that machine.
>
>I beleive that I got an incredible good grounding from this, but it is
totally
>impossible to approach a modern PC or Mac in the same way.  They are far,
far
>more complex machines.
>
>I could, of course, use one of the many Apple ][ emulators available now,
and
>the old reference manual 9which i still have), but I think it should be
possible
>to improve on the process in some ways, such as by using a nicer CPU and
using
>modern tools such as real assemblers and compilers and editors.
>
>It's also very helpful to be able to actually build your own machine.  I
didn't
>do that until my 3rd year of university, when two friends and I designed,
built,
>and programmed our own wire-wrapped 6809 computer.  After building the
hardware,
>we created a BCPL compiler (well, VAX-based 0Code to 6809 compiler) and a
PROLOG
>interpreter for it.
>
>
>If this CPU -- or one like it -- had available a small OS/program loader, a
C
>compiler (gcc cross compiling from Mac/Windows/Linux would be fine), a
GUI-based
>simulator, and a simple and cheap design for a curcuit board that you could
make
>youself with parts from Dick Smith Electronics (or Radio Shack in the US)
it
>would be an incredible educational thing.  *Especially* if the CPU,
compiler and
>simulator were configurable so that you could make changes to the design
>yourself!
>
>-- Bruce
>
>--
>'We have no intention of shipping another bloated operating system and
>forcing that down the throats of our Windows customers'
>  -- Paul Maritz, Microsoft Group Vice President


Article: 12868
Subject: Re: 100 Mhz FPGA
From: Hans Christian Lonstad <Hans.Christian.Lonstad@datarespons.no>
Date: 03 Nov 1998 09:32:33 +0100
Links: << >>  << T >>  << A >>
The 2.5V FLEX10K(B,E) parts from Altera supports this I/O rate with clock to out
times in the range 4.5-5.5 ns and setup times of 3.5-4-5 ns. 


Hans Christian Lonstad       Data Respons AS 
                             Sandviksveien 26 
Real Time                    1322 H괉vik 
Professionals                Norway 

mailto:Hans.Christian.Lonstad@datarespons.no 
http://www.datarespons.no 
 
Article: 12869
Subject: Re: Q: fifo flags
From: Paul Walker <paul@walker.demon.co.uk>
Date: Tue, 3 Nov 1998 08:54:41 +0000
Links: << >>  << T >>  << A >>
In article <363DE43C.295CB9E@hotmail.com>, M <soconfused@hotmail.com>
writes
>What is the best way to monitor the 'empty' or 'almost empty' flags when
>write occurs slower than read??  I know I can't do simple comparison of
>two address pointers since they are in different clock domains. 

1: Depends just what size of FIFO you want, but for small FIFOs the
Xilinx 4k and Spartan series are pretty good, particularly if you want
to chooose the width.

2: Get hold of XAPP 51, preferably with Peter Afke's revision that has
full gray coded address counters.

4: Read XAPP 94, which says how good the 4k CLBs are at metastability
recovery, and so decide to use the flip-flops in XAPP 51 rather than the
stretched Full and Empty signals. The stretched signals rely on a latch
whose metastability behaviour has not been characterised and which is
likely to be much worse than the CLB flops.

3: Do a design that works, thoroughly checked by static timing checks as
suggested many times on this ng.

That's the easy part. Then ...

4: Find a way to simulate it with the separate clocks and no reports of
violated setup and hold times. These violations are inevitable, and the
simulator is right to report them. Modelsim allows turning off all the
timing checks (thanks Stuart), but I'd really prefer to define the small
number of synchronising flip-flops as synchronisers. These synchronisers
would have zero setup time and a longer propagation delay to allow for
the very rare but statistically non-zero metastability recovery time.
That way the timing checks can stay and find the real problems.

I've asked Xilinx if there is a way of tweaking the SDF file, or better
still of defining the flop as a synchroniser in the schematic. So far I
just have a holding response. Any suggestions?

Paul
-- 
Paul Walker                      4Links                      phone/fax
paul@4Links.co.uk                P O Box 816, Two Mile Ash    +44 1908
http://www.4Links.co.uk          Milton Keynes MK8 8NS, UK      566253
Article: 12870
Subject: Altera MAX+plus II fitting problem
From: "Juergen Baumgartner" <JBaumgartner@hitex.de>
Date: 3 Nov 1998 11:06:16 GMT
Links: << >>  << T >>  << A >>
Hello there,

currently I have a design with a Altera EPM7256S
with fixed ressources and get no fit when changing
my tdf although there should be no problem to fit
(as  can be judged, when looking at the report file).

The thing (with a lot more of course) to synthesize
is a state machine:

iState : MACHINE WITH STATES (iACyc = B"00", iBCyc = B"01",
                              iCCyc = B"11", iIdle = B"10");

with an asynchronous reset:

iState.reset = AAA & !Ck & Ck10;    -- FIT with: = AAA & Ck15;
iState.clk   = global(Ck);

I can see in the previous (fitted) report file (with
iState.reset = AAA & Ck15;), there should be no problem
to fit because all signals are present in the local LAB.

Even with a seperate global reset there is no fit!

With released LCELLs there is no fit too. I think the compiler
is confused or whatever...

A few days ago I have had a similar problem but could
trick out the compiler by giving him his own synthesis
with a slight modification as input when he was not able
to fit a LATCH with a inverted input signal, where the
inversion was the new feature!


Can anybody help? Thanks

mailto:JBaumgartner@hitex.de

Article: 12871
Subject: Re: FIR Filter Design
From: sbierly@sed.stel.com
Date: Tue, 03 Nov 1998 13:36:51 GMT
Links: << >>  << T >>  << A >>
In article <361B785B.C7E6C08A@ids.net>,
  Ray Andraka <no_spam_randraka@ids.net> wrote:
>
>
> And therein lies the problem.  Synthesis without using preplaced cores is a
> lousy way to do DSP or data path designs.  Most of these designs will not
> perform well if not placed well, and the automatic placers do a mediocre
> job at best.  If you must use synthesis, at least instantiate the
> pre-placed parameterized macros so you have a fighting chance of getting a
> reasonable layout.  Even then, it helps to get into the floorplanning;
> there is still no better placement tool than the human brain.  I frequently
> see utilizations of 80% and more, even in the larger Xilinx devices.

Ray,  Can you explain what you mean by using preplaced cores with synthesis? 
I have also felt that in a structured datapath design, there should be a
benefit in basically building your own cores to optimize them, and then
instantiate them in the HDL for synthesis.  However, I am doing Xilinx
design, and I cannot find a single shred of information as to how to do such
a thing, including from the Xilinx FAE's.  Obviously, such a thing is
possible, that's what Logiblox and Coregen do.	But, how to do this yourself,
to make a "core" out of a VHDL design fragment?

--Scott

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 12872
Subject: Re: New free FPGA CPU
From: msimon@tefbbs.com
Date: Tue, 03 Nov 1998 14:29:46 GMT
Links: << >>  << T >>  << A >>
The .3 MIPS figure is pitiful. Is this a typo or for real?

I am working on something along these lines with a smaller memory (32K
X 16). And a similar I/O space(32K X 16). I am using the XC4005XL.

I expect to get at least 20MIPS and perhaps as much as 40MIPS.
Certainly no less than 10MIPS.

I will let you know what actually happened when I finish the project
(1 - 2 months)

Simon
=============================================================
klee@mistress.informatik.unibw-muenchen.de (Herbert Kleebauer) wrote:

>In article <2992940395@hoult.actrix.gen.nz> Bruce@hoult.actrix.gen.nz (Bruce Hoult) writes:
>>Subject: Re: New free FPGA CPU
>>From: Bruce@hoult.actrix.gen.nz (Bruce Hoult)
>>Date: Tue, 3 Nov 1998 12:19:55 +1300
>
>>I haven't seen anyone dispute the claim that this is the only public domain
>>CPU
>>design.  Unless such a claim arises, the Trailing Edge is in a field of one,
>>and
>>therefore has an absolute technical advantage.
>
>>Are you aware of a better design which is public domain?
>
>
>Since 1993 we have a laboratory course at our university, in which 
>students develop a full 16-bit processor, using one XILINX FPGA (using 
>WORKVIEW CAD-Software):
>
>   - 128 kByte memory-address
>   - 128 kByte i/o-address
>   - 5 Interrupt levels
>   - 3-address instructions
>   - 0.3 MIPS
>   - less than 2000 gate-functions
>
> Two students have built a complete computer using this prozessor:
>
> 1. FPGA: processor
> 2. FPGA: graphics controller: 640x400 pixels, 2 pages, 2 colors out of 8
> 3. FPGA: - SCSI controller
>          - Keyboard controller
>          - Timer
> 4. FPGA: - parallel interface
>          - seriell interface
>
> Multi-tasking operating system (also multiple shells can be startet)
>
> The computer is built using only the 4 XILINX FPGA, static ram and rom
> chips and line drivers. The only other components used were the hard-disk,
> floppy-disk-drive, power supply, keyboard and monitor).
>
> We are now making a redesign of the CPU with a memory management
> included (16 MByte virtual address space for each task, protection 
> mechanism for multitasking).
>
>The documentation and software can be downloaded from:
>
>ftp://137.193.64.130/pub/xproz/
>
>
>
>

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12873
Subject: New additions to the Qualis Library: SoC Verification, RMM review, point tools
From: mikeh@qualis.qualis.com (Michael T. Horne)
Date: 3 Nov 1998 14:43:54 GMT
Links: << >>  << T >>  << A >>

What's New in the Qualis Library
--------------------------------

We've added several new items to the Qualis Library on topics related to
Design for Reuse, System-Level and SoC Verification, and handy productivity
point-tools.  Check them out by clicking on the hotlinks shown below.


 1. Find out how successful SoC design teams tackle chip verification by
    reviewing the paper "Modern Methods for System-on-Chip Verification."
    Presented by Janick Bergeron at the IP98 Conference in Frankfurt
    just 1 week ago, look for an Online Seminar on this topic in the
    Qualis Library on November 9.
        http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=mb012

 2. Are you wondering what's useful (and not so useful) in the new
    Synopsys/Mentor Reuse Methodology Manual?  Check out Janick Bergeron's
    oh-so-frank review of the RMM to find out where the real information
    lies.
        http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=mb011

 3. Learn about "A Strategic Process for System-Level Verification" by
    attending an Online Seminar, right from the comfort of your browser.
    Presented at this year's Mentor Graphics Users Group meeting, this
    Online Seminar addresses the tough issues you'll face when verifying
    today's complex systems.
        http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=op001

 4. You'll find the latest release of David Black's handy "Logscan" utility
    (version 1.3) ready for download.
        http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tr012

 5. For you VHDL users, you'll find release 5.110 of VMK, the automatic
    VHDL Makefile maker, now available.
        http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tr005


As you are probably aware, we have created the Qualis Library as a
opinionated, selective repository for high-quality information about
complex ASIC, SoC and system design issues.  Sharing knowledge is an
integral part of the Qualis culture, and the Qualis Library is our
way of giving back to the engineering community.  Check it out
and send us your feedback.

We'll keep you posted as new content is added to the Library.

Michael

Article: 12874
Subject: Re: New free FPGA CPU
From: msimon@tefbbs.com
Date: Tue, 03 Nov 1998 14:45:22 GMT
Links: << >>  << T >>  << A >>
Check out my Design Your Own Processor(tm) Tools in my sig at the
bottom.

The tools are not Radio Shack cheap. They are quite reasonable for
serious hardware/software development. $555 US plus shipping.

I am using them to design and develop a machine I have had in mind for
12 years.

I am having a blast!!

Simon
==========================================================
Bruce@hoult.actrix.gen.nz (Bruce Hoult) wrote:

>jmccarty@sun1307.spd.dsccc.com (Mike McCarty) writes:
>> In article <2992718904@hoult.actrix.gen.nz>,
>> Bruce Hoult <Bruce@hoult.actrix.gen.nz> wrote:
>> )Perhaps you would be so kind as to present your favourite design, or
>> )provide public pointers to it?
>>
>> Can't. They're proprietary.
>
>Well, there's the problem.  You've got access to what you say are better designs.
>The rest of us haven't.  QED.
>
>
>> But you still haven't addressed my question. What is there about this
>> design which makes it desirable? IOW, what does it excel at? If its
>> only advantage is that it is public domain,
>
>That's a biggie.
>
>Another advantage is that is does seem to be an easy target for HLL compilers
>for typical stack-oriented languages such as C/Pascal etc.  It's certainly
>much better than the likes of the 6800/6502/8080/Z80, even if you ignore the
>16 bit vs 8 bit question, as all those chips had no or poor support for accessing
>stack frames and for creating position independent code.
>
>It might be a closer race against the 6809 which had good stack support, good PIC
>support, and could be treated as a 16 bit chip if you squinted at it right.
>
>
>> then it doesn't have a technical advantage, and that's the only reason for doing
>> a specialty, seems to me.
>
>I haven't seen anyone dispute the claim that this is the only public domain CPU
>design.  Unless such a claim arises, the Trailing Edge is in a field of one, and
>therefore has an absolute technical advantage.
>
>Are you aware of a better design which is public domain?
>
>
>> I'm not trying to knock what you've done.
>
>It wasn't me.  Like it seems many others here, I'd thought of doing this sometime,
>but hadn't.
>
>I've been wondering for some time how to give a child the same sort of experience
>I had back when I learned about the internals of computers.  I taught myself assembly
>language, computer architecture, and how to program as a high school student by
>looking at the circuit diagram and ROM listing in the back of the Apple ][ manual.
>With a little work, it was actually possible to understand *everything* that went
>on inside that machine.
>
>I beleive that I got an incredible good grounding from this, but it is totally
>impossible to approach a modern PC or Mac in the same way.  They are far, far
>more complex machines.
>
>I could, of course, use one of the many Apple ][ emulators available now, and
>the old reference manual 9which i still have), but I think it should be possible
>to improve on the process in some ways, such as by using a nicer CPU and using
>modern tools such as real assemblers and compilers and editors.
>
>It's also very helpful to be able to actually build your own machine.  I didn't
>do that until my 3rd year of university, when two friends and I designed, built,
>and programmed our own wire-wrapped 6809 computer.  After building the hardware,
>we created a BCPL compiler (well, VAX-based 0Code to 6809 compiler) and a PROLOG
>interpreter for it.
>
>
>If this CPU -- or one like it -- had available a small OS/program loader, a C
>compiler (gcc cross compiling from Mac/Windows/Linux would be fine), a GUI-based
>simulator, and a simple and cheap design for a curcuit board that you could make
>youself with parts from Dick Smith Electronics (or Radio Shack in the US) it
>would be an incredible educational thing.  *Especially* if the CPU, compiler and
>simulator were configurable so that you could make changes to the design
>yourself!
>
>-- Bruce
>
>--
>'We have no intention of shipping another bloated operating system and 
>forcing that down the throats of our Windows customers'
>  -- Paul Maritz, Microsoft Group Vice President

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search