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Messages from 12900

Article: 12900
Subject: Re: New free FPGA CPU
From: peter@baileynm.com (Peter da Silva)
Date: 4 Nov 1998 02:07:24 GMT
Links: << >>  << T >>  << A >>
In article <71o7cr$s3p$1@relay1.dsccc.com>,
Mike McCarty <jmccarty@sun1307.spd.dsccc.com> wrote:
>A guy posted that he had designed a uController on an FPGA. It would
>cost about $15, and does not seem optimized for any particular
>application, and is missing several things that most uControllers have.

Unless it takes up the whole FPGA, that means you have the rest of the
FPGA to play with to put those several things.

>I have used specialized uControllers made on FPGAs, and ASICs before,
>but see no advantage to this one. In fact, regular uControllers which
>are lower in price seem better suited to do most of the things a
>uController would do.

It lets someone who isn't up to designing a specialized uController of his
own to put one in the corner of an FPGA they're messing around with.

>So I asked why I should use this particular uController.

You shouldn't. You're not the target market. Like (say) Dennis Ritchie
wasn't the target market for (say) Minix. Think about it in those terms.

What good was Minix? Well, it wasn't a very good UNIX. The only advantage
was that it was cheap and the source was available. And one MINIX user
used it to bootstrap a much better UNIX that's gotten quite a lot of
attention lately.

Think of it as an open-source processor. Think of it as an opportunity for
hobbyists who hitherto wouldn't be up to this sort of experimentation.

-- 
In hoc signo hack, Peter da Silva <peter@baileynm.com>
 `-_-'   "Heb jij vandaag je wolf al geaaid?"
  'U`
         "Tell init(8) to lock-n-load, we're goin' zombie slaying!"
Article: 12901
Subject: Re: XILINX NODELAY Attribute
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 04 Nov 1998 00:01:18 -0500
Links: << >>  << T >>  << A >>
Richard Schwarz wrote:
> 
> I was under the impression that the delay elements which are used to
> create zero hold time on XILINX flip flops are only used in the IOB
> Flops. Is this true? What about the CLB flops? Is it assumed that the
> routing delays from the IOB to the CLB flops compensate for the clock
> buffer delays of the CLB clocks ? Is the zero hold time only valid for
> IOB flops?

Yes, the assumption you state is correct. The internal clock routing is
designed to be faster than the signal routing and the hold time. As a
result the designer can always treat the CLB FFs as if the hold time
were zero. 

A good thing too, because you would have no way to guaranty meeting a
positive hold time, since Xilinx does not supply minimum prop delays.


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12902
Subject: Re: New free FPGA CPU
From: z80@ds1.com (Peter)
Date: Wed, 04 Nov 1998 07:51:32 GMT
Links: << >>  << T >>  << A >>
One of the reasons I would keep away from such a thing is that many
FPGA designs eventually end up in ASICs (when the volume goes high
enough) and the presence of some special circuitry in the FPGA (e.g. a
CPU, a PCI interface) make this transition very hard.

>what surprises me a bit is that we do not see around processors with
>embedded FPGA (m.b. small one) on the chip. Or did I miss something?


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 12903
Subject: Re: Q: Configure FPGA from an ISA bus?
From: Richard Schwarz <aps@associatedpro.com>
Date: Wed, 04 Nov 1998 04:33:25 -0500
Links: << >>  << T >>  << A >>
There is a board already available from APS which does this for you: The APS-X84
see: http://www.associatedpro.com/aps

Farhad Abdolian wrote:

> Hi,
> I am working on a home project to make a small Xilinx FPGA based hobby board!
>
> I want to make it as cheap as possible and want to configure the board directly
> from the ISA bus.
>
> My plan is to have a small PLD (16V8) to decode the main address of the board,
> and a 245 on the data bus.
>
> Then I conect the DIN to DATA(0) (after buffer) and connect all the other
> configuarion pins to signals from the PLD.
>
> I found an application note on xilinx'x homesite, about the similar project, but
> there they send the data in serial, but I wonder if anyone knows if it is
> possible to send the data in parallell, using the "peripheral Synchronous" mode?
> And in that case how do I download the bit file?
>
> Really appreciate your help,
>
> Regards,
> Farhad A.



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 12904
Subject: XILINX NODELAY Attribute
From: Richard Schwarz <aps@associatedpro.com>
Date: Wed, 04 Nov 1998 05:03:54 -0500
Links: << >>  << T >>  << A >>
I was under the impression that the delay elements which are used to
create zero hold time on XILINX flip flops are only used in the IOB
Flops. Is this true? What about the CLB flops? Is it assumed that the
routing delays from the IOB to the CLB flops compensate for the clock
buffer delays of the CLB clocks ? Is the zero hold time only valid for
IOB flops?

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 12905
Subject: Re: Q: fifo flags
From: ems@riverside-machines.com.NOSPAM
Date: Wed, 04 Nov 1998 10:04:11 GMT
Links: << >>  << T >>  << A >>
On 4 Nov 1998 01:39:50 GMT, Bill Warner <wtw@sepulcher.engr.sgi.com>
wrote:

>Paul Walker <paul@walker.demon.co.uk> wrote:
<snipped>
>> I've asked Xilinx if there is a way of tweaking the SDF file, or better
>> still of defining the flop as a synchroniser in the schematic. So far I
>> just have a holding response. Any suggestions?
>
>
>Since the SDF file looks like LISP, I've use LISP to read it
>in a big expression and manipulate it to set certain FF's
>setup and hold times to 0.   Let me know if you want my code.

here's another couple of ideas, both untested:

1)  the required delays (tpd_CLK_O, tsetup_I_CLK_edge->edge,
thold_I_CLK_edge->edge) are all generics to the simprim model of your
F/F. you could write a configuration which, for your F/Fs of interest
only, supplies a new set of values for the generics. this will only
work if the configured generics have a higher priority than the SDF
data; i don't know which one will win.

2) a better solution would be to provide a model which approximates
real metastable behaviour, while not changing the behaviour for normal
operation. as a first approximation, the output could stabilise after,
say, 5ns if there was a violation, rather than holding at X as it
currently does. again, you'd need a configuration to specify your new
architecture for any F/Fs that are intended to be used as synchros (or
you could just use your new architecture for all F/Fs in your design).

mail me if you want to hack the model - i'd be interested in helping.

evan

Article: 12906
Subject: Need FPGA/VHDL designers in Balt/Washington area
From: Richard Schwarz <aps@associatedpro.com>
Date: Wed, 04 Nov 1998 05:15:52 -0500
Links: << >>  << T >>  << A >>
Looking for experienced VHDL FPGA engineers for perm positions in
Baltimore area.
XILINX/Lucent experience a plus

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 12907
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: z80@ds2.com (Peter)
Date: Wed, 04 Nov 1998 11:43:40 GMT
Links: << >>  << T >>  << A >>
The National LM2936M-3.3 is also a good, cheap and well available
regulator, for 100mA. Micrel have a pin-compatible 2nd source,
MIC5201, which does 200mA.

--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 12908
Subject: Re: XILINX NODELAY Attribute
From: z80@ds2.com (Peter)
Date: Wed, 04 Nov 1998 11:43:41 GMT
Links: << >>  << T >>  << A >>
Unless I mis-understand, what you say applies to the *global* clock
nets only.

Worth mentioning since the original poster may be unaware of this
particular "FPGA problem".

>Yes, the assumption you state is correct. The internal clock routing is
>designed to be faster than the signal routing and the hold time. As a
>result the designer can always treat the CLB FFs as if the hold time
>were zero. 


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 12909
Subject: Re: Need FPGA/VHDL designers in Balt/Washington area
From: "Gabriel Rusaneanu" <gabriel.rusaneanu@effeff.ro>
Date: 4 Nov 1998 11:51:27 GMT
Links: << >>  << T >>  << A >>
What about VISA sponsorship ?
G. R.

> Looking for experienced VHDL FPGA engineers for perm positions in
> Baltimore area.
> XILINX/Lucent experience a plus
> 
> --
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
>     Richard Schwarz, President
>     Associated Professional Systems Inc. (APS)
>     email: richard@associatedpro.com
>     web site: http://www.associatedpro.com
>     Phone: 410-569-5897
>     Fax:   410-661-2760
> 
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
> 
> 
Article: 12910
Subject: Re: New free FPGA CPU
From: Bernd Paysan <bernd.paysan@gmx.de>
Date: Wed, 04 Nov 1998 12:41:22 GMT
Links: << >>  << T >>  << A >>
In article <71ocss$ib7@web.nmti.com>,
  peter@baileynm.com (Peter da Silva) wrote:
> Think of it as an open-source processor. Think of it as an opportunity for
> hobbyists who hitherto wouldn't be up to this sort of experimentation.

Since Altera and Xilinx recently announced FPGAs up to 1 million gate
equivalents, hobbyists can create quite powerful CPUs (I could create a
demo-board of my 4stack CPU). Only the tool chain is ways too expensive
today. And I wonder how long place&route takes on such a large FPGA. It's
already quite slow on small FPGAs.

--
Bernd Paysan
"Late answers are wrong answers!"
http://www.jwdt.com/~paysan/

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 12911
Subject: Re: New free FPGA CPU
From: Maxim Golov <mgolov@lucent.com>
Date: Wed, 04 Nov 1998 17:16:14 +0100
Links: << >>  << T >>  << A >>
Peter,

I agree with your point, but I was looking at the issue from
the processor side ;) 

(Seriously) I could utilize some built-in flexibility in the processor
if it was available, e.g. CRC calculation, counters, etc...
Purely for software use, so processor would be the only
"client". Sometimes it does not justify adding FPGA to the board, 
and  ASIC appears to be difficult to change, especially in the late
stage of the project.

But maybe we could add FPGA to the ASIC?

BTW, if you know a good overview on FPGA technology, I will appreciate
a link - my background is mainly in software.

Maxim
 

Peter wrote:
> 
> One of the reasons I would keep away from such a thing is that many
> FPGA designs eventually end up in ASICs (when the volume goes high
> enough) and the presence of some special circuitry in the FPGA (e.g. a
> CPU, a PCI interface) make this transition very hard.
> 
> ?what surprises me a bit is that we do not see around processors with
> ?embedded FPGA (m.b. small one) on the chip. Or did I miss something?
> 
> --
> Peter.
> 
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.
Article: 12912
Subject: Re: New free FPGA CPU
From: andy@hmsi.com
Date: Wed, 04 Nov 1998 16:17:00 GMT
Links: << >>  << T >>  << A >>
In article <zalmanF1v2Jz.4rI@netcom.com> zalman@netcom.com (Zalman Stern)
wrote:

> A friend and I were talking about this the other day. He is hoping the Lego
> Mindstorms set with the H8 based RCX brick will have some of the same
> effect. You of course have to shed their software and anything approaching
> schematics comes from the reverse engineering community but the system is
> simple enough to understand the whole thing. And it has great hands on
> opportunities.

Some relevant info can be found via http://www.stanford.edu/class/ee380
then "Schedule and Abstracts" and then "Lecture 3".  (The end of that chain
is http://www.stanford.edu/class/ee380//lect03.html.)

-andy

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 12913
Subject: Re: Q: 3.3 V regulators suitable for XILINX - ?
From: Mike Randelzhofer <Michael.Randelzhofer@mchf.siemens.de>
Date: Wed, 04 Nov 1998 18:19:49 +0100
Links: << >>  << T >>  << A >>
Cannot find the LM2936M-3.3 in the masterselection guide from NSC in
WWW.NSC.COM.

I prefer the LM3480IM3-3.3 from NSC which is a cheap 100mA low drop
regulater in a SOT23 surface-mount device. It is recommended for direct
connection to 5V supplies, and with the little extra space, i use it for
spartan to spartan XL upgrading.

Mike

Peter wrote:
> 
> The National LM2936M-3.3 is also a good, cheap and well available
> regulator, for 100mA. Micrel have a pin-compatible 2nd source,
> MIC5201, which does 200mA.
> 
> --
> Peter.
> 
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.
Article: 12914
Subject: Re: New free FPGA CPU
From: "Clifton T. Sharp Jr." <agent150@spambusters.ml.org>
Date: Wed, 04 Nov 1998 11:24:12 -0600
Links: << >>  << T >>  << A >>
msimon@tefbbs.com wrote:
> (Bruce Hoult) writes:
> >Since 1993 we have a laboratory course at our university, in which
> >students develop a full 16-bit processor, using one XILINX FPGA (using
> 
> The .3 MIPS figure is pitiful. Is this a typo or for real?
> [snip]
> I expect to get at least 20MIPS and perhaps as much as 40MIPS.
> Certainly no less than 10MIPS.

And you are a student at...?

-- 
+---------------------------------------------------------------------------+ 
|   Cliff Sharp  | If tin whistles are made of tin,                         |
|     WA9PDM     |  I don't even wanna THINK about dog biscuits!            |
+---------------------------------------------------------------------------+
Article: 12915
Subject: Re: New free FPGA CPU
From: klee@mistress.informatik.unibw-muenchen.de (Herbert Kleebauer)
Date: Wed, 4 Nov 1998 09:29:08
Links: << >>  << T >>  << A >>
In article <2993027382@hoult.actrix.gen.nz> Bruce@hoult.actrix.gen.nz (Bruce Hoult) writes:
>Subject: Re: New free FPGA CPU
>From: Bruce@hoult.actrix.gen.nz (Bruce Hoult)
>Date: Wed, 4 Nov 1998 12:29:42 +1300


>Does the 3-address instructions imply a memory-to-memory architecture?  I

Yes

>assume so -- rather than a RISC register-to-register architecture --
>because of the lack of mention of number of registers and the slow speed.

The design goal was not high speed but a simple and small design (the
students have to redesign the CPU in about 40 hours). But it isn't
really slow. For example, when you copy a file to screen, the scrolling
speed is acceptable (the converting from the character to bitmap and
the scrolling has to be done by the CPU). I think the speed is comparable
to an Apple II or C64.

There are no internal registers (besides the status register). Even
the program counters (one for each interrupt level) are in memory.
The 0.3 MIPS are relativ: if you do an addition with both operands and
the result indirect addressed (only one instruction) you would need 7 
instructions (5 loads, 1 store, 1 execute) on a risc architecture.




                   +-------+
                   | XPROZ |
                   +-------+
               

HARDWARE INTERFACE:
==================

A14-A0:  address bus (seperate 32k words = 64 kbyte 
         RAM, ROM and I/O address range)

D15-D0:  data bus

RAMSEL~: if 0: accessing RAM (processor address $0000-$7fff)

ROMSEL~: if 0: accessing ROM (processor address $8000-$ffff)

IOSEL~:  if 0: accessing I/O space 

RW~:     if 0: write
         if 1: read

OE~:     if 0: RAM/ROM output buffers enabled 

RESET~:  if 0: reset processor (program starts at address $8000 in
               in interrupt mode 5 with disabled interrupts (sr=$00) 

IRQ1~:   if 0: interrupt request 1 
               (must be asserted at least 17*8 clock cycles)

IRQ2~:   if 0: interrupt request 2
               (must be asserted at least 17*8 clock cycles)

IRQ3~:   if 0: interrupt request 3 
               (must be asserted at least 17*8 clock cycles)

IRQ4~:   if 0: interrupt request 4 
               (must be asserted at least 17*8 clock cycles)

IRQ5~:   if 0: interrupt request 5 
               (must be asserted at least 17*8 clock cycles)


CLK:     processor clock (internaly divide by 8)



PROGRAM COUNTER (pc):
====================

The processor has no pc register. Memory location 0 is used for user pc and
memory location i (1<=i<=5) is used in interrupt mode i.



STATUS REGISTER (sr):
====================

This is the only internal processor register.


  15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| - | - | i5| i4| i3| i2| i1| ie| - | - | - | - | V | N | Z | C |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

ie:  if 1: interrupt enabled

i5:  if 0: processor is in interrupt mode 5 (highest priority) 
           (memory location 5 is used as pc)

i4:  if 0  and i5=1:  processor is in interrupt mode 4
           (memory location 4 is used as pc)

i3:  if 0  and i5=i4=1:  processor is in interrupt mode 3
           (memory location 3 is used as pc)

i2:  if 0  and i5=i4=i3=1:  processor is in interrupt mode 2
           (memory location 2 is used as pc)

i1:  if 0  and i5=i4=i3=i2=1:  processor is in interrupt mode 1
           (memory location 1 is used as pc)


V: overflow flag
N: negativ flag
Z: zero flag
C: carry flag

i5 - i1 are cleared by the external signals IRQ5~ - IRQ1~. They are set
(switch back to user mode) under software control.

After a reset the sr contains $00.




INSTRUCTION FORMAT:
==================


 B15 B14 B13 B12 B11 B10 B9  B8  B7  B6  B5  B4  B3  B2  B1  B0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|XSR|XIO|ZSR|ZIO|   |   |       |       |       |               |
+---------------+BED|SF |Z1  Z0 |Y1  Y0 |X1  X0 |ALU ALU ALU ALU|
|      CC       |   |   |       |       |       | 3   2   1   0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|                         x address (optional)                  |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|                         y address (optional)                  |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|                         z address (optional)                  |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+


ALU function determind by ALU3, ALU2, ALU1, ALU0
------------------------------------------------

+------+----------------+------+-------------------+
| ALU  |                | ALU  |                   |
| 1  0 |                | 3  2 |                   |
+------+----------------+------+-------------------+
|      |                | 0  0 |    add            |
| 0  0 | arithmetic     | 0  1 |    sub            |
|      |                | 1  0 |    addc           |
|      |                | 1  1 |    subc           |
+------+----------------+------+-------------------+
|      |                | 0  0 |    nor            |
| 0  1 | logic          | 0  1 |    and            |
|      |                | 1  0 |    eor            |
|      |                | 1  1 |    or             |
+------+----------------+------+-------------------+
|      |                | 0  0 |    ror            |
| 1  0 | shift right    | 0  1 |    rorc           |
|      |                | 1  0 |    asr            |
|      |                | 1  1 |    lsr            |
+------+----------------+------+-------------------+
|      |                | 0  0 |    rol            |
|      | shift left     | 0  1 |    rolc           |
| 1  1 |                | 1  0 |    asl=lsl        |
|      +----------------+------+-------------------+
|      | byte swap      | 1  1 |    bswp           |
+------+----------------+------+-------------------+





1. operand: x determind by X1,X0
--------------------------------

+-------+----------------------------------------------+---------+
| B5 B4 |  description                                 | symbol  |
+-------+----------------------------------------------+---------+
| 0  0  |  no x operand (internal a 1 is used)         |  -      |
| 0  1  |  x is an immediate operand                   | #wert   |
| 1  0  |  address of x                                | wert    |
| 1  1  |  address of address of x                     | (wert)  |
+-------+----------------------------------------------+---------+


2. operand: y determind by Y1,Y0
--------------------------------

+-------+----------------------------------------------+---------+
| B7 B6 |  description                                 | symbol  |
+-------+----------------------------------------------+---------+
| 0  0  |  no y operand (internal a 0 is used)         |  -      |
| 0  1  |  y is an immediate operand                   | #wert   |
| 1  0  |  address of y                                | wert    |
| 1  1  |  address of address of y                     | (wert)  |
+-------+----------------------------------------------+---------+


result: z determind by Z1,Z0
----------------------------

+-------+----------------------------------------------+---------+
| B9 B8 |  description                                 | symbol  |
+-------+----------------------------------------------+---------+
| 0  0  |  no result                                   |  -      |
| 0  1  |  result has same address as y operand        |  =      |
| 1  0  |  address of z                                | wert    |
| 1  1  |  address of addresse of z                    | (wert)  |
+-------+----------------------------------------------+---------+

exception: 

For y=(00) and z=(01) (i.e. no y operand and result has same address as y
operand) the result is stored in the actual pc (0 in user mode, i in
interrupt mode i). This allows 2 word jump instruction. 

e.g.    add cs hf #label,-,=


NOTE:

The combination y=(01) and z=(01) (i.e. y operand is immediate operand 
and result has same address as y operand) overwrites the immediate operand
with the result (self modifying code). This can be used for loop counter.

       add  tr hf  #100,-,lab2+1  ; initialise counter
lab1:  ...
       ...
       ...
lab2:  sub  tr sf  -,#0,=         ; subtract 1
       add  ne hf  #lab1,-,=      ; jump if not 0
       ...



set flags:  determind by SF
---------------------------

+----+----------------------------------------------------+---------+
|B10 |  description                                       | symbol  |
+----+----------------------------------------------------+---------+
| 0  |  flags are not modified                            |   hf    |
| 1  |  flags are modified according the result           |   sf    |
+----+----------------------------------------------------+---------+



conditional/unconditional: determind by BED
-------------------------------------------

+----+----------------------------------------------------+---------+
|B11 |  description                                       | symbol  |
+----+----------------------------------------------------+---------+
| 0  |  Instruction is executed only if the condition     |gt,ne,...|
|    |  CC (B15-B12) is is satisfied                      |         |
| 1  |  Instruction is always executed; B15-B12           |         |
|    |  modifies the x operand and result address         |   tr    |
+----+----------------------------------------------------+---------+



condition code: determind by CC
-------------------------------

+---------------+------+---------------------+----------------------+
|B15 B14 B13 B12|symbol|  description        | function             |
+---------------+------+---------------------+----------------------+
| 0   0   0   0 |  me  |  minus or equal     |  Z+N                 |
| 0   0   0   1 |  pe  |  plus and not equal |  (~Z)(~N)            |
| 0   0   1   0 |  hi  |  higher             |  (~C)(~Z)            |
| 0   0   1   1 |  ls  |  lower or same      |  C+Z                 |
| 0   1   0   0 |  cc  |  carry clear        |  ~C                  |
| 0   1   0   1 |  cs  |  carry set          |  C                   |
| 0   1   1   0 |  ne  |  not equal          |  ~Z                  |
| 0   1   1   1 |  eq  |  equal              |  Z                   |
| 1   0   0   0 |  vc  |  overvlow clear     |  ~V                  |
| 1   0   0   1 |  vs  |  overflow set       |  V                   |
| 1   0   1   0 |  pl  |  plus               |  ~N                  |
| 1   0   1   1 |  mi  |  minus              |  N                   |
| 1   1   0   0 |  ge  |  greater or equal   |  NV+(~N)(~V)         |
| 1   1   0   1 |  lt  |  less then          |  N(~V)+(~N)V         |
| 1   1   1   0 |  gt  |  greater then       |  NV(~Z)+(~N)(~V)(~Z) |
| 1   1   1   1 |  le  |  less or equal      |  Z+N(~V)+(~N)V       |
+---------------+------+---------------------+----------------------+


status register as x operand: determind by XSR
----------------------------------------------

+----+----------------------------------------------------+---------+
|B15 |  description                                       | symbol  |
+----+----------------------------------------------------+---------+
| 0  |  the regular x operand is used                     |  none   |
| 1  |  bits 13-8,3-0 of the regular x operand are        |         |
|    |  replaced by the corresponding bits in the         |   &     |
|    |  status register                                   |         |
+----+----------------------------------------------------+---------+


x operand from I/O address space: determind by XIO
--------------------------------------------------

+----+----------------------------------------------------+---------+
|B14 |  description                                       | symbol  |
+----+----------------------------------------------------+---------+
| 0  |  the regular x operand is used                     |  none   |
| 1  |  the address of the x operand is an I/O address    |         |
|    |  (no action if no x operand or immediate operand)  |   @     |
+----+----------------------------------------------------+---------+



result stored in status register: determind by ZSR
--------------------------------------------------

+----+----------------------------------------------------+---------+
|B13 |  description                                       | symbol  |
+----+----------------------------------------------------+---------+
| 0  |  the result is stored normaly                      |  none   |
| 1  |  the result is stored normaly and in the status    |         |
|    |  register                                          |    &    |
+----+----------------------------------------------------+---------+


NOTE: 
The least significant bits (flags) are stored in the status register 
only if also SF=1. The upper byte (interrupt and interrupt enable flags)
are stored in the status register only if there is also a normal Z result
(in memory or I/O, but not the current programm counter i.e. no Y operand
and Z result equal Y operand). 

EXAMPLE:

and tr sf   &-,#0,&-     ; C,Z,N,V flags cleared
                         ; interrupt flags not changed

and tr hf   &-,#0,&10    ; C,Z,N,V flags not changed
                         ; interrupt flags cleared 

and tr sf   &-,#0,&10    ; C,Z,N,V flags and interrupt flags cleared



result stored in I/O address space: detemind by ZIO
---------------------------------------------------

+----+----------------------------------------------------+---------+
|B12 |  description                                       | symbol  |
+----+----------------------------------------------------+---------+
| 0  |  the result is stored normaly                      |  none   |
| 1  |  the address of the result is an I/O address       |         |
|    |  (no action if no result)                          |    @    |
+----+----------------------------------------------------+---------+



INSTRUCTION SUMMARY
===================

add  x,y,z

     z = x + y                          C = carry
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = overflow 

addc x,y,z

     z = x + y + C                      C = carry
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = overflow 

sub  x,y,z

     z = y - x                          C = carry
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = overflow 

subc x,y,z

     z = y - x - C                      C = carry
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = overflow 

nor  x,y,z

     z = x nor y                        C = 0
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = undefined
                                        
or   x,y,z

     z = x or y                         C = 0
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

and  x,y,z

     z = x and y                        C = 0
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

eor  x,y,z

     z = x eor y                        C = 0
                                        Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

rol  x,y,z

     z[0] = x[15]                       C = x[15]
     z[i] = x[i-1]  for  1 <= i <= 15   Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

rolc x,y,z

     z[0] = C                           C = x[15]
     z[i] = x[i-1]  for  1 <= i <= 15   Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

lsl  x,y,z
asl  x,y,z

     z[0] = 0                           C = x[15]
     z[i] = x[i-1]  for  1 <= i <= 15   Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

ror  x,y,z

     z[i] = x[i+1]  for  0 <= i <= 14   C = x[0]
     z[15] = x[0]                       Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

rorc x,y,z

     z[i] = x[i+1]  for  0 <= i <= 14   C = x[0]
     z[15] = C                          Z = nor(z[i])
                                        N = z[15]
                                        V = undefined

lsr  x,y,z

     z[i] = x[i+1]  for  0 <= i <= 14   C = x[0]
     z[15] = 0                          Z = nor(z[i])
                                        N = z[15]
                                        V = undefined


asr  x,y,z

     z[i] = x[i+1]  for  0 <= i <= 14   C = x[0]
     z[15] = x[15]                      Z = nor(z[i])
                                        N = z[15]
                                        V = undefined


bswp  x,y,z

      z[i] = x[i+8]  for  0 <= i <= 7   C = x[15]
      z[i] = y[i-8]  for  8 <= i <= 15  Z = nor(z[i])
                                        N = z[15]
                                        V = undefined
  

program example:

    add  tr hf #100,xwert,ywert ; add 100 to xwert and store result in
                                ; ywert; flags not modified
    add  cs sf -,ywert,=        ; add 1 to ywert if carry set
                                ; modify flags according the result
    add  mi hf #l1,-,=          ; jump to l1 if negativ flag is set

    or   tr hf @$20,#$20,(30)   ; uncoditional 'or' with flags unchaged
                                ; 1. operand ist from I/O address $20
                                ; 2. operand = $20 (decimal 32)
                                ; the address of the result memory location
                                ; is stored im memory location 30 
l1: or   tr hf &#$3333,-,xwert  ; replace bits 13-8 and 3-0 of the number
                                ; $3333 with the coresponding bits of the
                                ; status register and store result in xwert
                                ; flags not modified

l2: add  tr hf #l2,-,=          ; endless loop   
                                ;   

IMPLEMENTATION DETAILS
----------------------

          +-------------*-------------*------------------------------DIN[15:0]
          |             |             |                 +---------+
          |             |             |                 +  TAKTE  +
    +-----+-------*-----+-------*-----+---------+       |T0 T1 T2 +--CLK
    | +---v--+    | +---v--+    | +---v--+      |       +-v--v--v-+
    +-> XREG <-+  +-> YREG <-+  +-> BREG <-+    +---------*  |  |
      +---v--+ |    +---v--+ |    +---v--+ |           +--v--v--v--+
          |    |        |    |        |    +----EB-----<           |
          |    |        |    +--------+---------EY-----<           |
          |    +--------+-------------+---------EX-----<           |
 +---+    |          +--*----------+  |                |           |
 |   |A   |B         |             |  +---B[15:0]------>           |
 | +-v----v-+    +---v---+     +---v---+               |           <-IRQ0
 |  \ XMUX /<+   | YGATE <-+   | AGATE <--GA,ADR[2:0]--<           <-IRQ1
 |    +-v+   |   +---v---+ |   +---v---+               |           <-IRQ2
 |      |    |       |     |       |                   |           <-IRQ3
 |      |    |       |     +-------+------GY-----------<           <-IRQ4
 |      |    +-------+-------------+------GX[1:0]------<           <-IRQ5
 |      |X           |Y            |                   |  control  |
 |  +---v----,  ,----v---+         |                   |           |
 |   \        \/        /          |                   |           >-OE
 *-SR0>\      ALU     /<-----------+------ALU [4:0]----<           >-RW
 |       +-v---v----+              |                   |           >-BE
 |         |   |Z                  |                   |           >-IO
 |         +---+-------------------+------SR_IN[15:0]-->           >-MEM
 +-------------+-------------------+------SR[15:0]-----<           |
               |                   |                   +-----------+
               |                   |
               |                   +---------------------------------AOUT[15:0]
               +-----------------------------------------------------DOUT[15:0]
 
 
+-----+--------------------+----------------------------------------------+
|phase| function           | description                                  |
+-----+--------------------+----------------------------------------------+
|  0  | PC  -> y           | load PC                                      |
|  1  | (y) -> BREG        | read opcode                                  |
|  2  | y+1 -> PC,y        | PC+1                                         |
|  3  | y+1 -> PC          | PC+1                                         |
|  4  | (y) -> y           | read address of address of  x operand        |
|  5  | (y) -> y           | read address of x operand                    |
|  6  | (y) -> x           | read x operand                               |
|  7  | PC  -> y           | load PC                                      |
|  8  | y+1 -> PC          | PC+1                                         |
|  9  | (y) -> y           | read ((address of) address of) y operand     |
| 10  | (y) -> y           | raed address of y operand                    |
| 11  | (y) -> y           | read y operand                               |
| 12  | ALU -> x           | do ALU operation, result -> x                |
| 13  | PC  -> y           | load pc                                      |
| 14  | y+1 -> PC          | PC+1                                         |
|     |     -> y if ~CC    | PC+1                                         |
| 15  | (y) -> y           | read (address of) address of result          |
| 16  | (y) -> y           | read address of result                       |
| 17  |  x  -> (y)         | store result                                 |
+-----+--------------------+----------------------------------------------+
x:       XREG
y:       YREG
CC:      1 if condition code true
ALU:     output of ALU
PC:      program counter 
          = memory location 0 for user mode, i for interrupt mode i

+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|phas| EB| EY| EX| GY|GX1|GX0| GA|Ad2|Ad1|Ad0|AL4|AL3|AL2|AL1|AL0| IO|MEM| RW|
+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|  0 | - | 1 | - | - | - | - | 0 | f1| f5| f6| - | - | - | - | - | 1 | 0 | 1 |
|  1 | 1 | 0 | - | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
|  2 | 0 | 1 | - | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|  3 | 0 | 0 | - | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|  4 | 0 | 1 | - | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
|  5 | 0 | 1 | - | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
|  6 | 0 | - | 1 | - | - | - | 1 | - | - | - | - | - | - | - | - |~f8| f8| 1 |
|  7 | 0 | 1 | 0 | - | - | - | 0 | f1| f5| f6| - | - | - | - | - | 1 | 0 | 1 |
|  8 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|  9 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
| 10 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
| 11 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
| 12 | 0 | - | 1 | f2| f3| f4| 0 | f1| f5| f6| f7| B3| B2| B1| B0| 1 |f10| 0 |
| 13 | 0 | 1 | 0 | - | - | - | 0 | f1| f5| f6| - | - | - | - | - | 1 | 0 | 1 |
| 14 | 0 |~CC| 0 | 1 | 1 | 0 | 0 | f1| f5| f6| - | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 15 | 0 | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
| 16 | - | 1 | 0 | - | - | - | 1 | - | - | - | - | - | - | - | - | 1 | 0 | 1 |
| 17 | - | - | - | 0 | 1 | 1 | 1 | - | - | - | - | 0 | 0 | 0 | 0 |~f9| f9| 0 |
+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

 f1 = (~I5) + (~I4)        f2 = B6 + B7           f3 = ~(B11 & B15)
 f4 = B4 + B5              f7 = B13 & B11         f8 = B11 & B14 & B5
 f5 = ( (~I2) + (~I3) ) & I4 & I5                 f9 = B11 & B12
 f6 = (~I1) & I2 & I4 +  (~I3) & I4  + (~I5)      f10= (~CC)+(~B8)+B9+B6+B7

B<i>= instruction bit i
CC  = 1 if condition code true
I<n>= sr[8+n] 
P<i>= phase i 



control signals:
---------------

EB = P1
EY = ~(P1 + P3 + P8 + P14 & CC)
EX = P6 + P12
GY = ~(P12 & (~B6) & (~B7) + P17) 
GX1= ~(P12 & B11 & B15)
GX0= P12 & (B4+B5) + P17
GA = ~(P0 + P2 + P3 + P7 + P8 + P12 + P13 + P14)
ADR2 = (~I5) + (~I4) 
ADR1 = ( (~I2) + (~I3) ) & I4 & I5  
Adr0 = (~I1) & I2 & I4 +  (~I3) & I4  + (~I5)   
ALU4 = B13 & B11
ALU3 = P12 & B3
ALU2 = P12 & B2
ALU1 = P12 & B1
ALU0 = P12 & B0
RW = ~(P2 + P3 + P8 + P12 + P14 + P17)
IO = ~(P6 & B11 & B14 & B5 + P17 & B11 & B12)
MEM=   P6 & B11 & B14 & B5 + P17 & B11 & B12 + P12 & ( (~CC)+(~B8)+B9+B6+B7 )


CLOCK:
-----

   .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .
   | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
   
           +---------------+               +---------------+            
T0  -------+               +---------------+               +------------

           +---+                           +---+                        
T1  -------+   +---------------------------+   +------------------------

       +-------+                       +-------+                       +
T2  ---+       +-----------------------+       +-----------------------+




state transition table:
----------------------

B<i>= instruction bit i
CC  = 1 if condition code true
P<i>= phase i 
C9,C8 = B9,B8  if  B9,B8 <> 0,1
C9,C8 = B7,B6  if  B9,B8 = 0,1


P0  --> P1
P1  --> P2
P2  --> P3  if     B4+B5
    --> P8  if     (~(B4+B5)) & (B6+B7) & ((~B8)+B9)
    --> P9  if     (~(B4+B5)) & (B6+B7) & B8 & (~B9)
    --> P12 if     (~(B4+B5)) & (~(B6+B7))
P3  --> P4  if     B4 & B5
    --> P5  if     (~B4) & B5
    --> P6  if     B4 & (~B5)
P4  --> P5
P5  --> P6
P6  --> P7  if     B6+B7
    --> P12 if     ~(B6+B7)
P7  --> P8  if     (~B8)+B9
    --> P9  if     B8 & (~B9)
P8  --> P9
P9  --> P10 if     B6 & B7
    --> P11 if     (~B6) & B7
    --> P12 if     (~B7)
P10 --> P11
P11 --> P12
P12 --> P13 if     C9+C8
    --> P0  if     (~C9) & (~C8)
P13 --> P14
P14 --> P15 if     CC & C9
    --> P17 if     CC & (~C9)
    --> P1  if     ~CC
P15 --> P16 if     C8
    --> P17 if     ~C8
P16 --> P17
P17 --> P0


                            +---+
                     +----->| 4 |
                     |      +-.-+
                     |        v
                     |      +---+
                     | +--->| 5 |
                     | |    +-.-+
                     | |      v
                    +'-'+   +---+   +---+
               +--->| 3 |-->| 6 |-->| 7 |---+
               |    +---+   +.--+   +-.-+   |
               |             |        v     |
               |             |      +---+   |
               | +-----------+----->| 8 |-+ |
               | |           |      +---+ v v
+---+  +---+  +'-'+          |           +---+  +---+
| 0 |->| 1 |->| 2 +----------+---------->| 9 |->| 10|
+---+  +---+  +-.-+          |           +.-.+  +-.-+
 ^ ^     ^      |            | +----------+ |     |
 | |     |      |            v v            v     |
 | |     |      |           +---+        +---+    |
 | |     |      +---------->| 12|<-------| 11|<---+
 | |     |                  +.-.+        +---+
 | +-----+-------------------+ v
 |       |                  +---+
 |       |                  | 13|
 |       |                  +-.-+
 |       |                    v
 |       |                  +---+
 |       +------------------| 14|-----+
 |                          +-.-+     v
 |                            |     +---+
 |                            |     | 15|
 |                            |     +.-.+
 |                            | +----+ v
 |                            | |    +---+
 |                            | |    | 16|
 |                            v v    +-.-+
 |                           +---+     |
 +---------------------------| 17|<----+
                             +---+


data and reset signals for state flip-flops:
-------------------------------------------

D0 = P12 & (~C9) & (~C8) + P17
D1 = P0 + P14 & (~CC)
D2 = P1
D3 = P2                                         R3 = P8 + P9 + P12
D4 = P3                                         R4 = P5 + P6
D5 = P4 + P3 & (~B4)
D6 = P5 + P3 & (~B5)
D7 = P6                                         R7 = P12
D8 = P7 + P2 & ( ~(B4+B5) )                     R8 = P9 +P12
D9 = P8 + D8 & B8 & (~B9)                       R9 = P12
D10= P9                                         R10= P11 + P12
D11= P10 + P9 & (~B6)                           R11= P12
D12= (P2 & ( ~(B4+B5) ) + P6 )  & ( ~(B6+B7) ) + P9 & (~B7) + P11
D13= P12                                        R13=P0
D14= P13
D15= P14                                        R15= P1 + P17
D16= P15                                        R16= P17
D17= P14 & (~C9) + P15 & (~C8) + P16            R17= P1


description of the functional units:
===================================

1. XREG
-------

description: 16 bit register
inputs:      D[15:0], CLK, E
outputs:     Q[15:0]
function:    if E=1 then D[15:0] is latched into the register with the
             next rising clock
reset:       after a reset this register contains 0


2. YREG
-------

description: 16 bit register
inputs:      D[15:0], CLK, E
outputs:     Q[15:0]
function:    if E=1 then D[15:0] is latched into the register with the
             next rising clock
reset:       after a reset this register contains $8000


3. BREG
-------

description: 16 bit register
inputs:      D[15:0], CLK, E
outputs:     Q[15:0]
function:    if E=1 then D[15:0] is latched into the register with the
             next rising clock
reset:       after a reset this register contains 0



4. TAKTE
--------

description: clock divider
inputs:      CLK
outputs:     T0, T1, T2
funcion:     generates the following clock signals:


   .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .
CLK| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
   
           +---------------+               +---------------+            
T0  -------+               +---------------+               +------------

           +---+                           +---+                        
T1  -------+   +---------------------------+   +------------------------

       +-------+                       +-------+                       +
T2  ---+       +-----------------------+       +-----------------------+
                           ^
                           start after reset


reset:       during reset T0, T1 and T2 are 0


5. XMUX
-------

description: multiplexer, which outputs $0001, the status register
             or the contens of XREG 
inputs:      A[15:0], B[15:0], G1, G0
outputs:     C[15:0]


function:    G1 G0 |  C[15:14] | C[13:8] | C[7:4] | C[3:0]
             ---------------------------------------------
             0  0  |     00    | A[13:8] |   0    | A[3:0]
             0  1  |  B[15:14] | A[13:8] | B[7:4] | A[3:0]
             1  0  |     00    |  000000 |  0000  |  0001 
             1  1  |  B[15:14] | B[13:8] | B[7:4] | B[3:0]


6. YGATE
--------

description: multiplexer, which outputs $0000 or the contens of YREG 
inputs:      A[15:0], G
outputs:     C[15:0]

funktion:      G |  C[15:0]
               ------------
               0 |  $0000  
               1 |  A[15:0]

7. AGATE
--------

description: multiplexer, which outputs $0000, $0001, $0002, $0003, $0004, 
             $0005  or the contens of YREG 
inputs:      A[15:0], G,S2,S1,S0
outputs:     C[15:0]

function:    if G=1 : C[15:0]=A[15:0]
             if G=0 : C<i>=0   for 15 <= i <= 3
                      C2=S2
                      C1=S1
                      C0=S0

8. ALU
------

description:  does arithmetic and logical operations
inputs:       X[15:0], Y[15:0], CIN, S[4:0]
outputs:      Z[15:0], SR_OUT[15:0]
function:      

               +------------+------------+---------------------------+
               |s1 s0 s3 s2 |  Z         | CF             VF         |
               +------------+------------+---------------------------+
               | 0  0  0  0 |  X+Y       | C(X+Y)         V(X+Y)     |
               | 0  0  0  1 |  Y-X       | C(Y-X)         V(Y-X)     |
               | 0  0  1  0 |  X+Y+CIN   | C(X+Y+CIN)     V(X+Y+CIN  |
               | 0  0  1  1 |  Y-X-CIN   | C(Y-X-CIN      V(Y-X-CIN) |
               +------------+------------+---------------------------+
               | 0  1  0  0 |  X nor Y   | 0              V(X+Y)     |
               | 0  1  0  1 |  X and Y   | 0              V(Y-X)     |
               | 0  1  1  0 |  X eor Y   | 0              V(X+Y+CIN  |
               | 0  1  1  1 |  X or  Y   | 0              V(Y-X-CIN) |
               +------------+------------+---------------------------+
               | 1  0  0  0 |  ror  X    | X[0]           V(X+Y)     |
               | 1  0  0  1 |  rorc X    | X[0]           V(Y-X)     |
               | 1  0  1  0 |  asr  X    | X[0]           V(X+Y+CIN  |
               | 1  0  1  1 |  lsr  X    | X[0]           V(Y-X-CIN) |
               +------------+------------+---------------------------+
               | 1  1  0  0 |  rol  X    | X[15]          V(X+Y)     |
               | 1  1  0  1 |  rolc X    | X[15]          V(Y-X)     |
               | 1  1  1  0 |  asl  X    | X[15]          V(X+Y+CIN  |
               | 1  1  1  1 |  bswp X,Y  | X[15]          V(Y-X-CIN) |
               +------------+------------+---------------------------+


               if S4=1: SR_OUT[13:8,3:0]= Z[13:8,3:0]

               if S4=0: SR_OUT[0]    = CF
                        SR_OUT[1]    = nor (Z[i])  i=0..15
                        SR_OUT[2]    = Z[15]
                        SR_OUT[3]    = VF
                        SR_OUT[13:8] = Z[13:8]



Article: 12916
Subject: Re: New free FPGA CPU
From: jmccarty@sun1307.spd.dsccc.com (Mike McCarty)
Date: 4 Nov 1998 19:33:45 GMT
Links: << >>  << T >>  << A >>
In article <snewman-0311981738370001@cm20816640181.cableco-op.com>,
Steve Newman <snewman@acm.no.spam.org> wrote:

)> So I asked why I should use this particular uController. What is its
)> supposed forte?
)> 
)> A bunch of people are answering unrelated questions like
)> 
)>         Why would anyone design a special purpose uController?
)>         Why did this guy design *this* uController?
)> etc.
)> 
)> You have joined the list of such responders.
)> 
)> Mike
)
)Are you deliberately trying to piss people off?  I seriously doubt that
)anyone has responded to this thread "without reading the posts at all".
)It might have occurred to you that, perhaps, just perhaps, there is an
)honest misunderstanding involved -- and it might even be on your part.

This particular guy, I don't care about. You have a problem with that?
I'm getting annoyed with people assuming that either

	I think it's foolish or stupid or not worthwhile to do such a
	thing
or
	I don't understand what the point of specialized uControllers is
or
	I have some sort of misunderstanding about what is being
	discussed.

I have no ulterior motives in asking a question!

I asked a simple question, posed TO THE MAN WHO DESIGNED THE THING, the
answer to which I thought would be of general interest, and everybody
and his dog are jumping in and telling me something is wrong with my
question or my attitude or something, YOU INCLUDED.

I want a simple answer to a simple question, not directions about how to
use the net, what to think, or instructions on how to improve my
attitude.

I'll restate the question so hopefully all will see what I asked and
stop pestering me.

What is the particular optimized point of this chip? What is it that it
is peculiarly good at doing?

If there is no application to which it is particularly suited and
superior to other (usually more available and cheaper) standard
uControllers, then fine, that's ok. I understand people playing with
stuff just to see whether it can be done, and if so just how well the
results turn out. And I can ignore the chip. No big deal.

Now, how about if the rest you SHUT UP AND LET THE DESIGNER ANSWER THE
QUESTION?

)I've avoided getting into this discussion because I'm not particularly
)expert in processor design or FPGAs.  However, it's gone on for a while
)without anyone making what I think is the key point, so here goes.

It's too bad you abandoned your wise choice not to attempt answering a
question which you have no hopes of being able to answer.

Since you do not and cannot know the answer to the question I posed
(since you didn't do the design, and only the designer knows what he is
setting out to optimize), please cease to waste bandwidth in attempting
to reply to my question.

[rest of post cut due to being speculation]

Mike
-- 
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel      <- They make me say that.
Article: 12917
Subject: Re: New free FPGA CPU
From: jmccarty@sun1307.spd.dsccc.com (Mike McCarty)
Date: 4 Nov 1998 19:38:13 GMT
Links: << >>  << T >>  << A >>
In article <71ocss$ib7@web.nmti.com>,
Peter da Silva <peter@baileynm.com> wrote:
)In article <71o7cr$s3p$1@relay1.dsccc.com>,
)Mike McCarty <jmccarty@sun1307.spd.dsccc.com> wrote:
)>A guy posted that he had designed a uController on an FPGA. It would
)>cost about $15, and does not seem optimized for any particular
)>application, and is missing several things that most uControllers have.
)
)Unless it takes up the whole FPGA, that means you have the rest of the
)FPGA to play with to put those several things.
)
)>I have used specialized uControllers made on FPGAs, and ASICs before,
)>but see no advantage to this one. In fact, regular uControllers which
)>are lower in price seem better suited to do most of the things a
)>uController would do.
)
)It lets someone who isn't up to designing a specialized uController of his
)own to put one in the corner of an FPGA they're messing around with.
)
)>So I asked why I should use this particular uController.
)
)You shouldn't. You're not the target market. Like (say) Dennis Ritchie
)wasn't the target market for (say) Minix. Think about it in those terms.

And there is nothing wrong with that answer. But to listen to most of
the replies to my question, one would think that I was looking down my
nose at anyone who would consider the thing. Or that I don't see the
value of "foolin' around" with something new just to get the hang of it.

To say that the thing is not particularly good at anything, and probably
shouldn't be used in any real applications, is not to say that it is not
worthwhile doing/having/playing with.

But are you the designer? If not, then you really aren't qualified to
answer the question; only the designer can say what he is trying to
optimize and what tradeoffs resulted.

The 8031 series optimized bit operations at the expense of memory
addressing.

[snip]

)Think of it as an open-source processor. Think of it as an opportunity for
)hobbyists who hitherto wouldn't be up to this sort of experimentation.

I have no problem with ANY answer to the question, so long as it is
truthful and comes from the designer.

Mike
-- 
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel      <- They make me say that.
Article: 12918
Subject: Re: Concept or Viewlogic viewer?
From: cha5253105@aol.com (CHa5253105)
Date: 4 Nov 1998 20:16:47 GMT
Links: << >>  << T >>  << A >>
      Thanks for the several replies regarding browser and translation
tools.  

1. In reference to one response regarding the use of Edif Out of
   Concept, and Edif In to Viewlogic, the tools don't solve enough of the
   problem.  There were files called chips_prt and filename.ppt which
   contain important library information that were not transferred.  

2. In reference to another response regarding Router Solutions (RSI), they
   appeared more back end oriented versus front end. 

3. I finally got in contact with an Cadence applications engineer, and asked 
   him what they use.   With the disclaimer, "We Don't Make Recommendations", 
   he did finally admit they have use RSI (http://www.rsi-inc.com) for the back
end 
   a company Concurrent CAED Solutions (http://www.ccaes.com)  for the front 
   end. They did have a browser that works for both concept and viewdraw
   schematics (so I now have some plots),  plus some translation tools.


Cindy Harris


Article: 12919
Subject: Re: New free FPGA CPU
From: rbarris@quicksilver.com (Rob Barris)
Date: Wed, 04 Nov 1998 14:11:54 -0800
Links: << >>  << T >>  << A >>
In article <71qa6p$n67$1@relay1.dsccc.com>, jmccarty@sun1307.spd.dsccc.com
(Mike McCarty) wrote:

> What is the particular optimized point of this chip? What is it that it
> is peculiarly good at doing?

   I thought the "open source processor" was a very apt descrption.  The
subsequent point of it being embeddable in an FPGA along with *whatever
else the designer can fit*... means it could be good for whatever you can
mold it into.

> Now, how about if the rest you SHUT UP AND LET THE DESIGNER ANSWER THE
> QUESTION?

   "Hey, you! Usenet! Shut up for a second!"

   It's not like posts and discussion from other folks will in any way
prevent you from reading the designer's answer, if and when he should
choose to write one for you.

Rob
Article: 12920
Subject: Re: New free FPGA CPU
From: snewman@acm.no.spam.org (Steve Newman)
Date: Wed, 04 Nov 1998 16:45:52 -0800
Links: << >>  << T >>  << A >>
In article <71qa6p$n67$1@relay1.dsccc.com>, jmccarty@sun1307.spd.dsccc.com
(Mike McCarty) wrote:

> In article <snewman-0311981738370001@cm20816640181.cableco-op.com>,
> Steve Newman <snewman@acm.no.spam.org> wrote:
> 
> ) [deeply nested quotes deleted]
> )
> )Are you deliberately trying to piss people off?  I seriously doubt that
> )anyone has responded to this thread "without reading the posts at all".
> )It might have occurred to you that, perhaps, just perhaps, there is an
> )honest misunderstanding involved -- and it might even be on your part.
> 
> This particular guy, I don't care about. You have a problem with that?
> I'm getting annoyed with people assuming that either
> 
>         I think it's foolish or stupid or not worthwhile to do such a
>         thing
> or
>         I don't understand what the point of specialized uControllers is
> or
>         I have some sort of misunderstanding about what is being
>         discussed.

Personally, I haven't made any of these assumptions.  If you assumed I
did, and are not simply referring to other posts in this thread, then you
have committed the same class of sin that you are accusing other people of.

More generally, I think you will get better results from Usenet if you
assume that people responding to your posts are genuinely trying to
answer a question you think they you asked, and if they seem to be doing
something else, then either they misunderstood your question (which might
be due to hasty reading on their part, or poor phrasing on your part), or
you misunderstood their answer (ditto).  Clarifying or restating your
question is great, but while doing so it is important to keep the
discussion on a calm level, and avoid provocative phrasing like "I'm
getting tired of people doing XXX" or accusations such as "people are
responding... without reading the posts at all".


> I have no ulterior motives in asking a question!
> 
> I asked a simple question, posed TO THE MAN WHO DESIGNED THE THING, the
> answer to which I thought would be of general interest, and everybody
> and his dog are jumping in and telling me something is wrong with my
> question or my attitude or something, YOU INCLUDED.
> 
> I want a simple answer to a simple question, not directions about how to
> use the net, what to think, or instructions on how to improve my
> attitude.
> 
> I'll restate the question so hopefully all will see what I asked and
> stop pestering me.
> 
> What is the particular optimized point of this chip? What is it that it
> is peculiarly good at doing?

Part of the problem, I think, is the form in which you are asking this
question.  It's a bit like "when did you stop beating your wife?"  The
way you phrase the question implies that it is particuarly optimized for
something, that no one would create a processor design without some
specific application in mind.  Based on your most recent post, I gather
that you did not intend such an implication.  I did not understand that
previously, and suspect that others in this group had the same
misunderstanding.

Now, if you don't want my (or others') advice, I'll stop offering it --
in any case, I doubt I will respond again on this thread.  But Usenet is
a public forum for open discussion, and when you make a post, it becomes
everyone's business.


> ...
> 
> )I've avoided getting into this discussion because I'm not particularly
> )expert in processor design or FPGAs.  However, it's gone on for a while
> )without anyone making what I think is the key point, so here goes.
> 
> It's too bad you abandoned your wise choice not to attempt answering a
> question which you have no hopes of being able to answer.
> 
> Since you do not and cannot know the answer to the question I posed
> (since you didn't do the design, and only the designer knows what he is
> setting out to optimize), please cease to waste bandwidth in attempting
> to reply to my question.
> 
> [rest of post cut due to being speculation]

Oh good grief.  Obviously I'm not the designer, and so I can't definitively
state what the designer's intent was.  But it's a long leap from there to
having "no hopes of being able to answer".  The designer has posted
considerable information about the processor, its capabilities, and the
ideas behind the design.  I had read and digested this information.
Based on this, I felt with some confidence that I could answer your
question, and since the designer had not done so, I thought I would chip
in.  With only 23 years of experience in the (broader) field, please
forgive me for engaging in "speculation".  Also note that your question
addressed the actual processor, and did not mention "intent" -- thus, it
concerns what the designer actually achieved, which may not be exactly the
same thing as what he intended, and is something that people other than the
designer are quite able to discuss.

-- Steve Newman
   snewman@acm.no.spam.org
Article: 12921
Subject: Re: New free FPGA CPU
From: jhallen@world.std.com (Joseph H Allen)
Date: Thu, 5 Nov 1998 00:53:25 GMT
Links: << >>  << T >>  << A >>
In article <71qaf5$pd0$1@relay1.dsccc.com>,
Mike McCarty <jmccarty@sun1307.spd.dsccc.com> wrote:

>only the designer can say what he is trying to optimize and what tradeoffs
>resulted.

The design goal is the same as it is for all general purpose CPUs: design
the most powerful CPU that will fit in the given hardware.  The hardware is
an XC5202 and byte-wide memory.  I chose this hardware because the XC5202 is
the cheapest SRAM FPGA that my tools will program and because single chips
of byte-wide external RAM and ROM is the cheapest memory solution.  I have
visions of making a BASIC-stamp type device with this, so it matters.  It is
cheaper (in an absolute dollar sense, and certainly in a dollar / bit sense)
than, say, trying to use an XC4003 (which has 2048 bits of internal RAM). 
It may not be cheaper than the altera flex parts (or whichever is the other
FPGA containing RAM), but I have no experience with them.

There are other more nebulous design goals as well.  Basically I would not
have made a weaker CPU if it came at the expense of being able to use data
structures.  This means that I prefer to have some form of indexing instead
of the cheaper alternatives: direct addressing only (like the original Von
Neumann computer with the resulting need for self-modifying code and the
execute instructions of future computers), register indirect addressing only
(like the 8080), or memory indirect addressing only (like the pdp-8).  I had
considered the 6502 method of indexing (where the base address is fixed, or
stored in a zero-page location, and the 8-bit offset is in a register), but
having programmed both 6502s and 6800s, I know that fixed offsets are to be
prefered to fixed base-addresses (thus the 6502 index registers are, IMHO,
useless).  So I know that I need to encode two fields for indexed
instructions: where the base is and the value of the offset.  You want the
offset to be as large as possible since that limits the size of the data
structures you can have, thus the current 2-bit/7-bit format.  If the base
address was not going to be in an actual register, the next best place is
the top of stack (which is much better than in a zero-page location).

The other nice thing about indexing is that it allows you to make fast move
unrolled move loops:

	lda	0,x
	sta	0,y
	lda	2,x
	sta	2,y
	etc.

At 8 cycles for loads and 10 cycles for stores and two bytes per transfer,
this gives a move speed of 9 cycles per byte.

If I could get high memory to memory copy speed (which I think is important)
with indexing, then I wouldn't have to worry wasting op-code space with any
other method (I.E., special instructions or auto-increment addressing
modes).

Another lesson from the 6502 (and the 8088 for that matter), is that it just
really sucks if the largest datum you can manipulate is smaller than your
address size.  This means that the accumulator needs to be the same size as
the PC- 16-bits.

So there you go.  If you have any ideas for improving it without expending
too much extra hardware, I'd like to hear them.

Actually, I have some improvements already: I realized that the ALU was not
restricted in one way that I had originally thought that it was: namely that
the subtraction direction (A-B) required that the left-shift operation be
only allowed on the A-side.  It turns out that I can invert the output
(which costs nothing) and switch the subtraction direction (B-A) (a side
effect is that the borrow sign is reversed).  This means that right-shifter
and sign-extender do not need to provide a complement operation (for getting
subtract with the restricted ALU), which results in halving their size.

Also, I'm going to eliminate the MUX which allows the PC to be directly
transfered to the address output register.  This MUX costs 16 FMAPs and
really only saves one cycle in one instruction.  Also, I'm no longer going
to have writes transfered directly from the ALU to the external data-bus. 
Instead, both the low and high bytes of the written data are going to be
registered.  This is because the CLK to output time for data going through
the ALU is too large. This adds one dead cycle to the RMW instructions, but
is more than made up for in clock frequency.

Another space-saving change will be to rearrange the operation decoder (not
the instruction decoder).  Upon reading the 5202 data sheet for the nth
time, I found that 5-input functions are available in only 2-fmaps instead
of 3 (because there's an extra MUX between each pair).  Anyway, I need to
rearrange this to take advantage of that.

A more significant change that I'm considering is to add 2 or 3 real index
registers (in replacement of the top-of stack indexing).  The consequeces of
this are 32 or 48 more flip-flops used, but 7 flip-flops saved since the
DISP register would not then be needed.  Best of all, it would cut 3-cycles
from each index instruction (index registers really do reduce the memory
bandwidth requirements :-).  I would also need loads, stores, adds and
compares for the index registers, but I think they could be squeezed into
the op-code map.  I think this is the cheapest thing I can do to the improve
the speed of the CPU.  The unrolled move speed improves to 6 cycles per byte
(or 5 cycles per byte if I make stores different from RMW), instead of the
current 9 cycles/byte.

>The 8031 series optimized bit operations at the expense of memory
>addressing.

I don't think this is quite right.  The 8031 (isn't it more proper to call
the series the 8048 or perhaps 8021?) was the first single-chip 8-bit
microcontroller.  It's competition was the two-chip F8.  I think the goal
here was simply to design any 8-bit processor that would fit on a single
chip along with ram and rom.  I don't think the bit operations really came
at the expense of anything- it's more likely that the bit operations were a
near-zero cost extension to the instruction set.

Intel likes those memory-immediate operations for some reason.  Everything
from the 8080 on (including the 8048) has them, but I doubt they are
worthwhile (and I'm sure they cost a lot).
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 12922
Subject: Re: New free FPGA CPU
From: Sp_am_Kil_ler_Xiuhtecuhtli@worldnet.att.net (Kolaga Xiuhtecuhtli)
Date: 5 Nov 1998 04:07:13 GMT
Links: << >>  << T >>  << A >>
On 4 Nov 1998 19:33:45 GMT, jmccarty@sun1307.spd.dsccc.com (Mike
McCarty) wrote:

>In article <snewman-0311981738370001@cm20816640181.cableco-op.com>,
>Steve Newman <snewman@acm.no.spam.org> wrote:
>
>)> So I asked why I should use this particular uController. What is its
>)> supposed forte?
>)> 
>)> A bunch of people are answering unrelated questions like
>)> 
>)>         Why would anyone design a special purpose uController?

What do you call those processors on video cards and disk drives?

I imagine if the volume is large enough, a specialized high
performance uC is appropriate.
---
Remove the characters SPAMMENOT to reply via e-mail
Article: 12923
Subject: Re: Schematic entry?
From: "Thomas D. Tessier" <tomt@hdl-design.com>
Date: Wed, 04 Nov 1998 21:53:53 -0700
Links: << >>  << T >>  << A >>
ems@riverside-machines.com.NOSPAM wrote:
> 
> On Sun, 1 Nov 1998 00:32:50 +0000, Edward Moore
> <edmoore@edmoore.demon.co.uk> wrote:
> 
> >Exemplar Leonardo supports blocks, and a whole lot of other stuff too.
> >The only thing it objects to that I would find useful is a declarative
> >region inside a GENERATE statement (VHDL'93 only), so you don't need to
> >do:
> >        block_name : BLOCK
> >                SIGNAL local_signal : STD_LOGIC;
> >        BEGIN
> >                generate_name : IF condition THEN GENERATE
> >                        -- code
> >                END GENERATE;
> >        END BLOCK;
> >
> >but could just do:
> >
> >        generate_name : IF condition THEN GENERATE
> >                SIGNAL local_signal : STD_LOGIC;
> >                -- code
> >        END GENERATE;
> 
> i just tried this on leo 4.1.3 without problems - i presume that your
> 'THEN' is a typo, and not the cause of the original problem?
> 
> exemplar does have a problem with attribute declarations in a generate
> declarative region (they're only evaluated once, instead of on every
> iteration), but that's another story.
What does Exemplar generate? Is this a piece of hierarchy that you can
operate on?  I have not use Exemplar for quite some time, but the Block
feature didn't work.  It would just ignore it!

Thanks for the update, I will look in it with pleasure :-)
TomT...
-- 
+------------------------ ---------------------- ----------------------+
: t2design                                                             :
: 249 Lois Drive                                                       :
: Louisville, CO 80027                                                 :
+------------------------ ---------------------- ----------------------+
:  tomt@hdl-design.com   *  (303)665-6402       * Fax: (303)665-6431   :
+------------------------ ---------------------- ----------------------+
Article: 12924
Subject: Re: Schematic entry?
From: "Thomas D. Tessier" <tomt@hdl-design.com>
Date: Wed, 04 Nov 1998 21:56:36 -0700
Links: << >>  << T >>  << A >>
ems@riverside-machines.com.NOSPAM wrote:
> 
> On Sun, 1 Nov 1998 00:32:50 +0000, Edward Moore
> <edmoore@edmoore.demon.co.uk> wrote:
> 
> >Exemplar Leonardo supports blocks, and a whole lot of other stuff too.
> >The only thing it objects to that I would find useful is a declarative
> >region inside a GENERATE statement (VHDL'93 only), so you don't need to
> >do:
> >        block_name : BLOCK
> >                SIGNAL local_signal : STD_LOGIC;
> >        BEGIN
> >                generate_name : IF condition THEN GENERATE
> >                        -- code
> >                END GENERATE;
> >        END BLOCK;
> >
> >but could just do:
> >
> >        generate_name : IF condition THEN GENERATE
> >                SIGNAL local_signal : STD_LOGIC;
> >                -- code
> >        END GENERATE;
> 
> i just tried this on leo 4.1.3 without problems - i presume that your
> 'THEN' is a typo, and not the cause of the original problem?
> 
> exemplar does have a problem with attribute declarations in a generate
> declarative region (they're only evaluated once, instead of on every
> iteration), but that's another story.
What does Exemplar generate? Is this a piece of hierarchy that you can
operate on?  I have not use Exemplar for quite some time, but the Block
feature didn't work.  It would just ignore it!

Thanks for the update, I will look in it with pleasure :-)
TomT...
-- 
+------------------------ ---------------------- ----------------------+
: t2design                                                             :
: 249 Lois Drive                                                       :
: Louisville, CO 80027                                                 :
+------------------------ ---------------------- ----------------------+
:  tomt@hdl-design.com   *  (303)665-6402       * Fax: (303)665-6431   :
+------------------------ ---------------------- ----------------------+


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