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Messages from 129425

Article: 129425
Subject: FPGA Editor Tutorial based on examples
From: maverick <sheikh.m.farhan@gmail.com>
Date: Sat, 23 Feb 2008 04:30:47 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,
I am looking for some good in depth tutorial on FPGA Editor. I have
seen the video demos on youtube but they just give you intro to the
tool. There are so many tutorials available on other tools from Xilinx
with examples but I could not find one on FPGA Editor. Any help in
this regard will be appreciated.....
regards
Farhan

Article: 129426
Subject: Re: FPGA Editor Tutorial based on examples
From: Frank Buss <fb@frank-buss.de>
Date: Sat, 23 Feb 2008 13:39:09 +0100
Links: << >>  << T >>  << A >>
maverick wrote:

> I am looking for some good in depth tutorial on FPGA Editor. I have
> seen the video demos on youtube but they just give you intro to the
> tool. There are so many tutorials available on other tools from Xilinx
> with examples but I could not find one on FPGA Editor. Any help in
> this regard will be appreciated.....

Another video, but maybe more in depth:

http://groups.google.de/group/comp.arch.fpga/browse_frm/thread/72439bf6f26c4100

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 129427
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: morphiend <morphiend@gmail.com>
Date: Sat, 23 Feb 2008 05:29:01 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 23, 3:06 am, Bob Smith <use...@linuxtoys.org> wrote:
> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
> of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
> google hits on this did not help.
>
> It must be a simple mistake; any ideas what I'm doing wrong?
> The "****" indicate the lines from the prototype that I've changed.
>
> thanks
> Bob Smith
>
> ==================================================================================
> module clocks(clkin, clkout1, clkout2);
>
> input clkin;     // Digilent Spartan 3e starter kit 50 MHz clock
> output clkout1;  // Wanna be 8 MHz
> output clkout2;  // 50 MHz/32 for comparison
>
> reg [7:0] count;
>
> always @(posedge clkin)
> begin
>      count <= count + 1;
> end
>
> assign clkout2 = count[4];
>
> DCM #(
>        .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
>                            //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
>        .CLKFX_DIVIDE(25),   // Can be any integer from 1 to 32       **************
>        .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32        ************
>        .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
>        .CLKIN_PERIOD(20.0),  // Specify period of input clock        ***********
>        .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
>        .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X  *********
>        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
>                                              //   an integer from 0 to 15
>        .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
>        .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
>        .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
>        .FACTORY_JF(16'hC080),   // FACTORY JF values
>        .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
>        .STARTUP_WAIT("FALSE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
>     ) DCM_inst (
>        .CLK0(CLK0),     // 0 degree DCM CLK output
>        .CLK180(CLK180), // 180 degree DCM CLK output
>        .CLK270(CLK270), // 270 degree DCM CLK output
>        .CLK2X(CLK2X),   // 2X DCM CLK output
>        .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
>        .CLK90(CLK90),   // 90 degree DCM CLK output
>        .CLKDV(CLKDV),   // Divided DCM CLK out (CLKDV_DIVIDE)
>        .CLKFX(clkout1),   // DCM CLK synthesis out (M/D)          ************
>        .CLKFX180(CLKFX180), // 180 degree CLK synthesis out
>        .LOCKED(LOCKED), // DCM LOCK status output
>        .PSDONE(PSDONE), // Dynamic phase adjust done output
>        .STATUS(STATUS), // 8-bit DCM status bits output
>        .CLKFB(CLKFB),   // DCM clock feedback
>        .CLKIN(clkin),   // Clock input (from IBUFG, BUFG or DCM)   ************
>        .PSCLK(PSCLK),   // Dynamic phase adjust clock input
>        .PSEN(PSEN),     // Dynamic phase adjust enable input
>        .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
>        .RST(RST)        // DCM asynchronous reset input
> );
>
> endmodule

I know this sounds like a simple answer, but have you checked your
input clock? That was an issue I just had recently. My external
oscillator was not generating its 100MHz signal.

-- Mike

Article: 129428
Subject: Re: FPGA Editor Tutorial based on examples
From: MikeShepherd564@btinternet.com
Date: Sat, 23 Feb 2008 14:17:51 +0000
Links: << >>  << T >>  << A >>
>I am looking for some good in depth tutorial on FPGA Editor. I have
>seen the video demos on youtube...

Videos???

YouTube???

There has to be something wrong with the documentation of a product
when people feel the need to explain it by making videos for YouTube.

Article: 129429
Subject: Re: FPGA Editor Tutorial based on examples
From: Frank Buss <fb@frank-buss.de>
Date: Sat, 23 Feb 2008 15:41:12 +0100
Links: << >>  << T >>  << A >>
MikeShepherd564@btinternet.com wrote:

>>I am looking for some good in depth tutorial on FPGA Editor. I have
>>seen the video demos on youtube...
> 
> Videos???
> 
> YouTube???
> 
> There has to be something wrong with the documentation of a product
> when people feel the need to explain it by making videos for YouTube.

That's no suprise for Xilinx tools. At least it is not that worse for the
usual functions, if you follow the quick start guide for some starter kit.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 129430
Subject: Planahead IP export
From: PatC <pato@patocarr.com>
Date: Sat, 23 Feb 2008 09:17:59 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm trying to insert an IP core generated by PlanAhead into our
script-based flow, but map fails with Pack:679 error on several slices.

The IP in question is a wrapper around the PCIe block plus, that
contains our DMA engine. This component is pretty big and we decided to
lock it down when we deliver the sources to our customers. Using
PlanAhead, we intend to floorplan it tightly and lock its placement so
the customer won't have timing issues.

The exported IP is in the edn/ucf form, and it's imported into our xst
flow without problems. I gutted the top level of the component and made
it a black box. Xst and ngdbuild run without problems. Both transform
the edn into an ngo. I also concatenated the system ucf to the component
ucf and fixed the relative paths.

Map fails with 105 error 679, and over 3 thousand warnings (some
expected). Different runs give different results though.

"Unable to obey design constraints (LOC=SLICE_X46Y115) which require the
combination of the following symbols into a single SLICEL component"
... (snip - see below)
"The clock enable signals don't agree. Please correct the design
constraints accordingly."

Looking at the SLICEL in PlanAhead, I see six symbols (3 LUTs, 3 FLOPs)
and a seventh one that doesn't seem related to the others. Perhaps this
is the one "clock enable" referred to in the error message.

Also, doubting of the import-into-my-flow procedure, I made another PA
project, where I import this same IP into the netlist, and it fails with
the same errors.

Has anybody seen this error? The answer records show some similar
errors, but no explanation on how to work around it/fix it.

Thanks in advance,
-Pat



Error Message:
------------------------------
ERROR:Pack:679 - Unable to obey design constraints (LOC=SLICE_X46Y115)
which require the combination of the following symbols into a single
SLICEL component:
LUT symbol
"ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_60_mux00003
11" (Output Signal =
ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_mux0000[8])
LUT symbol
"ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_60_mux00003
21" (Output Signal =
ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_mux0000[9])
LUT symbol
"ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_62_mux00003
11" (Output Signal =
ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_62_mux0000[8])
FLOP symbol
"ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_8" (Output
Signal = ctl_reg<;60><;8>)
FLOP symbol
"ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_9" (Output
Signal = ctl_reg<;60><;9>)
FLOP symbol
"ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_62_8" (Output
Signal = ctl_reg<;62><;8>)
The clock enable signals don't agree. Please correct the design
constraints accordingly.

Article: 129431
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: Bob Smith <usenet@linuxtoys.org>
Date: Sat, 23 Feb 2008 11:11:48 -0800
Links: << >>  << T >>  << A >>
morphiend wrote:
> On Feb 23, 3:06 am, Bob Smith <use...@linuxtoys.org> wrote:
>> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
>> of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
>> google hits on this did not help.
>>
>> It must be a simple mistake; any ideas what I'm doing wrong?
>> The "****" indicate the lines from the prototype that I've changed.


>> always @(posedge clkin)
>> begin
>>      count <= count + 1;
>> end
>>
>> assign clkout2 = count[4];

> I know this sounds like a simple answer, but have you checked your
> input clock? That was an issue I just had recently. My external
> oscillator was not generating its 100MHz signal.

Mike
     Thanks for the suggestion.  Yeah, the divide by 32 was a way
to prove that the clock is there.  The code (now snipped) builds
and seems to run fine but there's no output on CLKFX.

thanks
Bob

Article: 129432
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: PatC <pato@patocarr.com>
Date: Sat, 23 Feb 2008 12:37:54 -0800
Links: << >>  << T >>  << A >>
>>> assign clkout2 = count[4];
> 
>> I know this sounds like a simple answer, but have you checked your
>> input clock? That was an issue I just had recently. My external
>> oscillator was not generating its 100MHz signal.
> 
> Mike
>     Thanks for the suggestion.  Yeah, the divide by 32 was a way
> to prove that the clock is there.  The code (now snipped) builds
> and seems to run fine but there's no output on CLKFX.
> 
> thanks
> Bob

  Have you checked the locked output? if it's not locked, FX would not
output anything iirc, as opposed to clk0 which does regardless of lock.

-P@

Article: 129433
Subject: Re: scanf problem in EDk 9.1i (Microbaze)
From: PFC <lists@peufeu.com>
Date: Sat, 23 Feb 2008 22:47:06 +0100
Links: << >>  << T >>  << A >>
>> Hi ,
>>       I have assigned 64k of local memory.
>> Is there an alternative to this problem im facing.
>
> Allocate more memory or try iscanf, which is an integer only version
> of scanf, that should require less code space. (There should be
> iprintf too).
>
> Cheers,
> Jon

	scanf and printf are monsters - they do everything but there is a huge  
amount of code.
	also, the Microblaze code is not very compact.

	I needed to print and read some integers, so I just used simple functions  
that do just that. It should not take more than a couple hundred bytes...
	Something like this 1 minute example not guaranteed to work at all ;)

int fake_atoi( const char *c )
{
	int n = 0;
	while( isdigit( *c ))
		n = n*10 + (*c++ - '0');
	return n;
}

Article: 129434
Subject: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
From: Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid>
Date: Sat, 23 Feb 2008 23:10:10 +0100
Links: << >>  << T >>  << A >>
In comp.arch.fpga,
Mike Treseler <mike_treseler@comcast.net> wrote:
> Stef wrote:
>
>> I wanted an I/O buffer and that's what I got. I've read a lot here
>> about retiming the input signal so I added that. Not sure about the
>> output FF's though.
>
> They make it easier to meet timing in large processes.
> However I would never use a separate entity just to infer a buffer.

Never is such a big word. ;-)
In this particular case I might keep the entity, as it is only a
single bufffer at a rather important spot in the design. But in
general, I think it will be less messy just to incorporate then
in the existing processes.

>> Can't find an RTL viewer in my version of ISE (still on 8.2i).
>
> It might be worth your time to find it or upgrade.
> This is a valuable tool for learning and debugging.

Yes, I already downloaded 9.2i. I understand the value of the
tool, I had been looking for something like your quartus output
because I wanted to see what the tools did with myu code. I ended
up using the floor planner as a poor substitute.

>> On the other side of the "UART" I will need a bus interface to
>> a cpu. Adding all that delay there slows down the interface, so
>> I might need another approach.
>
> A uart does not require tri-state pins at all.

How would you handle the interface to an external cpu without tri-
state buffers? If you meant for the serial pin only, that's why I
quoted the word uart. Part of the design is a uart-like device.
Serial transmission will use BLVDS, half-duplex over an single 
pair.


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

"Computers in the future may weigh no more than 1.5 tons."
(Popular Mechanics, 1949)

Article: 129435
Subject: Re: How to use xilinx specific features from Modelsim Designer 6.3a
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 23 Feb 2008 15:14:36 -0800
Links: << >>  << T >>  << A >>
Stef wrote:

>>> I wanted an I/O buffer and that's what I got. I've read a lot here
>>> about retiming the input signal so I added that. Not sure about the
>>> output FF's though.

>> They make it easier to meet timing in large processes.
>> However I would never use a separate entity just to infer a buffer.

> Never is such a big word. ;-)
Yes, of course. The customer/boss is always right.

> In this particular case I might keep the entity, as it is only a
> single bufffer at a rather important spot in the design. But in
> general, I think it will be less messy just to incorporate then
> in the existing processes.

Yes. It might make sense to have
one design entity that converts the processor tristate
data bus to separate read and write data buses
on the fpga. Good luck.

 -- Mike Treseler


Article: 129436
Subject: Re: FPGA Editor Tutorial based on examples
From: sky465nm@trline5.org
Date: Sun, 24 Feb 2008 00:59:56 +0100 (CET)
Links: << >>  << T >>  << A >>
MikeShepherd564@btinternet.com wrote:
>>I am looking for some good in depth tutorial on FPGA Editor. I have
>>seen the video demos on youtube...

>Videos???

>YouTube???

>There has to be something wrong with the documentation of a product
>when people feel the need to explain it by making videos for YouTube.

You mean like not returning proper exit (error) values?, or crashing gui? :)

Article: 129437
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: JK <krishna.janumanchi@gmail.com>
Date: Sat, 23 Feb 2008 19:38:10 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 23, 1:06 pm, Bob Smith <use...@linuxtoys.org> wrote:
> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
> of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
> google hits on this did not help.


your DCM is missing reset, if I am not wrong.
I dont see any reset on your top level port list.
You are getting clkout2, because it is not depending on reset.

Please check.

Regards,
JK

Article: 129438
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: Bob Smith <usenet@linuxtoys.org>
Date: Sun, 24 Feb 2008 06:08:57 GMT
Links: << >>  << T >>  << A >>
JK wrote:
> your DCM is missing reset, if I am not wrong.
> I dont see any reset on your top level port list.
> You are getting clkout2, because it is not depending on reset.

Thanks for the suggestion.  I added a reset from a switch on the
board.  A reset does not seem to make any difference.


PatC wrote:
 >   Have you checked the locked output? if it's not locked, FX would not
 > output anything iirc, as opposed to clk0 which does regardless of lock.

Thanks for the suggestion.  I tied an LED on the board to the
locked status output.  The locked status never goes high (perhaps
as you suspected).   Any ideas why it won't lock?


JK and PatC, thanks both.

Bob Smith


Article: 129439
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: mng <michael.jh.ng@gmail.com>
Date: Sun, 24 Feb 2008 01:14:09 -0800 (PST)
Links: << >>  << T >>  << A >>
> PatC wrote:
>
>  >   Have you checked the locked output? if it's not locked, FX would not
>  > output anything iirc, as opposed to clk0 which does regardless of lock.
>
> Thanks for the suggestion.  I tied an LED on the board to the
> locked status output.  The locked status never goes high (perhaps
> as you suspected).   Any ideas why it won't lock?
>
> JK and PatC, thanks both.
>
> Bob Smith

See the line
.CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
*********

The DLL needs clock feedback to lock (and work). So try setting this
to 1X.

Article: 129440
Subject: canny edge detection
From: saran <rsvn29@gmail.com>
Date: Sun, 24 Feb 2008 01:39:45 -0800 (PST)
Links: << >>  << T >>  << A >>
hai.. i am doing project in image processing using cyclone II fpga...i
need the core of the canny edge detection for one of it's module..any
one can help me..

Article: 129441
Subject: Re: canny edge detection
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sun, 24 Feb 2008 11:03:09 +0000
Links: << >>  << T >>  << A >>
On Sun, 24 Feb 2008 01:39:45 -0800 (PST), saran wrote:

>hai.. i am doing project in image processing using cyclone II fpga...i
>need the core of the canny edge detection for one of it's module..any
>one can help me..

The smoothing and gradient operators are simple, standard 
2-D linear convolution and I'm sure your lecture notes 
have covered how to do that in some detail.

The peak-following edge tracker is a lot more troublesome 
in an FPGA because of its complicated addressing operations
and its many conditional choices;  if I were doing that, 
I'd probably use a softcore CPU.

Google for "canny edge detector" produced quite a lot of useful
stuff for me... maybe it doesn't work so well where you are?
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

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From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: FPGA Editor Tutorial based on examples
Newsgroups: comp.arch.fpga
Date: Sun, 24 Feb 2008 15:13:58 +0100
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maverick wrote:

> Hi,
> I am looking for some good in depth tutorial on FPGA Editor. I have
> seen the video demos on youtube but they just give you intro to the
> tool. There are so many tutorials available on other tools from Xilinx
> with examples but I could not find one on FPGA Editor. Any help in
> this regard will be appreciated.....
> regards
> Farhan


http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/ref=pd_bbs_sr_3?ie=UTF8&s=books&qid=1203862392&sr=8-3

Article: 129442
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: Bob Smith <usenet@linuxtoys.org>
Date: Sun, 24 Feb 2008 19:08:58 GMT
Links: << >>  << T >>  << A >>
mng wrote:
>>  >   Have you checked the locked output? if it's not locked, FX would not
>>  > output anything iirc, as opposed to clk0 which does regardless of lock.

> 
> See the line
> .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
> *********
> 
> The DLL needs clock feedback to lock (and work). So try setting this
> to 1X.


Michael,
   Thanks for the suggestion.  Changing the feedback to 1X did not make
a difference although it builds fine.   I could have sworn that using
1X in an earlier attempt gave me an error saying that frequency synthesis
needed NONE.  The Spartan 3 Users Guide (pg 70) says kind of the same
thing.

thanks
Bob Smith

Article: 129443
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: PatC <pato@patocarr.com>
Date: Sun, 24 Feb 2008 12:53:45 -0800
Links: << >>  << T >>  << A >>
Bob Smith wrote:
> JK wrote:
>> your DCM is missing reset, if I am not wrong.
>> I dont see any reset on your top level port list.
>> You are getting clkout2, because it is not depending on reset.
> 
> Thanks for the suggestion.  I added a reset from a switch on the
> board.  A reset does not seem to make any difference.
> 
> 
> PatC wrote:
>>   Have you checked the locked output? if it's not locked, FX would not
>> output anything iirc, as opposed to clk0 which does regardless of lock.
> 
> Thanks for the suggestion.  I tied an LED on the board to the
> locked status output.  The locked status never goes high (perhaps
> as you suspected).   Any ideas why it won't lock?

Since your code sample is snipped, I don't see the BUFG connecting clk0
to clkfb. If you are using clock feedback 1x, this is how it should be
connected. Without this feedback, it won't lock.

-P@

Article: 129444
Subject: Re: Problem with PINs XC3S700A-4FG484
From: jkljljklk <maricic@gmail.com>
Date: Sun, 24 Feb 2008 13:12:54 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 22, 8:12 pm, Fei Liu <fei....@gmail.com> wrote:
> In the quick start tutorial, it says connect DIRECTION with PIN K13 (SW7
> signal on board), but after browsing through ug300.pdf and s3a
> schematics, I don't see anything that remotely makes sense. I understand
> I need a input signal, but I have no idea which PIN would give me that
> on S3A board.
>
> Here is my vhdl source:
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity counter is
>     Port ( CLOCK : in  STD_LOGIC;
>            DIRECTION : in  STD_LOGIC;
>            COUNT_OUT : out  STD_LOGIC_VECTOR (3 downto 0));
> end counter;
>
> architecture Behavioral of counter is
> signal count_int : std_logic_vector(3 downto 0) := "0000";
> begin
>
> process (CLOCK)
> begin
>    if CLOCK='1' and CLOCK'event then
>       if DIRECTION='1' then
>          count_int <= count_int + 1;
>       else
>          count_int <= count_int - 1;
>       end if;
>    end if;
> end process;
> COUNT_OUT <= count_int;
>
> end Behavioral;

Did you mean ug130.pdf instead of ug300.pdf? If so, K13 pin on the
FPGA chip is connected to the switch SW7. This means that you need to
assign your DIRECTION input to K13 in your constraints file (edit ucf
file).

Dan

Article: 129445
Subject: Re: Problem with PINs XC3S700A-4FG484
From: jkljljklk <maricic@gmail.com>
Date: Sun, 24 Feb 2008 13:16:26 -0800 (PST)
Links: << >>  << T >>  << A >>
> Hello Dan, my board is S3A described in ug330.pdf. In ug330.pdf Fig 2-1
> there is no SW7. Also I have no idea how to control it, do I have to
> manually push it up and down? I have 4 push button switch T14,15,16 and
> U15 in Fig 2-5.
>
> The quick start tutorial in qst.pdf uses a S3 board.
>
> Fei

Yes, you have to control the switches and pushbuttons on the board
manually.

Article: 129446
Subject: Re: Problem with PINs XC3S700A-4FG484
From: Fei Liu <fei.liu@gmail.com>
Date: Sun, 24 Feb 2008 19:11:22 -0500
Links: << >>  << T >>  << A >>
jkljljklk wrote:
>> Hello Dan, my board is S3A described in ug330.pdf. In ug330.pdf Fig 2-1
>> there is no SW7. Also I have no idea how to control it, do I have to
>> manually push it up and down? I have 4 push button switch T14,15,16 and
>> U15 in Fig 2-5.
>>
>> The quick start tutorial in qst.pdf uses a S3 board.
>>
>> Fei
> 
> Yes, you have to control the switches and pushbuttons on the board
> manually.

I see, many thanks. I guess I can use either of the manual switch to
control DIRECTION. One thing I don't understand is that the clock is
50MHz and my timing constraints is only a few macro seconds. I wonder
how I can control DIRECTION that fast by manually pushing the switch.

Fei

Article: 129447
Subject: more microblaze firmware blues. tool chain version problem?
From: chrisdekoh@gmail.com
Date: Sun, 24 Feb 2008 16:16:17 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all,
    I am currently working on porting some code on microblaze from a
spartan 3 FPGA to a virtex 2 pro FPGA for expansion reasons. The code
which really works on a spartan 3 FPGA, just somehow does not seem to
work on the virtex 2 pro. Here are some details:

1) for the spartan 3 FPGA, I used both EDK9.1i+ISE 7.1i and EDK9.2i
+ISE9.2i
    the same firmware running on the spartan works fine.
2) I ported exactly the same architecture + firmware + EDK9.1i, since
EDK9.2i does not support virtex 2 pro yet. which is really
disappointing
3) my hardware architecture is like this; the hardware peripherals are

when using EDK9.2i and spartan 3
- microblaze v7.0 with plb bus
- a UART peripheral, modified to perform hardware handshaking
- this works fine

when using EDK7.1i and spartan 3
- microblaze v4.0 with opb bus
-a UART peripheral, modified to perform hardware handshaking
- this works fine

when using EDK9.1i and virtex 2 pro
- microblaze 6.0
- a UART peripheral, modified to perform hardware handshaking
- this does not work, the algo does not return correct data at all.

4) my software design flow looks like the one below. No interrupt is
used.

int main(){
    get_params(); //get data from UART using blocking statements
    start_algo(); //to start algo
     return_result(); //return results back to PC via UART.
}

void start_algo(){
  // I inserted a breakpoint around here.
  ...the rest of the algo....
}


5) I have tested that
int main(){
    get_params(); //get data from UART using blocking statements
     return_result(); //return results back to PC via UART.
}

works. So the problem is not with the UART data transfer.

6) how i know it does not work
a) wrong data is sent back from the virtex 2 pro board back to PC.
b) when I sent the compilation switch to no optimisation, the problem
gets worse. No data is sent back at all to PC.
again to iterate, the same firmware works on spartan 3, using EDK9.2i
(microblaze 7) and EDK7.1i (microblaze 4). now, it does not work on
EDK9.1i (microblaze 6).

if things are not already bad enough, when doing debugging using the
mdm hardware debugger, stepping sometimes already results in the
program jumping to some other routine that does not correspond to the
software flow. I am equally cluelss about this.

this subject is related to one that i posted 2 weeks ago. the topic is
"microblaze firmware + UART handshaking blues"

I have modifed to make sure that the stack size is 0x1000. What else
could have gone wrong?

any help on this will be greatly appreciated.

thanks a million.
Chris

Article: 129448
Subject: Re: scanf problem in EDk 9.1i (Microbaze)
From: MAx <mahesh1280@gmail.com>
Date: Sun, 24 Feb 2008 21:32:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 24, 2:47=A0am, PFC <li...@peufeu.com> wrote:
> >> Hi ,
> >> =A0 =A0 =A0 I have assigned 64k of local memory.
> >> Is there an alternative to this problem im facing.
>
> > Allocate more memory or try iscanf, which is an integer only version
> > of scanf, that should require less code space. (There should be
> > iprintf too).
>
> > Cheers,
> > Jon
>
> =A0 =A0 =A0 =A0 scanf and printf are monsters - they do everything but the=
re is a huge =A0
> amount of code.
> =A0 =A0 =A0 =A0 also, the Microblaze code is not very compact.
>
> =A0 =A0 =A0 =A0 I needed to print and read some integers, so I just used s=
imple functions =A0
> that do just that. It should not take more than a couple hundred bytes...
> =A0 =A0 =A0 =A0 Something like this 1 minute example not guaranteed to wor=
k at all ;)
>
> int fake_atoi( const char *c )
> {
> =A0 =A0 =A0 =A0 int n =3D 0;
> =A0 =A0 =A0 =A0 while( isdigit( *c ))
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 n =3D n*10 + (*c++ - '0');
> =A0 =A0 =A0 =A0 return n;
>
>
>
> }- Hide quoted text -
>
> - Show quoted text -

Hi,
     Didnt find iscanf in the library. very reluctatntly chose reading
in the number a digit at a time using
XUartLite_RecvByte into an array and then converted that array to a
number...

hope it holds well during the demo

Thanks guys
MAx

Article: 129449
Subject: Re: more microblaze firmware blues. tool chain version problem?
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 24 Feb 2008 23:04:28 -0800 (PST)
Links: << >>  << T >>  << A >>
On 25 Feb., 01:16, chrisde...@gmail.com wrote:
> Hi all,
>     I am currently working on porting some code on microblaze from a
> spartan 3 FPGA to a virtex 2 pro FPGA for expansion reasons. The code
> which really works on a spartan 3 FPGA, just somehow does not seem to
> work on the virtex 2 pro. Here are some details:
>
> 1) for the spartan 3 FPGA, I used both EDK9.1i+ISE 7.1i and EDK9.2i
> +ISE9.2i
>     the same firmware running on the spartan works fine.
> 2) I ported exactly the same architecture + firmware + EDK9.1i, since
> EDK9.2i does not support virtex 2 pro yet. which is really
> disappointing
> 3) my hardware architecture is like this; the hardware peripherals are
>
> when using EDK9.2i and spartan 3
> - microblaze v7.0 with plb bus
> - a UART peripheral, modified to perform hardware handshaking
> - this works fine
>
> when using EDK7.1i and spartan 3
> - microblaze v4.0 with opb bus
> -a UART peripheral, modified to perform hardware handshaking
> - this works fine
>
> when using EDK9.1i and virtex 2 pro
> - microblaze 6.0
> - a UART peripheral, modified to perform hardware handshaking
> - this does not work, the algo does not return correct data at all.
>
> 4) my software design flow looks like the one below. No interrupt is
> used.
>
> int main(){
>     get_params(); //get data from UART using blocking statements
>     start_algo(); //to start algo
>      return_result(); //return results back to PC via UART.
>
> }
>
> void start_algo(){
>   // I inserted a breakpoint around here.
>   ...the rest of the algo....
>
> }
>
> 5) I have tested that
> int main(){
>     get_params(); //get data from UART using blocking statements
>      return_result(); //return results back to PC via UART.
>
> }
>
> works. So the problem is not with the UART data transfer.
>
> 6) how i know it does not work
> a) wrong data is sent back from the virtex 2 pro board back to PC.
> b) when I sent the compilation switch to no optimisation, the problem
> gets worse. No data is sent back at all to PC.
> again to iterate, the same firmware works on spartan 3, using EDK9.2i
> (microblaze 7) and EDK7.1i (microblaze 4). now, it does not work on
> EDK9.1i (microblaze 6).
>
> if things are not already bad enough, when doing debugging using the
> mdm hardware debugger, stepping sometimes already results in the
> program jumping to some other routine that does not correspond to the
> software flow. I am equally cluelss about this.
>
> this subject is related to one that i posted 2 weeks ago. the topic is
> "microblaze firmware + UART handshaking blues"
>
> I have modifed to make sure that the stack size is 0x1000. What else
> could have gone wrong?
>
> any help on this will be greatly appreciated.
>
> thanks a million.
> Chris

you are not the only one having GCC/UART/EDK blues

1) with some GCC version it has been necessarry to add

call_some_really_dummy_do_nothing();

2) sometimes it is needed to add

wait_some_real_time();

at the start of main() or first UART output will not appear

3) if using EDK 9.1 then if the BRAM is made up of 2 or more
BRAM blocks then there is no tool error reported, but
the second BRAM does not get initialized with code, so if
the algorithm spans into second BRAM it will fail with
different behaviour depending on optimization setting

4) some other issues are also possible of course
5)
6)..

Antti Lukats




















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