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Messages from 129675

Article: 129675
Subject: Re: FPGA/CPLD group on LinkedIn
From: John_H <newsgroup@johnhandwork.com>
Date: Sun, 02 Mar 2008 21:45:35 -0800
Links: << >>  << T >>  << A >>
wmwmurray@gmail.com wrote:
> On Mar 2, 3:15 pm, sky46...@trline5.org wrote:
>> wmwmur...@gmail.com wrote:
>>> FPGA/CPLD group on LinkedIn
>>>    http://www.linkedin.com/e/gis/56713/3CC3BF77FD22
>>> Group for People Involved In the Design and Verification of FPGA's and
>>> CPLD's to Exchange Idea's and Techniques.  You should have FPGA/CPLD
>>> Design/Verification on your Profile to Join.  (The focus is more on
>>> FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
>>> ASIC)
>> I prefer NNTP over webbforums that is pumped full of the latest webb-fad from
>> the webmaster. Thread structure often missing.
> 
> The one big advantage is that joining the group allows one to search
> the members CV's and look for a few people to ask for a one-on-one
> answer to something that they are familiar with.  It also allows one
> to build contacts in an area of interest, that one might not otherwise
> meet.  Hope this helps with why I started the group.  There are other
> reasons to join beyond this as well -- will save for later -- both
> NNTP, and LinkedIn can be useful tools

I enjoy helping people out when information or insights from my own 
experience can help others and I certainly like the exposure I get to 
different ideas and tools I rarely (or don't) use.

I certainly don't need one-on-one conversations brought up by people who 
don't want to make their questions and pursuits more public.

There are too many people asking others to do their work for them as it 
is whether educational or professional.  Too many want something for 
nothing.  In an open forum, maybe someone will oblige.  Random emails 
from unfamiliar names are NOT appreciated from where I sit.

You've given me reason enough not to even look to see what the board 
might offer.

- John_H

Article: 129676
Subject: Re: Software for FPGA-based PC scope
From: Jeff Cunningham <jcc@sover.net>
Date: Mon, 03 Mar 2008 00:46:06 -0500
Links: << >>  << T >>  << A >>
Nico Coesel wrote:

>> Actually, IMHO it is a very serious response. I worked on a project 
>> where the software was over a year late due in large part to 
>> misunderstandings about what Visual Basic could do.
> 
> Which in turn is probably caused by lack of experience. So any
> language would have caused the project te be delayed by a year. Hiring
> better programmers would have been the sensible thing to do. The way I
> see it a programmer is like a tool. 'It' does something well when
> operating within its capabilities (=language known best).

Fair enough. Let me just say that for a task involving hardware 
synchronization and low level realtime functions (like a FPGA based PC 
scope), VB is probably a poor tool.

Article: 129677
Subject: Re: real to signed
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Sun, 2 Mar 2008 22:19:33 -0800 (PST)
Links: << >>  << T >>  << A >>
On 29 Feb., 15:46, FPGA <FPGA.unkn...@gmail.com> wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it. I have searched on the internet and
> did not find any valuable information.

Start with understanding what a real is:
http://en.wikipedia.org/wiki/IEEE_754-1985
Than it is easy to write your conversion function.

bye Thomas

Article: 129678
Subject: Re: Is there any way to disable JTAG for Sptantan3AN
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 2 Mar 2008 22:27:11 -0800 (PST)
Links: << >>  << T >>  << A >>
On 3 Mrz., 05:48, Goli <tog...@gmail.com> wrote:
> On Feb 29, 2:34 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On 29 Feb., 09:59, waltherz <walther.za...@gmx.de> wrote:
>
> > > ofcourse u can. just ground them!
>
> > > j...@amontec.com schrieb:
>
> > > > On Feb 29, 4:52 am, Goli <tog...@gmail.com> wrote:
> > > > > Hi,
>
> > > > > We want to make Spartan3AN as One Time Programmable. We want to
> > > > > program it once and then disable JTAG.
> > > > > Is it possible to do that? How can we do that?
>
> > > > > --
> > > > > Goli
>
> > > > You cannot disable the JTAG !
>
> > > > and why do you want to remove the powerful JTAG link from your board
> > > > application ?
> > > > One Time Programmable = Not Upgradeable System !
>
> > > > Larry
> > > >  http://www.amontec.com
>
> > that doesnt prevent the JTAG being used if the chip is desoldered...
> > so it really isnt disabling the JTAG just making it harder to access
>
> > lso when the S3AN are to be programmed before sending to assembly fab?
>
> > Antti
>
> I do agree that there are ways on board with which you can make it
> very difficult for other people to use JTAG. But I was wondering if
> there is any solution to make the FPGAs as OTP (One time
> Programmable). I think for Spartan XL FPGAs we used to get OTP Proms.
> So was wondering if there is any similar solution for Spartan3AN.
>
> --
> Goli

the internal FLASH of S3AN does have OTP write protect fuse.
so if you set that protection then the S3AN internal memory comes read
only
but it will not prevent configuration by other means

Antti



Article: 129679
Subject: Virtex-5 FXT coming soon?
From: Antti <Antti.Lukats@googlemail.com>
Date: Sun, 2 Mar 2008 23:56:52 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

the fact that forum posting about ML507 was removed by Xilinx
moderator (from Xiliinx forums), gives us at least the information
that ML507 is a Virtex-5FXT development board. This should mean that
the FXT silicon will soon be announced. Sure many of us hoped FXT some
years ago already.

Antti

Article: 129680
Subject: Re: Virtex-5 FXT coming soon?
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Mon, 3 Mar 2008 00:28:52 -0800 (PST)
Links: << >>  << T >>  << A >>
I talked to Xilinx at the embedded world in N=FCrnberg about that.

There are samples available know for special customers now.
To mortals like us the FXT samples will be available in a few months.
There will be no FX without power PC.
At least some FXT will be almost pin compatible to LXT devices.

Kolja

On 3 Mrz., 08:56, Antti <Antti.Luk...@googlemail.com> wrote:
> Hi,
>
> the fact that forum posting about ML507 was removed by Xilinx
> moderator (from Xiliinx forums), gives us at least the information
> that ML507 is a Virtex-5FXT development board. This should mean that
> the FXT silicon will soon be announced. Sure many of us hoped FXT some
> years ago already.
>
> Antti


Article: 129681
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: samonestopva@gmail.com
Date: Mon, 3 Mar 2008 00:29:09 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 27, 12:30 am, Bob Smith <use...@linuxtoys.org> wrote:

> Thanks, John.  The Spartan User's Guide talked about the clock
> wizard but it is a Windows only feature so I've not been able
> to try it since I sit at a Linux box.   My original post was
> wrong in that I said I have a Spartan 3E.  In fact it is just
> a Spartan 3.  I removed the "_SP" references to change from a
> 3E to a 3 and it compiled correctly.   Sad to say there's still
> no output except on the divide-by-32 counter output.
>
> I'll try simulating the DCM this weekend when I can spend more
> time on it.
>
> Thanks very much for posting the wizard output.
>
> Bob Smith

Bob! I am using the Spartan 3E, and have been dealing with the exact
same situation
as you have, for the entire weekend!!! Just now after reading all of
your attempts and thoughts
I got it working!
I was careful to notice when you would follow up on all of the
suggestions, and that
helped me to speed up by skipping the ones that you already tried for
me!! :)

BUT !!! There was one suggestion that I thought sounded good, but you
replied to 3
suggestions at once, and kind of missed the RST comment.  I put a
reset delay counter
at the beginning of the code to be sure the "clkin" frequency has
already been adjusted
and stablized.  My board changes the default from 12Mhz to 24Mhz from
an EEPROM
sometime near startup, so I added about a 1 second delay keeping RST
high during
that period, then dropping once the initial delay was complete and
finally I got my LED
to flash on the CLKFX output clock counter !!!!

Sorry for the excitement, but when I saw that little LED flashing and
double checked
the code, it felt really satisfying if you know what I mean! Hope the
same solution
works for you !!

Sam

Article: 129682
Subject: Re: real to signed
From: Tricky <Trickyhead@gmail.com>
Date: Mon, 3 Mar 2008 01:08:43 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 29, 6:33 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> On Feb 29, 11:29 am, Tricky <Trickyh...@gmail.com> wrote:
>
> > On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > How to convert real to signed. The range of real will be from -1 to 1,
> > > -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> > > signed vector of bit width bw(generic). The data has to be scaled but
> > > I have no idea on how to do it. I have searched on the internet and
> > > did not find any valuable information.
>
> > You will need to know magnitude width and fraction width as you will
> > be generating a fixed point decimal.
> > Magnitude width (MW) can be done by taking log2(limit) and adding 1
> > (to account for the sign bit).
>
> MW and FW of  output real changes with change in amplitude. What is
> 'limit'?
>
> > Fraction width (FW) is then bw-MW.
>
> > Then you scale the result by 2**FW and convert it to an integer (which
> > then gives you your signed number).
> > Remember Integer(my_real) always rounds to nearest. If you dont want
> > to round to nearest, you have to write a function that rounds to zero,
> > otherwise removing the LSBs will always round down. (towards 0 for
> > +ve, away from 0 for -ve).

You are ignoring what the MW and FW lengths of the real are, because
it uses neither. For a real, which is floating point, its not
magnitude and fraction widths, its mantissa and exponent. You are
specified what YOU want the real to fit in to. You are making a FIXED
POINT decimal value, so MW and FW never change. for example:

from 3 to -3

you need MW = 3  (1 sign bit an 1 other bit)
FW = how ever many you want. each bit represets 2^-n (with n=0 to the
left of the imaginary point)

so 0.75 is represended by:  000.1100000 = 2^-1 (0.5) + 2^-2 (0.25)
1.75 = 001.11000000  = 2^0 (1) + 2^-1 (0.5) + 2^-2 (0.25)
-1.75 = 110.01111111 (invert all bits and add one to number above)
etc
etc
All values are 2s compliment, and can then be used in any standard
adder, multiplier etc on firmware. Just make sure you use the correct
bits of the result:

a 2.6 number x 6.2 number = 8.8 result

              a a . a a a a a a
      b b b b b b . b b
= r r r r r r r r . r r r r r r r r

Article: 129683
Subject: Re: Virtex-5 FXT coming soon?
From: Antti <Antti.Lukats@googlemail.com>
Date: Mon, 3 Mar 2008 02:20:58 -0800 (PST)
Links: << >>  << T >>  << A >>
On 3 Mrz., 09:28, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> I talked to Xilinx at the embedded world in N=FCrnberg about that.
>
> There are samples available know for special customers now.
> To mortals like us the FXT samples will be available in a few months.
> There will be no FX without power PC.
> At least some FXT will be almost pin compatible to LXT devices.
>
> Kolja
>
> On 3 Mrz., 08:56, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > Hi,
>
> > the fact that forum posting about ML507 was removed by Xilinx
> > moderator (from Xiliinx forums), gives us at least the information
> > that ML507 is a Virtex-5FXT development board. This should mean that
> > the FXT silicon will soon be announced. Sure many of us hoped FXT some
> > years ago already.
>
> > Antti

Hi Kolja

eh I was so busy at embedded while demonstrating the portable XSVF
player
(well at Atmel i said its AVR ISP programmer of course) and talking to
you
that I totally forgot to ask anything at Xilinx stand :)

but if RAD HARD V5FX are expected end of the year, then I would have
very firm thumb guess that FX samples are there NOW, and possible
have been delivered to some special customers some while ago.

but as the V5FX has been delaying so long, I have almost lost interest
to follow up how much longer it is delaying in reality...

The Spartan-4 is much more interesting, but I guess there is much
leaked out yet,
except rumors that we might expect more on chip special functions --
USB anyone??

Antti



Article: 129684
Subject: Re: Is there any way to disable JTAG for Sptantan3AN
From: Bert <bert.maarsen@nl.thalesgroup.com>
Date: Mon, 3 Mar 2008 02:54:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On 3 mrt, 07:27, Antti <Antti.Luk...@googlemail.com> wrote:
> On 3 Mrz., 05:48, Goli <tog...@gmail.com> wrote:
>
>
>
>
>
> > On Feb 29, 2:34 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On 29 Feb., 09:59, waltherz <walther.za...@gmx.de> wrote:
>
> > > > ofcourse u can. just ground them!
>
> > > > j...@amontec.com schrieb:
>
> > > > > On Feb 29, 4:52 am, Goli <tog...@gmail.com> wrote:
> > > > > > Hi,
>
> > > > > > We want to make Spartan3AN as One Time Programmable. We want to
> > > > > > program it once and then disable JTAG.
> > > > > > Is it possible to do that? How can we do that?
>
> > > > > > --
> > > > > > Goli
>
> > > > > You cannot disable the JTAG !
>
> > > > > and why do you want to remove the powerful JTAG link from your boa=
rd
> > > > > application ?
> > > > > One Time Programmable =3D Not Upgradeable System !
>
> > > > > Larry
> > > > > =A0http://www.amontec.com
>
> > > that doesnt prevent the JTAG being used if the chip is desoldered...
> > > so it really isnt disabling the JTAG just making it harder to access
>
> > > lso when the S3AN are to be programmed before sending to assembly fab?=

>
> > > Antti
>
> > I do agree that there are ways on board with which you can make it
> > very difficult for other people to use JTAG. But I was wondering if
> > there is any solution to make the FPGAs as OTP (One time
> > Programmable). I think for Spartan XL FPGAs we used to get OTP Proms.
> > So was wondering if there is any similar solution for Spartan3AN.
>
> > --
> > Goli
>
> the internal FLASH of S3AN does have OTP write protect fuse.
> so if you set that protection then the S3AN internal memory comes read
> only
> but it will not prevent configuration by other means
>
> Antti- Tekst uit oorspronkelijk bericht niet weergeven -
>
> - Tekst uit oorspronkelijk bericht weergeven -

Hi,

If design security is an issue consider Actel iso. Xilinx Spartan or
other Xilinx devices with AES protection ....

Bert.

Article: 129685
Subject: Re: Is there any way to disable JTAG for Sptantan3AN
From: Antti <Antti.Lukats@googlemail.com>
Date: Mon, 3 Mar 2008 03:15:31 -0800 (PST)
Links: << >>  << T >>  << A >>
On 3 Mrz., 11:54, Bert <bert.maar...@nl.thalesgroup.com> wrote:
> On 3 mrt, 07:27, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On 3 Mrz., 05:48, Goli <tog...@gmail.com> wrote:
>
> > > On Feb 29, 2:34 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > On 29 Feb., 09:59, waltherz <walther.za...@gmx.de> wrote:
>
> > > > > ofcourse u can. just ground them!
>
> > > > > j...@amontec.com schrieb:
>
> > > > > > On Feb 29, 4:52 am, Goli <tog...@gmail.com> wrote:
> > > > > > > Hi,
>
> > > > > > > We want to make Spartan3AN as One Time Programmable. We want to
> > > > > > > program it once and then disable JTAG.
> > > > > > > Is it possible to do that? How can we do that?
>
> > > > > > > --
> > > > > > > Goli
>
> > > > > > You cannot disable the JTAG !
>
> > > > > > and why do you want to remove the powerful JTAG link from your board
> > > > > > application ?
> > > > > > One Time Programmable = Not Upgradeable System !
>
> > > > > > Larry
> > > > > >  http://www.amontec.com
>
> > > > that doesnt prevent the JTAG being used if the chip is desoldered...
> > > > so it really isnt disabling the JTAG just making it harder to access
>
> > > > lso when the S3AN are to be programmed before sending to assembly fab?
>
> > > > Antti
>
> > > I do agree that there are ways on board with which you can make it
> > > very difficult for other people to use JTAG. But I was wondering if
> > > there is any solution to make the FPGAs as OTP (One time
> > > Programmable). I think for Spartan XL FPGAs we used to get OTP Proms.
> > > So was wondering if there is any similar solution for Spartan3AN.
>
> > > --
> > > Goli
>
> > the internal FLASH of S3AN does have OTP write protect fuse.
> > so if you set that protection then the S3AN internal memory comes read
> > only
> > but it will not prevent configuration by other means
>
> > Antti- Tekst uit oorspronkelijk bericht niet weergeven -
>
> > - Tekst uit oorspronkelijk bericht weergeven -
>
> Hi,
>
> If design security is an issue consider Actel iso. Xilinx Spartan or
> other Xilinx devices with AES protection ....
>
> Bert.

Bert,

1) Design change from Xilinx to Actel may cause many man-months of
struggle.
2) Field updates of Actel FPGA are only secure for non M7/M1 devices.
Any design that updates on field Actel M7/M1 silicon has design theft
security equal to NIL VOID ZERO
3) Lattice ECP2 have non-volatile AES key, making them best candidate
if design security/theft is of concern, also the design migration from
Xilinx to Lattice is much much more easier then Xilinx to Actel

Antti

Article: 129686
Subject: Re: Random Number Generation in VHDL
From: Aragorn <me.aragorn@gmail.com>
Date: Mon, 3 Mar 2008 04:01:31 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi
  I am new to this group. I am an undergraduate student working on an
implementation of RSA on an FPGA. I am using a LFSR for random number
generation, but I also need a random state of the LFSR to begin with,
don't I? How do I get that? What does one do in such a case? I don't
want to restart the whole random no. generation business with a new
method!!

I want the user to get a different key each time he uses the key
generation system.

Thanks

Article: 129687
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: JK <krishna.janumanchi@gmail.com>
Date: Mon, 3 Mar 2008 04:22:39 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 3, 1:29=A0pm, samonesto...@gmail.com wrote:
> and stablized. =A0My board changes the default from 12Mhz to 24Mhz from
> an EEPROM
> sometime near startup, so I added about a 1 second delay keeping RST
> high during
> that period, then dropping once the initial delay was complete and
> finally I got my LED
> to flash on the CLKFX output clock counter !!!!
>

You need to monitor LOCKED output. When the DCM loses lock, reset
should be asserted for a period equal to or greater than 3 valid CLKIN
cycles.

Regards,
JK

Article: 129688
Subject: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
From: "Göran Bilski" <goran.bilski@xilinx.com>
Date: Mon, 3 Mar 2008 13:25:23 +0100
Links: << >>  << T >>  << A >>
Hi,

Could you try the latest patch for MicroBlaze 
http://www.xilinx.com/support/answers/30051.htm ?
It includes fixes which SP2 don't have.

Göran Bilski

<Remy.thomas.38@gmail.com> wrote in message 
news:5edea62c-648b-4a1f-b141-948bd4116cc8@v3g2000hsc.googlegroups.com...
The Service Pack 2 is already installed and i use the Microblaze
7.00.b

Rémy 



Article: 129689
Subject: Re: FPGA/CPLD group on LinkedIn
From: rickman <gnuarm@gmail.com>
Date: Mon, 3 Mar 2008 04:50:48 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 2, 7:19 pm, wmwmur...@gmail.com wrote:
> On Mar 2, 3:15 pm, sky46...@trline5.org wrote:
>
> > wmwmur...@gmail.com wrote:
> > >FPGA/CPLD group on LinkedIn
> > >    http://www.linkedin.com/e/gis/56713/3CC3BF77FD22
> > >Group for People Involved In the Design and Verification of FPGA's and
> > >CPLD's to Exchange Idea's and Techniques.  You should have FPGA/CPLD
> > >Design/Verification on your Profile to Join.  (The focus is more on
> > >FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
> > >ASIC)
>
> > I prefer NNTP over webbforums that is pumped full of the latest webb-fad from
> > the webmaster. Thread structure often missing.
>
> The one big advantage is that joining the group allows one to search
> the members CV's and look for a few people to ask for a one-on-one
> answer to something that they are familiar with.  It also allows one
> to build contacts in an area of interest, that one might not otherwise
> meet.  Hope this helps with why I started the group.  There are other
> reasons to join beyond this as well -- will save for later -- both
> NNTP, and LinkedIn can be useful tools

A friend of mine used to visit the Yahoo stock message boards which,
if you have ever looked at them, are full of crap and a lot of people
with bad attitudes.  They are a bit like adolescent punks spraying
graffiti on your computer screen.  My friend was following a stock in
its message board and someone posted that they had just started
following this stock and asked if anyone had some advice.  What he got
was a litany of rude remarks, personal insults and comments about his
heritage.  Then one other poster asked "How do you like the welcome
wagon"!

Sometimes this group is a bit like that.  Instead of just allowing
your post to go without comment, you got posts explaining personal
reasons for not wanted to visit any web based forum.  I have no idea
why they felt the need to make their posts.  They don't seem to be
trying to convince others that they should not visit the group.  They
just felt the need to post a personal opinion.  Ok, it's a free
Internet.

Just so you don't think everyone here is against your idea, I had
already joined because I saw it listed on LinkedIn.  I find Yahoo
forums to be very valuable, mostly because they can be very
specifically targeted.  There are lots of people here who are happy to
respond to a reply, but not everyone likes this format.  Certainly
there is room in the Internet for both this group and a Yahoo group.

See you there!




Article: 129690
Subject: Re: FPGA/CPLD group on LinkedIn
From: rickman <gnuarm@gmail.com>
Date: Mon, 3 Mar 2008 05:01:42 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 3, 7:50 am, rickman <gnu...@gmail.com> wrote:
> Just so you don't think everyone here is against your idea, I had
> already joined because I saw it listed on LinkedIn.  I find Yahoo
> forums to be very valuable, mostly because they can be very
> specifically targeted.  There are lots of people here who are happy to
> respond to a reply, but not everyone likes this format.  Certainly
> there is room in the Internet for both this group and a Yahoo group.

Opps, I got my groups mixed up.  I was talking about a Yahoo group and
you are talking about the LinkedIn group.

It's still early here.  :)


Article: 129691
Subject: Re: FPGA/CPLD group on LinkedIn
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 3 Mar 2008 14:56:54 -0000
Links: << >>  << T >>  << A >>
rickman wrote:
>
> Sometimes this group is a bit like that.  Instead of just allowing
> your post to go without comment, you got posts explaining personal
> reasons for not wanted to visit any web based forum.  I have no idea
> why they felt the need to make their posts.  They don't seem to be
> trying to convince others that they should not visit the group.  They
> just felt the need to post a personal opinion.  Ok, it's a free
> Internet.
>
Hi Rick,
I've no idea why, but I feel the need to thank you for posting your personal 
opinion! ;-)
Cheers, Syms. 



Article: 129692
Subject: Re: Xilinx DCM for frequency synthesis -- newbie question
From: samonestopva@gmail.com
Date: Mon, 3 Mar 2008 07:09:46 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 25, 5:55 am, Rob <BertyBoos...@googlemail.com> wrote:

> Without a RST input you also need to be careful that the clock is
> running and stable before configuration. Any change in the input clock
> requires RST to be asserted.
> I'm also not sure that the LOCKED pin should go high, since the
> datasheet states that this is asserted when CLKIN and CLKFB are in
> phase, which of course will never happen in this configuration.
>
> Cheers
> Rob


This was the best comment with precise and accurate statements from
the documentation. A lot of other people give suggestions too but some
didn't give from the documentation, just they make it up. Good job
Rob!!!

Ciao for now,
Sam

Article: 129693
Subject: Re: clock generation
From: Dave Pollum <vze24h5m@verizon.net>
Date: Mon, 3 Mar 2008 07:19:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 2, 9:28 am, sriman <srima...@gmail.com> wrote:
> hi
>
> i have a basic doubt in fpga implementation. i am new to this. i have
> made a stepper motor controller and implenting it on a DE1 board. i
> have no problem in simulation. everything is working fine.
> when i am about to program it onto board, i have to do pin
> assignments. i have a clock signal and control signals as input and
> drive pulses as output. while doing pin assignments on the board i
> have given the outputs onto the I/O pins of the board. inoder to give
> a clock signal input for my program i have use a inbuilt 50Mhz signal.
> it is having a value=PIN_L1. i have given it. but that signal is not
> taken by the program when implementing on the borad
>
> so what i need is how to give a clock signal. cant i use that inbuilt
> clocks on the board.?
>
> my board supports 24Mhz, 27Mhz and 50 Mhz

I'm not familiar with this board, but I assume that it comes with demo
HDL code (VHDL or Verilog) to read switches and light the LEDs, etc.
Run any demos that use the built-in clocks.  If they run OK, then
there is something wrong with your HDL code.
HTH
-Dave Pollum

Article: 129694
Subject: Re: Software for FPGA-based PC scope
From: Itandian@gmail.com
Date: Mon, 3 Mar 2008 07:25:15 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 28, 7:07=A0am, Vagant <vladimir.v.koroste...@rambler.ru> wrote:
> Hello,
>
> Although I am a newbie in FPGA design and have experience only with
> some simple designs so far, I am thinking of some more ambitious
> project and want to design a FPGA-based PC scope working in Windows
> XP.
> Let's assume that I know how to program (in VHDL) and implement this
> on FPGA. Then I will need to write software for this and I need advice
> about it. What software such project will require and what development
> tools I will need to write such software? May I write this in C++
> Builder or Visual Basic or I will need some lower level programming?
> So, my question is very general and I would appreciate your advice
> which I need to start up with this since on my own I just feel stuck
> about software for my project.

Sounds like you have not heard of the altera NiosII and their free dev
tools. Sorry Xilinx people. Anyhow, you can write your for the FPGA in
any RTL language like you said, and you can also use any windows
language you want on your PC. The thing is you can only use C or C++
(as far as I know) on the FPGA side. You have to have a way of let
your windows based program know what your RTL code is doing, and NIOS
II is the answer. Send me an email if you dont see what I'm saying.

Article: 129695
Subject: Re: Virtex-5 FXT coming soon?
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Mon, 3 Mar 2008 08:15:38 -0800 (PST)
Links: << >>  << T >>  << A >>
On 3 Mrz., 11:20, Antti <Antti.Luk...@googlemail.com> wrote:

> but as the V5FX has been delaying so long, I have almost lost interest
> to follow up how much longer it is delaying in reality...
>
> The Spartan-4 is much more interesting,

Well, we are desperately waiting for the V5 MGTs.
Actually we need a solution for 10gbps soon as XAUI is going to be
replaced
by SFP+ really soon. We can't place external 10G serdes on 12 ports.

Kolja Sulimma

Article: 129696
Subject: Re: Virtex-5 FXT coming soon?
From: Antti <Antti.Lukats@googlemail.com>
Date: Mon, 3 Mar 2008 08:17:39 -0800 (PST)
Links: << >>  << T >>  << A >>
On 3 Mrz., 17:15, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> On 3 Mrz., 11:20, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > but as the V5FX has been delaying so long, I have almost lost interest
> > to follow up how much longer it is delaying in reality...
>
> > The Spartan-4 is much more interesting,
>
> Well, we are desperately waiting for the V5 MGTs.
> Actually we need a solution for 10gbps soon as XAUI is going to be
> replaced
> by SFP+ really soon. We can't place external 10G serdes on 12 ports.
>
> Kolja Sulimma

well EVERY new xilinx family since V2ProX is DOWNGRADING the speed of
MGTs
V4 less than V2
V5 less than V4

so you may need wait V6 :(

Antti



Article: 129697
Subject: clock distribution accross boards
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Mon, 3 Mar 2008 08:27:15 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

maybe you folks can help me with a design decision:

I need to distribute a clock to up to ten identical boards.
The boards are all plugged into a backplane in a single row.

In addition to the backplane the boards will be connected by
a twinax flatband cable on samtec connectors. For the clock
distribution I can choose between a bus structure cable or a
series of point to point connections between neighbouring boards.

The leftmost of the identical boards shall provide a clock for all
the other boards. I am now concerned that a bus structure with
that many stubs will have problems maintaining a good signal quality.

I could instead use point to point connections with fanout clock
buffers on each board to forward the clock to the next board. As far
as the signal quality goes this will obviously work very well,
BUT the boards need a fixed phase relationship. While the absolute
phase is of no importance, the phase must not drift over time or
temperature by more than 50ps or so. Ten buffers in a row would
probably have a larger drift, wouldn't they?

Any ideas, how I can make a pure passive distribution work in a setup
like that?

Also: How can I turn on the termination on the last board dynamically?


Kolja Sulimma



Article: 129698
Subject: Re: Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
From: chakra <narashimanc@gmail.com>
Date: Mon, 3 Mar 2008 08:43:38 -0800 (PST)
Links: << >>  << T >>  << A >>
when i looked in through Chipscope the OPB_RNW signal is always high
and never goes low (which it shud when i use XIO_Out command). Thus
always getting the Bus2IP_RDCE signal to go high instead of the
Bus2IP_WRCE.

still dont know why the OPB_RNW signal is always high. if anyone got
this type of error do send me a fix if you found one.

Article: 129699
Subject: ICAP for readback on Microblaze...
From: Xesium <amirhossein.gholamipour@gmail.com>
Date: Mon, 3 Mar 2008 08:55:20 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi everybody,
I'm trying to partially reconfigure my device (XC2VP30 on ML310 board)
through ICAP. I have my ICAP attached to OPB which is attached to
Microblaze. In bitgen.ut file I have set the value of mode pins
(M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. I
also made sure that persist bit is not set. As well the base address
and high address of my HWICAP is 0x42000000 and 0x42000fff as
mentioned in the datasheet of HWICAP. My system's (processor and OPB
bus) clock frequency is 25 MHz to make sure that ICAP is OK with it.
The system contains a timer, a SysAce, a hwicap, a uartlite and an opb-
mdm (for debugging) all attached to the opb. The microblaze has some
local memory too. I'm also using EDK, ISE 8.2. That's the whole
setting about my system. Now here is the problem:

I just need to measure the delay of reconfiguration through ICAP. The
following is a very simple C code I have implemented to read a frame
and print the content on the screen. Later I want to write something
to a frame and again read it back just to make sure that in fact it
changed the reconfiguration. Firstly I initialize the ICAP module and
then invoke XHwIcap_DeviceReadFrame() and then I read the
configuration through XHwIcap_StorageBufferRead().

    XHwIcap my_icap;

    XStatus icap_stat;

    icap_stat = XHwIcap_Initialize(&my_icap,
XPAR_OPB_HWICAP_0_DEVICE_ID, XHI_READ_DEVICEID_FROM_ICAP);

    if(icap_stat != XST_SUCCESS)
        print("\n Initialization not successful!!\n");

    Xuint32 frame_content;

    icap_stat = XHwIcap_DeviceReadFrame(&my_icap, XHI_FAR_CLB_BLOCK,
32, 32);

    if(icap_stat != XST_SUCCESS)
        print("\n There is something working in reading a frame!\n");

        for(i = 0; i < my_icap.WordsPerFrame; i++)
    {
        print("word number");
        putnum(i+1);
        print(" is equal to: ");
        frame_content = XHwIcap_StorageBufferRead(&my_icap, i);
        putnum(frame_content);
        putchar('\n');
        }

The problem is when I read back the frame except for the first 7 words
everything is 0, no matter what frame it is. I have carefully studied
ICAP's driver's functions and their
implementation. I know that the driver writes the first 7 words in the
storage buffer which are basically dummy word, sync word, setting CMD
register, setting FAR register and etc. While I have not verified that
to read back these are the words that should be sent to ICAP but they
sound reasonable. The seven words that I read are as follows:

30008001
0000000d
ffffffff
ffffffff
30002001
00404000
2800619c

(I guess this should not be an issue but the first 4 words are
different than what was written in DeviceReadFrame function, I
realized that the content changes after invoking Desync command in
DeviceReadFrame function!)
So as I mentioned, my problem is I can't basically read a frame of
configuration correctly. Do you have any idea where I'm doing wrong or
what the problem is? I have been advised to use DeviceRead and
DeviceWrite instead of DeviceReadFrame and DeviceWriteFrame. Does any
one have a successful on unsuccessful experience with these functions
in the driver?

As well I have some doubts and questions. Firstly why should we first
read a frame, modify it and then write it back to the configuration?
Can't we just write something to the device? I haven't still worked
with difference-based reconfiguration and it might have something to
do with that. But if I just want to write configuration to one frame
that doesn't implement any other part of any other circuit, can't I
just write something to that frame without first reading it and
modifying it?

The second question that I have is about the storage buffer of the
HWICAP module. Firstly I thought that I have to set an opb_bram so
that HWICAP can use it. However later through studying the driver I
realized that the base address for HWICAP is the same as storage
buffer (which is the BRAM) so I concluded that when I use a HWICAP I
implicitly assign a BRAM to it. Is this so? If not please let me know.

The third question is the clock frequency that ICAP operates! I have
read somewhere that the highest is 66MHz. Is it correct or we can set
the clock higher than that?

This message became very long, but I really appreciate it if you could
kindly help me out with it. I have read many of the previous posts
about ICAP but couldn't find enough information to solve my problems.
So perhaps this post can be a complement to them.

Thanks a lot beforehand,



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