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On 3=D4=C211=C8=D5, =CF=C2=CE=E711=CA=B125=B7=D6, Jeff Cunningham <j...@sove= r.net> wrote: > wicky wrote: > > I found Chipscope is too difficult to learn for college students, it > > Yes but isn't college supposed to prepare them for the real world? In this course, we try to introduce 8086/8088 system to those who know nothing about FPGA. > > > has too much options. I want to develop a simple gui software and > > using it in a 8086/8088 FPGA embedded system. For example, students > > can understand a bus transaction with just a simple mouse click in > > this software, instead of setting so much options in the tranditional > > Chipscope software. Can anyone give me some information about this > > work? Thank you! > > Couldn't the instructor set up chipscope and then save all the options? > Then the student would just have to reload the saved project file, and > the bus transaction would be there all optimally displayed for > understanding. > In fact, I want to integrated the software debugging environment, so... > -Jeff Thanks for your kindly reply WickyArticle: 129951
On Mar 11, 7:19=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > Hi Paul, > Yeah, if you look at your code, you're trying to do an asynchronous read. = I > suggest you try simulating your design and also a design where you > instantiate a block ram. You'll be able to compare and see clearly what th= e > block ram does. > HTH., Syms. This is not the first time that someone has tried to read the BRAM asynchronously. I have posted many times, and also inserted a sentence into our documentation that "nothing happens without a clock". Any ideas how we can spread this important (and non-obvious) information even better and wider??? Peter Alfke, Xilinx ApplicationsArticle: 129952
On Mar 11, 4:48 pm, Peter Alfke <pe...@xilinx.com> wrote: > On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > Hi Paul, > > Yeah, if you look at your code, you're trying to do an asynchronous read. I > > suggest you try simulating your design and also a design where you > > instantiate a block ram. You'll be able to compare and see clearly what the > > block ram does. > > HTH., Syms. > > This is not the first time that someone has tried to read the BRAM > asynchronously. I have posted many times, and also inserted a sentence > into our documentation that "nothing happens without a clock". > Any ideas how we can spread this important (and non-obvious) > information even better and wider??? > Peter Alfke, Xilinx Applications Hi Peter, Just rename your component from BRAM to BSRAM ! Synchronous RAM ! As a ROM based on BRAM should be renamed by BSROM. (It is not regular to have synchronous ROM, but yes it is synchronous ( need CLK clock ) too when based on Xilinx BRAM ) Regards, Laurent http://www.amontec.comArticle: 129953
On 7 Mrz., 22:57, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > austin wrote: > > Jim, > > > It is an anti-fuse array technology. > > Thanks. Any comments on programming Speed, and Yields ? :) > I wouldn't worry about yield, as Siliconblue/Kilopass should have built in bit error correction when reading / programming the antifuse- NVM. I would worry more about programming Speed for the NVM, remembering Quicklogic Parts long ago needing 20minutes to program. But again this could be much better because the NVM is seperate and localized - not spread over the chip - so it may also be optimized for speed / parallel Programming. I hope they have a useable development software environment. Their opportunity is making it easy for engineers to replace other FPGAs with theirs / adapt their FPGA's quickly and being able to deliver stable working parts. They seem a worthy competitor for the mass-FPGA maket. But also the path they have chosen seems easy to pick-up for the big players (on success), leaving a rather small time-to-market advantage for them, compared to the massive market/financial power of the old players. Raymund HofmannArticle: 129954
Peter Alfke wrote:
> This is not the first time that someone has tried to read the BRAM
> asynchronously. I have posted many times, and also inserted a sentence
> into our documentation that "nothing happens without a clock".
> Any ideas how we can spread this important (and non-obvious)
> information even better and wider???
The problems I see in this newsgroup are a result of
hdl designers continuously reinventing templates
to infer a block ram by trial and error.
If I worked for Xilinx I would write an
ap note in vhdl and verilog for a useful
application example that infers block ram from code,
and then reference that example in all related documents.
Feel free to use my public template if you like:
http://home.comcast.net/~mike_treseler/block_ram.vhd
-- Mike Treseler
Article: 129955On Mar 11, 6:10 pm, donald <Don...@dontdoithere.com> wrote: > j...@amontec.com wrote: > > On Mar 11, 4:48 pm, Peter Alfke <pe...@xilinx.com> wrote: > >> On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote: > > >>> Hi Paul, > >>> Yeah, if you look at your code, you're trying to do an asynchronous read. I > >>> suggest you try simulating your design and also a design where you > >>> instantiate a block ram. You'll be able to compare and see clearly what the > >>> block ram does. > >>> HTH., Syms. > >> This is not the first time that someone has tried to read the BRAM > >> asynchronously. I have posted many times, and also inserted a sentence > >> into our documentation that "nothing happens without a clock". > >> Any ideas how we can spread this important (and non-obvious) > >> information even better and wider??? > >> Peter Alfke, Xilinx Applications > > > Hi Peter, > > > Just rename your component from BRAM to BSRAM ! Synchronous RAM ! > > > As a ROM based on BRAM should be renamed by BSROM. (It is not regular > > to have synchronous ROM, but yes it is synchronous ( need CLK clock ) > > too when based on Xilinx BRAM ) > > > Regards, > > Laurent > >http://www.amontec.com > > This is an FPGA is it not. > > Nothing in an FPGA happens without a clock. > > Why would anyone think that BRAM would operate differently ?? > > My .02 > > donald sorry but you may describe LUT as asynchronous ROM ? -> No Clock ! My 0.02 Laurent http://www.amontec.comArticle: 129956
job@amontec.com wrote: > On Mar 11, 4:48 pm, Peter Alfke <pe...@xilinx.com> wrote: >> On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote: >> >>> Hi Paul, >>> Yeah, if you look at your code, you're trying to do an asynchronous read. I >>> suggest you try simulating your design and also a design where you >>> instantiate a block ram. You'll be able to compare and see clearly what the >>> block ram does. >>> HTH., Syms. >> This is not the first time that someone has tried to read the BRAM >> asynchronously. I have posted many times, and also inserted a sentence >> into our documentation that "nothing happens without a clock". >> Any ideas how we can spread this important (and non-obvious) >> information even better and wider??? >> Peter Alfke, Xilinx Applications > > Hi Peter, > > Just rename your component from BRAM to BSRAM ! Synchronous RAM ! > > As a ROM based on BRAM should be renamed by BSROM. (It is not regular > to have synchronous ROM, but yes it is synchronous ( need CLK clock ) > too when based on Xilinx BRAM ) > > Regards, > Laurent > http://www.amontec.com This is an FPGA is it not. Nothing in an FPGA happens without a clock. Why would anyone think that BRAM would operate differently ?? My .02 donaldArticle: 129957
Peter Alfke <peter@xilinx.com> wrote: >On Mar 11, 7:19=A0am, "Symon" <symon_bre...@hotmail.com> wrote: >> Hi Paul, >> Yeah, if you look at your code, you're trying to do an asynchronous read. = >I >> suggest you try simulating your design and also a design where you >> instantiate a block ram. You'll be able to compare and see clearly what th= >e >> block ram does. >> HTH., Syms. > >This is not the first time that someone has tried to read the BRAM >asynchronously. I have posted many times, and also inserted a sentence >into our documentation that "nothing happens without a clock". >Any ideas how we can spread this important (and non-obvious) >information even better and wider??? >Peter Alfke, Xilinx Applications A world wide advertising campagne include TV commercials? "And now a serious message from our Xilinx Jedi masters: use the clock!" -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 129958
Uhm....Do you really need chipscope for this? Is the purpose to introduce the students to FPGAs or to introduce them to the 8086/8088 processor and their bus transactions? Granted it has been a bit more than 10 years since I was in college. But I had multiple courses dealing with the 8086/8088 as well as courses with the 6800 Motorola processor. I even had a DSP course with a TI processor. Seeing the BUS transaction during those classes was a simple lab introducing us to a digital logic analyzer. Seems to me throwing the FPGA and Chipscope in when it may not need to be there is overly complex. If the purpose is to introduce them to FPGAs, then I think it is better to keep the students using the standard tools they can download from xilinx. Just have a good lab write up and there shouldn't be a problem. I remember many a lab where the tool used was complex, but the Lab kept us to a small subset of the functionality as an introduction to the tool. Adding a new yet simpler GUI, will only hinder the students wehn they start going to job interviews and say they know how to use chipscope version "easy_mode". "wicky" <wicky.zhang@gmail.com> wrote in message news:c388a3b0-f07f-4572-8c61-a49743aaa57c@s13g2000prd.googlegroups.com... >I found Chipscope is too difficult to learn for college students, it > has too much options. I want to develop a simple gui software and > using it in a 8086/8088 FPGA embedded system. For example, students > can understand a bus transaction with just a simple mouse click in > this software, instead of setting so much options in the tranditional > Chipscope software. Can anyone give me some information about this > work? Thank you! > > Best Regards, > > WickyArticle: 129959
Hi Peter, Symon, everyone, Peter Alfke wrote: > On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote: >> Hi Paul, >> Yeah, if you look at your code, you're trying to do an asynchronous read. I >> suggest you try simulating your design and also a design where you >> instantiate a block ram. You'll be able to compare and see clearly what the >> block ram does. > > This is not the first time that someone has tried to read the BRAM > asynchronously. I have posted many times, and also inserted a sentence > into our documentation that "nothing happens without a clock". > Any ideas how we can spread this important (and non-obvious) > information even better and wider??? > Peter Alfke, Xilinx Applications My mistake was not realizing that - of course - the data on the BRAM are not available instantaneously, but will be available at the next clock cycle, hence the need to register them. I mistakenly thought 'hey, this process block has a clock in its sensitivity list, so why is XST still claiming I'm using it asynchronously?' So I was not "tryin to read the BRAM asynchronously" as Peter wonders, just not having any idea what I was doing ;-) Thanks for the many helpful replies. Regards. Paul Boven.Article: 129960
Some initial feedback "Video #2" has the title " FPGAs for Beginners - The Top 6 Questions" followed by 6 questions. All the questions are covered in the video but the slides only state that there were 5 questions. "Tony Burch" <tony@burched.com.au> wrote in message news:47d69334$0$10472$afc38c87@news.optusnet.com.au... > Hi all, > > > > I have just released a new online Video guide called "The BurchED Getting > Started with Xilinx FPGAs Video Guide" http://www.BurchED.com > > > > It is an easy step-by-step guide for FPGA beginners. I go all the way > through from "What is an FPGA?" right up to compiling designs and > downloading to your FPGA board. > > > > You can log in to the site whenever you want and watch the videos, > including any additional ones that I will put up over time. > > > > There's a Free Membership area where you can watch some videos for free. > > > > * FPGAs for Beginners - the Top 6 Questions answered > > * How to choose an FPGA board > > * An independent review of available FPGA boards > > * What to do when you first get your FPGA board > > * How to download and install the free Xilinx design software > > > > There's also an introductory offer on the full video guide, which includes > 18 videos on getting started with Xilinx FPGAs. Some of the benefits are: > > > > * Save time and effort when getting started with FPGAs > > * Avoid the big mistakes that often derail first time FPGA users > > * Save money - advice to lower your cost when getting an FPGA board > > * Expand your design options by putting FPGAs in your toolbox > > * Achieve the satisfaction and fun of designing your own FPGA circuits > > * Amaze your colleagues with your new FPGA skills > > * Gain the skills and confidence needed to go on and make more complex > designs > > > > I look forward to seeing you over there. Grab the Free membership & have a > look at the introductory offer on the full video guide > http://www.BurchED.com > > > > Kind regards, > > > > Anthony Burch > > BurchED - Making it easy to get started with FPGAs > > > > PS. A note for University Lecturers: > > University & company site licenses are available. Minimise the amount of > lecture time that you spend teaching FPGA basics. Let your students do > this video course at home. Please email me for details about great value > site licenses. > > > >Article: 129961
Video 3b - At the end you recomend that your viewers purchase a Digilent board. You should add the reason for this recomendation. That reason being that future videos will be easier to follow if they purchase the digilent board. Althouhg the videos can be used with a non- digilent board. "Dwayne Dilbeck" <ddilbeck@yahoo.com> wrote in message news:13tdicepdj4vc79@corp.supernews.com... > Some initial feedback "Video #2" has the title > " FPGAs for Beginners - The Top 6 Questions" > followed by 6 questions. All the questions are covered in the video but > the slides only state that there were 5 questions. > > > "Tony Burch" <tony@burched.com.au> wrote in message > news:47d69334$0$10472$afc38c87@news.optusnet.com.au... >> Hi all, >> >> >> >> I have just released a new online Video guide called "The BurchED Getting >> Started with Xilinx FPGAs Video Guide" http://www.BurchED.com >> >> >> >> It is an easy step-by-step guide for FPGA beginners. I go all the way >> through from "What is an FPGA?" right up to compiling designs and >> downloading to your FPGA board. >> >> >> >> You can log in to the site whenever you want and watch the videos, >> including any additional ones that I will put up over time. >> >> >> >> There's a Free Membership area where you can watch some videos for free. >> >> >> >> * FPGAs for Beginners - the Top 6 Questions answered >> >> * How to choose an FPGA board >> >> * An independent review of available FPGA boards >> >> * What to do when you first get your FPGA board >> >> * How to download and install the free Xilinx design software >> >> >> >> There's also an introductory offer on the full video guide, which >> includes 18 videos on getting started with Xilinx FPGAs. Some of the >> benefits are: >> >> >> >> * Save time and effort when getting started with FPGAs >> >> * Avoid the big mistakes that often derail first time FPGA users >> >> * Save money - advice to lower your cost when getting an FPGA board >> >> * Expand your design options by putting FPGAs in your toolbox >> >> * Achieve the satisfaction and fun of designing your own FPGA circuits >> >> * Amaze your colleagues with your new FPGA skills >> >> * Gain the skills and confidence needed to go on and make more complex >> designs >> >> >> >> I look forward to seeing you over there. Grab the Free membership & have >> a look at the introductory offer on the full video guide >> http://www.BurchED.com >> >> >> >> Kind regards, >> >> >> >> Anthony Burch >> >> BurchED - Making it easy to get started with FPGAs >> >> >> >> PS. A note for University Lecturers: >> >> University & company site licenses are available. Minimise the amount of >> lecture time that you spend teaching FPGA basics. Let your students do >> this video course at home. Please email me for details about great value >> site licenses. >> >> >> >> > >Article: 129962
donald wrote: (snip) > This is an FPGA is it not. > Nothing in an FPGA happens without a clock. Where does this come from? There is no reason one can't do designs that don't use any FF's in an FPGA, though there is a strong incentive to use them. > Why would anyone think that BRAM would operate differently ?? Because that is the way traditional SRAMs work and people get used to using them that way. Also, most ROMs. -- glenArticle: 129963
job@amontec.com wrote: > On Mar 11, 4:48 pm, Peter Alfke <pe...@xilinx.com> wrote: (snip) >>Any ideas how we can spread this important (and non-obvious) >>information even better and wider??? > Just rename your component from BRAM to BSRAM ! Synchronous RAM ! Except that SRAM traditionally means Static RAM, so one might still not notice. How about BSyRAM? -- glenArticle: 129964
Fei Liu wrote: (snip) > I will look into these options. I am more interested in some hands on > experience at the moment. FPGA just feels too much programming. I have > done enough software programing. I will have a bit more hands on > experience/fun with electronics before going back to programming > again, albeit programming the FPGA hardware. That sounds good. More common is people used to programming and not logic design thinking of it in programming (serial) terms. If you think of it as a way to write down logic structure, you will do much better. -- glenArticle: 129965
Marc Reinig wrote: > I need some references of where systolic arrays have > actually been used in equipment or instruments. I previously gave the best references I could find to the Paracel machines. The FDF (Fast Data Finder) originated with TRW for text searching and development was continued by Paracel. A patent search for FDF should find that. The FDF2 used an 8 processor element/chip ASIC. GeneMatcher is/was a Paracel product for DNA and protein sequence comparison, also an ASIC based systolic array. The processor unit is much more complicated than the FDF, especially with the included result processors. Within the array between every eight data processors is logic for collecting results and saving them for later analysis. For FPGA based systolic arrays, there is Time Logic. http://www.timelogic.com/technology.html -- glenArticle: 129966
satyam <satyam.dwivedi@gmail.com> wrote: >I want to interface matlab with the Xilinx Virtex-II pro board. Intent >is to give input from matlab to the FPGA and to read the ouput of FPGA >in matlab. >Problem is in interfacing speed. I need high speed interface, of the >order of 2 mega bits per second (Mbps). Seems RS-232 will be >inadequate for my purpose. From Documents interface through ethernet >seems to be a viable option but I am not sure. To summarize I want >answers and suggestions on following: >1). FPGA to PC communication by ethernet ? Yes works. >2). What can be the maximum speed ? 1000Mbps depending on your ethernet chip(s). >3). How to transfer data on ethernet by matlab ? C socket programming >4). Is it possible to write inputs (60 Mega bits) to some memory on >FPGA board and then read it from there to do the computation ? If your ethernet PHY manages 100 Mbps in full duplex, then yes. >Please let me know if you have any suggestion for me. Do you need realtime or synchronous operation? Btw, there's lots of good stuff to be found via the google force luke ;)Article: 129967
We have two of these boards (with the LX50 ES), and both failed the DDR memory test with a build from the Base System Builder. We downloaded the test designs from the Avnet Design Resource Center, and these would sporadically fail. We looked at the datasheet for the MT47H16M16BG DDR2, and noticed that the acceptable frequency range for the DDR is between 125MHz and 200MHz. The BSB design uses 125MHz, and according to our FAE, the test design uses 200MHz. Apparently our boards are marginal at both these extremes. We modified the clock generator in the BSB design to set the clock to 133MHz and 150MHz, both of these designs passed the memory test. As an aside, when I recompiled my EDK libraries for 9.2, I told it not to recompile any deprecated cores. Now it looks like there are only PLB cores availible, is Xilinx phasing out support for OPB? We are using EDK/ISE 9.2 with the latest web updates.Article: 129968
sdf wrote: > Let's say, I have big table which is usually suitable to fit it in > some ROM. > But it's possible to construct some circuit containing only primitive > gates that acts just as that ROM. For modern systems, especially FPGAs, it might be better to consider multiple smaller tables. I have a data book from years ago with a sine lookup table ROM in it. They start with one ROM with limited resolution. Next they do linear interpolation on the first ROM with the help of one, two, or three more ROMs. Also, in the past nanoprogramming has been used to avoid the problems of large microprogram ROMs. That is, a two level lookup table in place of one large one, as a more efficient storage system for microprogram ROMs. In most cases it might be easier to do by hand, using knowledge about the table data. There are still some possibilities for automation, though. -- glenArticle: 129969
There was also Princeton's PNAC by Lopresti in this area. And all the work by Kung in the 1980s (iWARP). Also see the Application Specific Array Processors (ASAP) conference for ongoing work ( http://asap-conference.org/ ). -- Steve -- 3/11/08 "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:XImdnSW1pdyJdEvanZ2dnUVZ_r6rnZ2d@comcast.com... > Marc Reinig wrote: >> I need some references of where systolic arrays have >> actually been used in equipment or instruments. > > I previously gave the best references I could find to > the Paracel machines. > > The FDF (Fast Data Finder) originated with TRW for text > searching and development was continued by Paracel. > A patent search for FDF should find that. The FDF2 used > an 8 processor element/chip ASIC. > > GeneMatcher is/was a Paracel product for DNA and protein > sequence comparison, also an ASIC based systolic array. > The processor unit is much more complicated than the FDF, > especially with the included result processors. Within > the array between every eight data processors is logic for > collecting results and saving them for later analysis. > > For FPGA based systolic arrays, there is Time Logic. > > http://www.timelogic.com/technology.html > > -- glen >Article: 129970
On Mar 6, 10:17=A0pm, Skogul <etork...@gmail.com> wrote: > I set OPTION CORE_STATE =3D > DEVELOPMENT in the mpd and when I rerun "Generate Netlist" I get the > output "make: Nothing to be done for `netlist'." platgen is not being > run. Is there a way to get it working from within EDK? Try using Project> Rescan user repositories.Article: 129971
In the course about 8086/8088 processor, I just plan to introduce this CPU and its bus transactions. if those younker are interested in more about FPGA, i think "no problem", :-) The reason why I choose FPGA for the course lab is: 1) Soft core 8086/8088 is more flexible, we could monitor the bus transactions and even the cpu internal signal. Furthermore, we could introduce other processor system based on the same hardware platform. 2) We are a member of Xilinx XUP, we have several V2PRO and Spartan3E boards. 3) We have no budget to prepare logic analyzer for every student Btw: There is a opensource 8086/8088 for FPGA in this web: http://www.ht-lab.com/freecores/cpu8086/cpu86.html Many thanks! Wicky On Mar 12, 1:42=A0am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > Uhm....Do you really need chipscope for this? =A0Is the purpose to introdu= ce > the students to FPGAs or to introduce them to the 8086/8088 processor and > their bus transactions? > > Granted it has been a bit more than 10 years since I was in college. But I= > had multiple courses dealing with the 8086/8088 as well as courses with th= e > 6800 Motorola processor. I even had a DSP course with a TI processor. > Seeing the BUS transaction during those classes was a simple lab introduci= ng > us to a digital logic analyzer. > > Seems to me throwing the FPGA and Chipscope in when it may not need to be > there is overly complex. > > If the purpose is to introduce them to FPGAs, then I think it is better to= > keep the students using the standard tools they can download from xilinx. > Just have a good lab write up and there shouldn't be a problem. =A0 I reme= mber > many a lab where the tool used was complex, but the Lab kept us to a small= > subset of the functionality as an introduction to the tool. =A0 Adding a n= ew > yet simpler GUI, will only hinder the students wehn they start going to jo= b > interviews and say they know how to use chipscope version "easy_mode". > > "wicky" <wicky.zh...@gmail.com> wrote in message > > news:c388a3b0-f07f-4572-8c61-a49743aaa57c@s13g2000prd.googlegroups.com... > > > > >I found Chipscope is too difficult to learn for college students, it > > has too much options. I want to develop a simple gui software and > > using it in a 8086/8088 FPGA embedded system. For example, students > > can understand a bus transaction with just a simple mouse click in > > this software, instead of setting so much options in the tranditional > > Chipscope software. Can anyone give me some information about this > > work? Thank you! > > > Best Regards, > > > Wicky- Hide quoted text - > > - Show quoted text -Article: 129972
"Dwayne Dilbeck" <ddilbeck@yahoo.com> wrote in message news:13tdicepdj4vc79@corp.supernews.com... > Some initial feedback "Video #2" has the title > " FPGAs for Beginners - The Top 6 Questions" > followed by 6 questions. All the questions are covered in the video but > the slides only state that there were 5 questions. > Hi Dwayne, thanks for checking out the videos and for your feedback. You are right. I have changed it on the site. Video #2 (in the free membership area) is now... FPGAs for Beginners - The Top 5 Questions What is an FPGA? And how is that different to a microcontroller? Who makes FPGAs? What can I use FPGAs for? Why would I want to use FPGAs? How can I learn FPGA design?... The microcontroller topic is a kind of sub-question that I put in there. Kind regards, Anthony The BurchED Getting Started With Xilinx FPGAs Video Guide http://www.BurchED.comArticle: 129973
and while we are on this subject, why doesn't edk create a real makefile with all the necessary dependencies. then, when you change anything, all the necessary files would be rebuilt. this would also get rid of the cache, because automatically, only dependent files would be rebuilt. it seems like xilinx got 90% of the way there with make and then fumbled the last 10%. software people build gargantuan projects entirely with make. why can't edk? alan nishiokaArticle: 129974
Are the dev tools (lke the shade simulator) available for x86 win/lin platform??
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