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Jacob W Janovetz wrote: > Hello, > > I've "built" a multiplier (10-bit by 8-bit) component > from COREgen (for Solaris -- Linux would be preferred, by the way). > I get the component output as mult10x8.xnf. > > Now, I try to instantiate that in VHDL under Leonardo. > I get the following error from 'ngdbuild': > > WARNING:basnb:79 - Pin mismatch between block "themult", TYPE="mult10x8", and > file "<MY_DIRECTORY>/mult10x8.ngo" at pin > "prod(0)". Please make sure that all pins on the instantiated component > match pins in the lower-level design block. (Pin-name matching is > case-insensitive.) > > prod(0) is the LSB of the product pin. Now, I've read a few > things about this error (namely solution 2234) in the help. It > says to change the bus config under logiblox.ini. However, I look > at the coregen.ini file under $COREGEN/wkg and there is nothing to > address this. In addition, there are no setup menus in COREgen to > help me out. > > What needs to be done here? If someone knows what's going on, > I can send my VHDL, XNF, EDIF files or what not to show how I'm > doing things. Thanks for any assistance. > > Cheers, > Jake > > -- > janovetz@uiuc.edu | Once you have flown, you will walk the earth with > University of Illinois | your eyes turned skyward, for there you have been, > | there you long to return. -- da Vinci > PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html Hello. I use Coregen and Galileo (now same vendor as Leonardo bur less powerfull). I use the file.vhx whith Galileo, file.vhd for functionnal simulation and the file.xnf with M1.4. Galileo sees only an empty entity (without architecture) and the M1.4 links the components. No problems. Anyway, do you have problem with bus only or with all signals? May be the way for writing bus is different between coregen and leonardo (see option). Do you use <> or () or thomesing else for bus? (data<0>, data(0), ...). Good luck. Michel.Article: 13101
Jacob W Janovetz wrote: > I've "built" a multiplier (10-bit by 8-bit) component > from COREgen (for Solaris -- Linux would be preferred, by the way). > I get the component output as mult10x8.xnf. > > Now, I try to instantiate that in VHDL under Leonardo. > I get the following error from 'ngdbuild': > > WARNING:basnb:79 - Pin mismatch between block "themult", TYPE="mult10x8", and > file "<MY_DIRECTORY>/mult10x8.ngo" at pin > "prod(0)". Please make sure that all pins on the instantiated component > match pins in the lower-level design block. (Pin-name matching is > case-insensitive.) I believe the problem here is due to a mismatch between the CoreGen netlist (XNF) and the output of your synthesis tool. Although you think your pin names are the same, one tool writes the pins as a bus and the other as individual ports. There are a number of ways to approach this, but I expect your synthesis tool has an option to write the netlist with ports expanded rather than as busses. However then you need to watch out for the way that the tool expands busses. For example one tool may be writing busa(0) and the other busa<0> or busa_0. A solution that I have used with Exemplar Leonardo is to load the appropriate library, read in the CoreGen XNF file and write it out again as a VHDL netlist. The VHDL can then be read in when you analyze the rest of the VHDL for your project. Make sure you set a don't touch on the CoreGen block so that it is not optimized with the rest of the design. Finally the design that is written out as everything you need and you don't rely on the Xilinx merger to get the port mapping right. This may sound like a pain, but you usually only need to do the XNF to VHDL netlist conversion once for each CoreGen model. I am interested to here if anyone has a better solution. MarkArticle: 13102
Hi Shail, Technically speaking, there is no advantage of Big-Endianness over Little-Endianness. Intel processors are predominantly Little-Endian, while Motorola processors are Big-Endian. Choosing one over the other depends primarily on the overall system. If you are designing a subsystem which will be connected to an Intel platform, it makes sense to choose Little-Endianness. It is important to note that although many bridges (e.g., PCI-to-local bus) have on the fly byte-swapping, this only maintains address invariance. If a program running on one 32-bit platform tries to access 32-bit data produced by another program running on another 32-bit platform with different endianness, you still have to perform explicit conversion. Address invariance means that, when accessing an aggregate data structure (e.g., record), the relative address of the fields are maintained. If latency isn't a problem, it doesn't matter which ever Endianness you choose. To reply to your second point, not all RISC processors are Big-Endian. The i960 family of processors are Little-Endian although some of them have the capability of Endian conversion. Dr Yves Tchapda Design Engineer Power X EnglandArticle: 13103
You are thinking of a phase adder in a technique called DDS or Direct Digital Synthesis. Simon ============================= Le mer Michel <michel.lemer@ago.fr> wrote: >ovilup wrote: > >> Hello ! >> >> I am working on an I2C controller. Now, I am designing the >> internal clock generator. I have an 1.5 MHz internal clock, >> from which I have to generate the 100 KHz, 90 KHz, 44 KHz >> 1.5 KHz SCL clocks. >> >> Any examples of such an clock generator would be appreciated ! >> >> Thank you in advance. >> OL > >Hello > >I do not know exactly what it is but I heard about the direct numeric >synthesis. It is use in the signal generators to privide a wave of a >specific frequency. > >Bye. >Michel. > Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htmArticle: 13104
--------------2E0E5DD694A1EA8757417BEC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You don't mention whether you need all these clock rates at same time, or one at a time. Also what is the acceptable % error on those clock rates? 100 Khz is 1.5 Mhz divided by 15, you can get 88.23 Khz dividing by 17, 44.11 Khz by dividing by 34. 1.5 Khz by dividing by 1000. If you only need one clock at a time, use a programmable counter where a bit-vector selects what counter preload value to use. For getting 50% duty cycle from odd divisor, check out my article in the August 15, 1997 issue of EDN magazine, page 73. Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address> Le mer Michel <michel.lemer@ago.fr> wrote: > >ovilup wrote: > > > >> Hello ! > >> > >> I am working on an I2C controller. Now, I am designing the > >> internal clock generator. I have an 1.5 MHz internal clock, > >> from which I have to generate the 100 KHz, 90 KHz, 44 KHz > >> 1.5 KHz SCL clocks. > >> > >> Any examples of such an clock generator would be appreciated ! > >> > >> Thank you in advance. > >> OL > --------------2E0E5DD694A1EA8757417BEC Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> You don't mention whether you need all these clock rates at same time, or one at a time. Also what is the acceptable % error on those clock rates? 100 Khz is 1.5 Mhz divided by 15, you can get 88.23 Khz dividing by 17, 44.11 Khz by dividing by 34. 1.5 Khz by dividing by 1000. If you only need one clock at a time, use a programmable counter where a bit-vector selects what counter preload value to use. For getting 50% duty cycle from odd divisor, check out my article in the August 15, 1997 issue of EDN magazine, page 73. <P>Brian C. Boorman <BR>Harris RF Communications <BR>Rochester, NY 14610 <BR>XYZ.bboorman@harris.com <BR><Remove the XYZ. for valid address> <P>Le mer Michel <michel.lemer@ago.fr> wrote: <BLOCKQUOTE TYPE=CITE>>ovilup wrote: <BR>> <BR>>> Hello ! <BR>>> <BR>>> I am working on an I2C controller. Now, I am designing the <BR>>> internal clock generator. I have an 1.5 MHz internal clock, <BR>>> from which I have to generate the 100 KHz, 90 KHz, 44 KHz <BR>>> 1.5 KHz SCL clocks. <BR>>> <BR>>> Any examples of such an clock generator would be appreciated ! <BR>>> <BR>>> Thank you in advance. <BR>>> OL <BR><A HREF="http://www.tefbbs.com/spacetime/index.htm"></A> </BLOCKQUOTE> </HTML> --------------2E0E5DD694A1EA8757417BEC--Article: 13105
Leonardo has a property called EDIF_WRITE_ARRAYS, which can be set to TRUE or FALSE. You can also specify how Leonardo writes out bus identifiers (i.e. <> () []). Xilinx tools do accept EDIF netlists. Try looking at this method as a solution to your problem. Mark Snook wrote: > I believe the problem here is due to a mismatch between the CoreGen > netlist (XNF) and the output of your synthesis tool. Although you think > your pin names are the same, one tool writes the pins as a bus and the > other as individual ports. There are a number of ways to approach this, > but I expect your synthesis tool has an option to write the netlist with > ports expanded rather than as busses. However then you need to watch out > for the way that the tool expands busses. For example one tool may be > writing busa(0) and the other busa<0> or busa_0. > > > Mark -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 13106
On 14 Nov 1998 04:04:50 GMT, janovetz@ews.uiuc.edu (Jacob W Janovetz) wrote: >Hello, > > I've "built" a multiplier (10-bit by 8-bit) component >from COREgen (for Solaris -- Linux would be preferred, by the way). >I get the component output as mult10x8.xnf. > > Now, I try to instantiate that in VHDL under Leonardo. >I get the following error from 'ngdbuild': > >WARNING:basnb:79 - Pin mismatch between block "themult", TYPE="mult10x8", and > file "<MY_DIRECTORY>/mult10x8.ngo" at pin > "prod(0)". Please make sure that all pins on the instantiated component > match pins in the lower-level design block. (Pin-name matching is > case-insensitive.) > I think your problem here is to do with the differing bus naming conventions used by Xilinx tools and Exemplar. I have not tried using CoreGen macros with Leonardo, but I have used LogiBlox cells and experienced similar problems. In LogiBlox, first you have to select 'Mentor' from the vendor type. This ensures that the right sort of bus numbering brackets are used (eg. <> or [] or () ). CoreGen has only one output bus option which seems to be set correctly for Exemplar with <> brackets. Second, you must use the Exemplar '-nobus' switch during synthesis. This expands all busses into bunches of 'single wires' in the netlist, and is the format in which Xilinx tools work. If you don't do this, the netlist will have traditional busses, and the CoreGen generated block will not; thus causing the mismatch. I guess the latter requirement is the cause of your problems. Hope that helps. Graeme Durant HELION Technology Limited - Programmable Logic Consultants The Granary, Home End, Fulbourn, Cambridge CB1 5BS. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ mailto:gd@heliontech.com http://www.heliontech.com ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 13107
Mark,
Over the weekend, I was able to get the tools to cooperate. I
just wrote a script to revise the .xnf files from COREgen into the
right format. And I can still do all this without using a GUI.
Why? BECAUSE I'M NOT USING WINDOWS!!!!! Yyeeeee Haaa!
(Sorry, I love UNIX...)
Cheers,
Jake
Mark Snook <mark.snook@arm.com> writes:
>Jacob W Janovetz wrote:
>> I've "built" a multiplier (10-bit by 8-bit) component
>> from COREgen (for Solaris -- Linux would be preferred, by the way).
>> I get the component output as mult10x8.xnf.
>>
>> Now, I try to instantiate that in VHDL under Leonardo.
>> I get the following error from 'ngdbuild':
>>
>> WARNING:basnb:79 - Pin mismatch between block "themult", TYPE="mult10x8", and
>> file "<MY_DIRECTORY>/mult10x8.ngo" at pin
>> "prod(0)". Please make sure that all pins on the instantiated component
>> match pins in the lower-level design block. (Pin-name matching is
>> case-insensitive.)
>I believe the problem here is due to a mismatch between the CoreGen
>netlist (XNF) and the output of your synthesis tool. Although you think
>your pin names are the same, one tool writes the pins as a bus and the
>other as individual ports. There are a number of ways to approach this,
>but I expect your synthesis tool has an option to write the netlist with
>ports expanded rather than as busses. However then you need to watch out
>for the way that the tool expands busses. For example one tool may be
>writing busa(0) and the other busa<0> or busa_0.
>A solution that I have used with Exemplar Leonardo is to load the
>appropriate library, read in the CoreGen XNF file and write it out again
>as a VHDL netlist. The VHDL can then be read in when you analyze the
>rest of the VHDL for your project. Make sure you set a don't touch on
>the CoreGen block so that it is not optimized with the rest of the
>design. Finally the design that is written out as everything you need
>and you don't rely on the Xilinx merger to get the port mapping right.
>This may sound like a pain, but you usually only need to do the XNF to
>VHDL netlist conversion once for each CoreGen model.
>I am interested to here if anyone has a better solution.
>Mark
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 13108> A few of points: > > 1. One of the improvements to Par/v1.5 is that ram blocks are recognised > as such, and are supposedly placed in a sensible manner. This should > remove the need for RLOC'ing. This is right. We have installed Service Pack and we haven't met any such problems now. > 2. It sounds like Xilinx have suggested the -ir map option to get round > some mapping bug's in version 1.5. However, if the -ir option is used > relative placement information is lost, so RLOC'ing wouldn't get you > anywhere. I suggest getting the M1.5 service pack anyway. So, if I don't meed those errors, then I don't need to use RLOC'ing, do I? > 3. If the clb's with rams are intended to also have flip-flops, it might > be worth while checking in EPIC that they are both going in the same > clb. The FF's in CLB's are not used in RAM implementations, as far as I have understood Xilinx Data Book 1998. In EPIC Editor, when I have looked inside CLB's, it seems that edge-triggering has been implemented either in F-G Generators or somewhere on chip. > 4. Contrary to popular belief, structured hierarchical relative > placement is possible with VHDL too. In fact it's easier and quicker. Frankly speaking, I am not interested in VHDL-Verilog difference. The problem is, if my big amount of RAM can be a drawback for routing (we have core, which consists of a logic of 600-650 CLB's and internal RAM's of 1000-1200 CLB's; so the amount of RAM is ca. %55 of core but not any device resources). Now my question is, is such an amount of RAM is really a drawback for placement&routing? One engineer from Canada told me that such a big amount of internal RAM is beyond the limits of Xilinx internal resource capabilities, since it needs astronomical resources. But we have never met some information on RAM concept for Xilinx technology. If you know any good information occasionally, that we seem to have missed it, would you please inform me? The 1000-1200 CLB's is not a single block RAM but is made up of several 32x8, 128x1, 128x3, 128x7 and 128x8 dual-port RAM's and 64x8 synchronous single-port RAM's. It was not necessary to implement internal RAM's in this way. One of the internal RAM structure had to be implemented as 128x40 storage structure but we thought it would be a good way to partition it by instantiating 5 times 128x8 dual-port RAM modules. It is not so easy to redesign RAM organization. If possible, I want to have your experiences about RAM organizations and those effects on placement&routing. Since a placement&routing efforts take at least 3-4 days on Ultra-10/300 MHz/128 Mb, your experiences will be invaluable. Would you please share your RAM organization concepts and their influences on placement&routing? What we have learned are: Design Manager is smart enough to place internal RAM's according to minimal routing requirements. We have observed that 128x1 dual-port RAM structures have been placed as much "square-based" as possible (we have seen it at EPIC Editor). We have mapped our chip (600-650 CLB's for logic, 1000-1200 CLB's for internal RAM's) into several devices and here are the results (it took several weeks to get these results): Device Speed Packet Total CLB's Mapped Amount Unrouted Grade of device CLB's connections ======================================================================== XC4062XL -3 HQ304 2304 (48x48) 2570 %111 2-2000 XC4085XLA -09 HQ304 3136 (56x56) 2580 %85 2-1000 XC40110XV -09 BG352 4096 (64x64) 2580 %63 2 XC40150XV -09 BG352 5184 (72x72) 2580 %50 2 XC40200XV -09 BG432 7056 (84x84) 2590 %37 2 XC40250XV -09 BG432 8464 (92x92) 2600 %30 2 Some people also recommended to use Floorplanner. How can we place 128x1? Is the tool smart enough to "recognize" our placement? Does it really improve the performance significantly? We must expert to use Floorplaner, I think, and even for such a complicated chip. UtkuArticle: 13109
Steven K. Knapp wrote: > > You can find some tutorial information via The Programmable Logic Jump > Station at http://www.optimagic.com/tutorial.html. this link doesn't work utku > > Also, you may want to check out The Programmable Logic Bookstore at > http://www.optimagic.com/books.html#VHDL. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>... > >Dear all, > > > >I am looking for a good documentation on programming FPGA's and > >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn > >more about FPGA's and ASIC's. > > > >Thank you. > >Article: 13110
Hi, I have to programme some xc40125xv from a 68360. The FPGAs are in synchronous paripheral mode. D[7..0] from the FPGAs are connected to D[31..24] from the 68k. CCLK is generated from a MAX7128, as the others control signals (/prog and /init). /init has an external pull up tied to 3v3. To programm, I do: - set /prog and /init down, - wait a few us (about 50 us), - release /init and set /prog high, - wait for /init to go high, - send a first CCLK pulse (320ns high), - put an 8 bits data on the bus and send 8 CCLK pulses (data are remove before the seconde pulse, pulses are generated by a control register in the MAX7128), - look if /init has gone down (no wait), - send the next byte (last datas are already in, due to 68k timmings) - and so on (send byte and look /init) for complete data (349630 bytes) - if /init goes down during the process (error!), stop it and show how many bytes were sent - at the end, look if done pin is high (fed up) and I have a probleme: after 100-150 bytes (it allways changes), the process stop, due to a low /init. and I just don't understand why. If someone could help me, I would be very gratefull, because it's for my diploma project and I'm stuck there and I don't know how to go on. Thanks every body, SebastienArticle: 13111
glenn kubota wrote in message <364E1429.91883AE8@earthlink.net>... >i've got a project where i'm looking at using CPLDs from either Altera >or Xilinx. it looks like they both have chips that will fit the bill. >my question, however, is what're the relative pros and cons of Xilinx >Foundation vs. Altera Max Plus? what's easier to learn? what will serve >me better in the future? > >thanks, >glenn k. > > I've been using both vendors for mainly CPLD designs. They both have their strengths in both tools and silicon, and they don't remain static. That said here are some of my thoughts. Tools: Maxplus II is easier to use, but Xilinx has made big improvements since introducing foundation, and Altera is not without their weaknesses. If you are doing any serious VHDL design you will find the Altera VHDL somewhat limited. Since adopting FPGA Express, Xilinx has pulled ahead here. Of course if you have the budget, they both support 3rd party synthesis tools. Also you will find the Altera simulator pretty basic. I chose to buy my own VHDL simulator anyway, so that's not an issue for me. Chips: The 7K parts vs the 9500's is a bit of a saw off. The 7K has some blazingly fast clock rates, but the 9500's product term sharing system can make for some very nice wide logic functions. The 7K also has a neat feature where you can bypass the logic and get sub 3ns setup times! Have to watch the newer parts though. It looks like the 9500XL's may have addressed the low clock frequency problem. Good Luck SteveArticle: 13112
Try http://www.optimagic.com/tutorials.html On Mon, 16 Nov 1998, Utku Ozcan wrote: > Date: Mon, 16 Nov 1998 17:26:59 +0200 > From: Utku Ozcan <ozcan@netas.com.tr> > Newsgroups: comp.arch.fpga, comp.cad.synthesis, comp.lang.vhdl > Subject: Re: Looking for a good documentation on FPGA > > Steven K. Knapp wrote: > > > > You can find some tutorial information via The Programmable Logic Jump > > Station at http://www.optimagic.com/tutorial.html. > > this link doesn't work > > utku > > > > > Also, you may want to check out The Programmable Logic Bookstore at > > http://www.optimagic.com/books.html#VHDL. > > > > ----------------------------------------------------------- > > Steven K. Knapp > > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > > E-mail: sknapp@optimagic.com > > Web: http://www.optimagic.com > > ----------------------------------------------------------- > > > > ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>... > > >Dear all, > > > > > >I am looking for a good documentation on programming FPGA's and > > >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn > > >more about FPGA's and ASIC's. > > > > > >Thank you. > > > > >Article: 13113
I have been using Altera's EPM5128 devices since they came out. I am using increasing quantities of them at $55 a pop. Is there a cheaper alternative? Arnold Beland acbel@worldnet.att.netArticle: 13114
In article <364ff418.2246316251@firewall>, yves@px.uk.com (Yves Tchapda) wrote: > > Hi Shail, > Technically speaking, there is no advantage of Big-Endianness over > Little-Endianness. Intel processors are predominantly Little-Endian, > while Motorola processors are Big-Endian. Choosing one over the other > depends primarily on the overall system. I'm not totally convinced. Why do Intel designers choose an Endianness that is, well, counter-intutive? Take a look at an x86 memory dump to know what I mean... Are you sure there's no difference in the gate counts required to make a system Small or Big Endian? Maybe one of them requires much fewer gates to implement... --Shail Bains Silicon Automation Systems Ltd. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13115
After the leading string of eight '1' bits, is the pattern 0,0,1,0 (see page 4-49 of the 1/98 data book). then 24 length count bits, then 4 more '1's. Total of 40 bits of header. If you are clocking everything correctly, you should see the exact same stuff with a 1 clock delay on the DOUT pin (right next to the DIN pin). Check that the header is coming out and it looks correct. The out going header is EXACTLY what the chip thought it got as an incomming header, so if it is incorrect, then the chip internally has not got a valid header. The random failure position suggests a clocking problem, such as a non-clean rising and falling edge of the clock. You need to check this with a 300MHz (or faster) scope. Remember to check the falling edge, as a glitch on the falling edge can look like a rising edge. Given your problem description, this seems quite likely. Philip Freidin. In article <36504487.0@dinews.epfl.ch> serard@lslsun.epfl.ch (Sebastien Erard) writes: >Hi, > >I have to programme some xc40125xv from a 68360. The FPGAs are in >synchronous paripheral mode. D[7..0] from the FPGAs are connected >to D[31..24] from the 68k. CCLK is generated from a MAX7128, as the >others control signals (/prog and /init). /init has an external >pull up tied to 3v3. > >To programm, I do: > >- set /prog and /init down, >- wait a few us (about 50 us), >- release /init and set /prog high, >- wait for /init to go high, >- send a first CCLK pulse (320ns high), >- put an 8 bits data on the bus and send 8 CCLK pulses > (data are remove before the seconde pulse, pulses are generated by > a control register in the MAX7128), >- look if /init has gone down (no wait), >- send the next byte (last datas are already in, due to 68k timmings) >- and so on (send byte and look /init) for complete data (349630 bytes) > >- if /init goes down during the process (error!), stop it and show how > many bytes were sent > >- at the end, look if done pin is high (fed up) > > >and I have a probleme: after 100-150 bytes (it allways changes), the >process stop, due to a low /init. and I just don't understand why. >If someone could help me, I would be very gratefull, because it's >for my diploma project and I'm stuck there and I don't know how to >go on. > >Thanks every body, SebastienArticle: 13116
actually intuitiveness depends on how you define it :-). It can be argued that little endian is more intuitive. The Least Significant byte is at the LS address is what you get with little endian which frankly makes sense. You are thinking from the point of view of a human and that POV is not suitable for computers. You should think about increasing byte addresses giving you more of the bytes. Also when you sign extend a number it is nice if its address doesn't change. shailbains007@my-dejanews.com wrote: >In article <364ff418.2246316251@firewall>, > yves@px.uk.com (Yves Tchapda) wrote: >> >> Hi Shail, >> Technically speaking, there is no advantage of Big-Endianness over >> Little-Endianness. Intel processors are predominantly Little-Endian, >> while Motorola processors are Big-Endian. Choosing one over the other >> depends primarily on the overall system. > >I'm not totally convinced. Why do Intel designers choose an Endianness that >is, well, counter-intutive? Take a look at an x86 memory dump to know what I >mean... Are you sure there's no difference in the gate counts required to >make a system Small or Big Endian? Maybe one of them requires much fewer >gates to implement... > >--Shail Bains >Silicon Automation Systems Ltd. > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 13117
I have worked with both Big-Endian and Little-Endian types. I see no particular advantage to either, except one or the other is usually required to match up with the software used to compile or assemble programs, and ICE equipment for debugging. There might be an advantage to one or the other when matching data structures to hardware in specific designs (especially with address/data buses instead of separate address and data buses), but this has not been important in my experience. I do agree that byte memory dumps for structures larger than bytes (especially for bit fields which span between bytes) are generally less intelligible with Little-Endian types, but that appears to be the only advantage of Little-Endian types. Russell May On Mon, 16 Nov 1998 17:18:00 GMT, shailbains007@my-dejanews.com wrote: >In article <364ff418.2246316251@firewall>, > yves@px.uk.com (Yves Tchapda) wrote: >> >> Hi Shail, >> Technically speaking, there is no advantage of Big-Endianness over >> Little-Endianness. Intel processors are predominantly Little-Endian, >> while Motorola processors are Big-Endian. Choosing one over the other >> depends primarily on the overall system. > >I'm not totally convinced. Why do Intel designers choose an Endianness that >is, well, counter-intutive? Take a look at an x86 memory dump to know what I >mean... Are you sure there's no difference in the gate counts required to >make a system Small or Big Endian? Maybe one of them requires much fewer >gates to implement... > >--Shail Bains >Silicon Automation Systems Ltd. > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13118
I have worked with both Big-Endian and Little-Endian types. I see no particular advantage to either, except one or the other is usually required to match up with the software used to compile or assemble programs, and ICE equipment for debugging. There might be an advantage to one or the other when matching data structures to hardware in specific designs (especially with address/data buses instead of separate address and data buses), but this has not been important in my experience. I do agree that byte memory dumps for structures larger than bytes (especially for bit fields which span between bytes) are generally less intelligible with Little-Endian types, but that appears to be the only disadvantage of Little-Endian types. Russell May On Mon, 16 Nov 1998 17:18:00 GMT, shailbains007@my-dejanews.com wrote: >In article <364ff418.2246316251@firewall>, > yves@px.uk.com (Yves Tchapda) wrote: >> >> Hi Shail, >> Technically speaking, there is no advantage of Big-Endianness over >> Little-Endianness. Intel processors are predominantly Little-Endian, >> while Motorola processors are Big-Endian. Choosing one over the other >> depends primarily on the overall system. > >I'm not totally convinced. Why do Intel designers choose an Endianness that >is, well, counter-intutive? Take a look at an x86 memory dump to know what I >mean... Are you sure there's no difference in the gate counts required to >make a system Small or Big Endian? Maybe one of them requires much fewer >gates to implement... > >--Shail Bains >Silicon Automation Systems Ltd. > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13119
> I can't verify the details of offset and commands. But I can verify that > the process works. Does that work for NT????? Thanks, AustinArticle: 13120
Hi, I intend to implement some of my circuit functionality on a Xilinx Spartan FPGA. The signals are time critical but I know it can be implemented in this FPGA. My question is that does the actual pinout make a difference on the timing? (I want to do board layout first and then work on the FPGA configuration so I was wondering if I could arbitarily assign I/O pins). TIA, Jai.Article: 13121
Not that ModelSim is the most expensive but if you are interested in a good ratio of price-feature-performance functionality then check out www.model.com. APS wrote in message <364DE427.2C8C962D@associatedpro.com>... >Check out the PeakVHDL suite at http://www.associatedpro.com It can handle all >the major FPGA vendors, has synthesis and simulation, and is a bit less money >than the ALDEC suite. > >Ido Kleinman wrote: > >> Dear all, >> >> I am looking for a good VHDL development (compiling, simulation, gate-level >> sim/FSM support, Testbench generator) software tool. I need it to have a >> comfortable interface to maxplus2 for exporting compiled designs for >> synthesis in Altera's devices. >> I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and >> quite happy with it, but I have a slow internet connection, therefore, >> before I start downloading tens of megabytes again, I would like to know if >> there are any other compact software tools worth looking at...? >> >> Anyone got any experience with Aldec's tool? >> Are the big ones (Synopsys, Examplar..) worth the investment? >> >> -- >> >> Ido Kleinman. >> kleinn@mail.biu.ac.il > >-- >__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > >Richard Schwarz, President EDA & Engineering Tools >Associated Professional Systems (APS) http://www.associatedpro.com >3003 Latrobe Court richard@associatedpro.com >Abingdon, Maryland 21009 >Phone: 410.569.5897 Fax:410.661.2760 > >__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > >Article: 13122
My name is Douglas. I've been a student of Computer Science and Electronics Engineering Technology for several years now. Recently I've moved to Ogden, UT. In the near future, I plan to attend Weber State University to finish my BSCS. As a special Independant-Study project, I'm going to attempt a port of the Linux operating system to the Zilog Z380, a 32-bit successor to the Zilog Z80. I'm looking for references to PROTECTED MEMORY, how it is implemented, and perhaps some design examples. I will attempt to also design an external memory management unit to implement memory protection for this processor, using an FPGA or several MSI/LSI and CPLD components. At the present time, I'm trying to gather information, but have found almost nothing -- application notes or theory, which would better-explain an actual implementation of protected memory for a new processor. Any references, contacts, or pointers you might provide would be most-appreciated. Cordially, Douglas Beattie Jr. http://www2.whidbey.net/~beattidp/Article: 13123
Group the signals in a way that make sense for the circuit board and I don't think you'll have problems with speed (you won't split a data bus all around the package, would you? I don't think so, you'll group them together). Do at least one place and route to make sure you don't have a bad pin assignment (like a signal pin connected to power or ground, or something like that). jai wrote in message <3650956A.7DF7@hotmail.com>... >Hi, > >I intend to implement some of my circuit functionality on a Xilinx >Spartan FPGA. The signals are time critical but I know it can be >implemented in this FPGA. >My question is that does the actual pinout make a difference on the >timing? (I want to do board layout first and then work on the FPGA >configuration so I was wondering if I could arbitarily assign I/O pins). > >TIA, >Jai.Article: 13124
I just saw an $89 starter kit for students from Xilinx in a San Jose bookstore last weekend. I didn't get the deytails. Go to www.clbooks.com. If you work for a company, your local Xilinx rep should have free to low-cost CD rom starter packages. Peff Hlebasko@t-online.de wrote: > I am looking for information for some low cost FPGA development tools for > learning. I am trying to improve my "skill set" on my own and I can't > afford multiple thousand dollar tool sets. > > Thanks. > > Joseph Hlebasko
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