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Austin posted: |----------------------------------------------------------| |"[..] neutrons at sea level are causing upsets, [..] | | | |[..] | | | |I suggest that if you are not thinking about single | |event effects, you should be, and demanding your vendor | |show you the proof of their design efforts in this regard.| | | |[..]" | |----------------------------------------------------------| Aye. |---------------------------------------------------| |"There is a reason why Xilinx FPGA devices are | |finding their way into many high availability | |and high reliability applications: we are the | |only choice -- there is no competition whatsoever."| |---------------------------------------------------| Are you sure you have not been brainwashed by your own P.R. department? I commend Xilinx's acknowledgement of the existence of single-event transients (my attempt at a Ph.D. in electronic engineering was ruined by a supposed tutor who used to work for the European Space Agency for four years who only ever spoke about single-event upsets even though I had applied to the university with an explicit emphasis on single-event transients in my application essay). How can you say that people can only buy from Xilinx instead of from, for example, Aeroflex? Regards, Colin Paul Gloster, unemployed and hungryArticle: 131126
Colin, Yes. One choice. No competition whatsoever. I really wish there was some competition, as I believe that competition is healthy for an industry. But, sadly, there is none. Nada. Nil. If you want 405PPC, EMAC, DSP, 200K LUT, etc, there is one, and only one Grade V space qualified vendor: Xilinx. http://www.xilinx.com/support/documentation/aerospace_qpro-r.htm On sale right now, and being designed into all those fancy platforms (to be flown starting in 2009). No PR here, just solid purchase orders, shipments, and revenue. We have progressed from "interesting technology, but we can't use you in space" a few years back, to "critical enabler, must use you in this generation like we have in the previous two successful missions to meet the mission requirements." AustinArticle: 131127
Roger wrote: > Will there be a 64 bit WebPack version of ISE in the near future? Is it really necessary? WebPack doesn't support parts large enough to exhaust the memory avialable in the 32-bit world.Article: 131128
I have the following scenario in verilog which i need to convert to vhdl always if reset . . . else case . . . end case // set default values case. . . . . end case end How do I convert this to vhdl. I am lost on what the equivalent of // set default values and the case statements after that would be in VHDL. From webmaster@nillakaes.de Fri Apr 11 11:11:59 2008 Path: flpi142.ffdc.sbc.com!flpi104.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin2!goblin.stu.neva.ru!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <47ffa9eb$0$584$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: ISE 9.2 and Windriver Newsgroups: comp.arch.fpga Date: Fri, 11 Apr 2008 20:11:59 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 11 Organization: CNNTP NNTP-Posting-Host: d5d89374.read.cnntp.org X-Trace: DXC=4A`ofk]n[knXMoNd=::YAkWoT\PAgXa?aY70?_8WM9Wm1P5d:S1^>6cdlT:^LKmYjj]<X20T9?0_bSR5>dB75[io X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143549 X-Received-Date: Mon, 21 Apr 2008 19:24:59 EDT (flpi142.ffdc.sbc.com) Hi, my Windriver trial period has expired, and then I found out that the license costs $900 ?!? Is it possible to bypass windriver - e.g. by using the xilinx usb-cable ? I'm currently using the Digilent parallel cable. Best Regards ThorstenArticle: 131129
Check out the VHDL Language Reference Guide. on-line version: http://staffwww.itn.liu.se/~andki/vhdl_refguide/ Windows help version: http://www.iol.ie/~dmurray/Prism/vhdlhlp.zipArticle: 131130
On Apr 11, 1:08 pm, FP <FPGA.unkn...@gmail.com> wrote:
> I have the following scenario in verilog which i need to convert to
> vhdl
>
> always
> if reset
> .
> .
> .
> else
> case
> .
> .
> .
> end case
> // set default values
> case.
> .
> .
> .
> .
> end case
> end
>
> How do I convert this to vhdl. I am lost on what the equivalent of //
> set default values and the case statements after that would be in
> VHDL.
I'm not a Verilog person, but I do have a book that shows both VHDL
and Verilog code ("HDL Chip Design", by Douglas J. Smiths). The book
shows that "//" is a Verilog comment. So, "// set default values" is
a comment. The Verilog "default" is the same as the VHDL "when others
=>". "always@ .. end" is the same as a VHDL "process .. end
process". In your case (no pun intended), it's a combinatorial
process.
HTH
-Dave Pollum
Article: 131131I understand the original post is not about Blogs, but... Maybe I am too old to simply jump on new fashioned things like blogs, but why should a good thing be abandoned because so many cows like to follow each other instead of actually look around and go to the best place? Blogs may be a faster way to communicate but like other internet oriented things all they do is take more time in communication. Every new fashion in the internet is demanding more time online instead of improving our time at work (or at home). For instance, the complexity of the web pages and their servers stole a lot of processing time, bandwitdh and makes easy to loose important information in the process. When I access Xilinx's webpage usually the first thing I do is to type a question regarding what I want to read there (unless I know exactly where it is). So, I did test if I could find the messages you (Austin) and Peter have left in the blogs... and: no results. Try the word: blogosphere or "5.5 million" (in the P.Alfke text). No results. So, what is the point of having a blog page? To waste more time diging where it is? And what about the time you, Peter, Ken and others use to make dialogs in those blogs? It is just in the beggining.... I wonder where it goes in a year or two. I have to say that your (whole Xilinx team) efforts to answer directly a lot of questions from users are a real marvel. You must use at least half day just to answer emails and threads in this group... In my opinion information must be easy to get, use less time as possible to build it up (or to retrieve) and does not need to follow dotCom fashion. Best regards, AugustoArticle: 131132
Hi, I have the following problem: I have designed a peripheral with a Fsl bus. It works fine when I create and EDK Project with micoblaze. Now I wanted to switch to a Virtex 4 with a Power PC. I know the there exists and Fcb2Fsl bus brigde. I searched the xilinx web site and google for some examples or tutorial how to use and fsl peripheral with the PPC. UnfortunatelyI couldn't find any so far. Reading the datasheets I found I tried the following: I created an EDK project using PPC. I added and FCB Bus, a Fcb2Fsl bus bridge, 2 Fsl Buses (one for slave one for master) and my peripheral. I connected them also in this order. so far the hardware synthesizes but i cant talk to my peripheral. With microblaze there existed a Fsl bus slot that was defined in parameters.h. But I can't find something similar for the Fsl bus when I'm using the PPC. (I understand that the PPC doesn't have a direct Fsl bus integrated). But shouldn't there be something similar? Like a slot id for the Bus bridge or the Fcb bus? Can somebody point me into the right directions? Perhaps a code sample or a tutorial? And hints would be appreciated thanks UrbanArticle: 131133
On Apr 11, 2:17 pm, Dave Pollum <vze24...@verizon.net> wrote:
> On Apr 11, 1:08 pm, FP <FPGA.unkn...@gmail.com> wrote:
>
>
>
> > I have the following scenario in verilog which i need to convert to
> > vhdl
>
> > always
> > if reset
> > .
> > .
> > .
> > else
> > case
> > .
> > .
> > .
> > end case
> > // set default values
> > case.
> > .
> > .
> > .
> > .
> > end case
> > end
>
> > How do I convert this to vhdl. I am lost on what the equivalent of //
> > set default values and the case statements after that would be in
> > VHDL.
>
> I'm not a Verilog person, but I do have a book that shows both VHDL
> and Verilog code ("HDL Chip Design", by Douglas J. Smiths). The book
> shows that "//" is a Verilog comment. So, "// set default values" is
> a comment. The Verilog "default" is the same as the VHDL "when others
> =>". "always@ .. end" is the same as a VHDL "process .. end
> process". In your case (no pun intended), it's a combinatorial
> process.
> HTH
> -Dave Pollum
The presence of "if reset" could imply that this is a clocked process,
not combinatorial. We can't tell because the "always" statement is not
included, and we cannot tell if the block is also sensitive to posedge
clock.
Andy
Article: 131134
Hello
I am working on playing simple 11 kbytes/second 8bit WAV data through my
FPGA stereo jack. I used the following synthesis to play the sound data
delivered through the serial interface. I also used the mono_dac demo
module.
My problem is I am getting a very high noise to signal ratio although I
can hear the speech. The sound file plays crystal clear on my host
computer.
Another problem I have with simple WAV file is I don't know how to
extract volume information. So I hardwired 3'b100 as the volume.
I could use some help figuring out the source of the high noise. Is this
caused by timing issue?
Fei
WAV file info:
File : 11k8bitpcm.wav
Length : 152312
RIFF : 152304
WAVE
fmt : 16
Format : 0x1 => WAVE_FORMAT_PCM
Channels : 1
Sample Rate : 11025
Block Align : 1
Bit Width : 8
Bytes/sec : 11025
data : 152267
End
----------------------------------------
Sample Rate : 11025
Frames : 152267
Channels : 1
Format : 0x00010005
Sections : 1
Seekable : TRUE
Duration : 00:00:13.811
Signal Max : 128 (0.00 dB)
`include "timescale.v"
module serial_snd(
clk,
rx,
tx,
led0,
led1,
led2,
aud_l,
aud_r
);
parameter clk_freq=50000000;
parameter blink_freq = 25;
(* LOC="E12" *) input clk;
(* LOC="F16" *) input rx;
(* LOC="E15" *) output tx;
(* LOC="R20" *) output led0;
(* LOC="T19" *) output led1;
(* LOC="U20" *) output led2;
(* LOC="Y10" *) output aud_l;
(* LOC="V10" *) output aud_r;
wire data_ready;
wire RxD_idle;
wire [7:0] rx_data;
reg [blink_freq:0] count = 0;
// serial port receiver
async_receiver #(.clk_freq(clk_freq)) ar(
.clk(clk),
.RxD(rx),
.RxD_data_ready(data_ready),
.RxD_data(rx_data),
.RxD_idle(RxD_idle)
);
// Serial port transmitter
async_transmitter #(.clk_freq(clk_freq)) serializer(
.clk(clk),
.TxD(tx),
.TxD_start(data_ready),
.TxD_data(rx_data)
);
// Blink LED0 with a frequency slightly slower than once per second
assign led0 = count[blink_freq];
assign led2 = RxD_idle;
// LED1 lights on when there is incoming data from serial line, it lasts
2^20 clks
state_holder #(.clk_hold(20)) bl(clk, data_ready, led1);
//PWM audio(
// .clk(clk),
// .PWM_in(rx_data),
// .PWM_out(aud_l)
//);
wire audio;
FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk));
mono_dac mono(
.signed_data(rx_data),
.volume(3'b100),
.audio(audio),
.clk(clk)
);
assign aud_r = 8'bz;
always @(posedge clk) begin
count <= count + 1;
end
endmodule
Article: 131135Lars wrote: > Aaaaarg!!! I was after "Six Easy Pieces (Non-Synchronous Circuit > Tricks)" and it seems that didn't make it to the White Papers. And the > web archive link lacks the images :( > I guess I will have to ruffle through my stack of old "useful > printouts" for that one, if it is there... Not high-tec stuff but > useful to explain basic priciples to beginners. > > Thanks anyway, and Austin and Peter; if you read this, please use your > influence to correct some of the obvious mistakes made by the web- > people at Xilinx! Amazing - how hard can it be to get that right ? -jgArticle: 131136
On Apr 11, 4:02=A0pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Lars wrote: > > Aaaaarg!!! I was after "Six Easy Pieces (Non-Synchronous Circuit > > Tricks)" and it seems that didn't make it to the White Papers. And the > > web archive link lacks the images :( > > I guess I will have to ruffle through my stack of old "useful > > printouts" for that one, if it is there... Not high-tec stuff but > > useful to explain basic priciples to beginners. > > > Thanks anyway, and Austin and Peter; if you read this, please use your > > influence to correct some of the obvious mistakes made by the web- > > people at Xilinx! > > =A0 Amazing - how hard can it be to get that right ? > > -jg We try to please. If Lars had only given his real and usable e-mail address, he would have had the properly formatted information in minutes... Peter AlfkeArticle: 131137
Peter Alfke wrote: > On Apr 11, 4:02 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: >> Lars wrote: >> >>> Thanks anyway, and Austin and Peter; if you read this, please use >>> your influence to correct some of the obvious mistakes made by the >>> web- people at Xilinx! >> >> Amazing - how hard can it be to get that right ? >> >> -jg > > We try to please. > If Lars had only given his real and usable e-mail address, he would > have had the properly formatted information in minutes... > Peter Alfke ...along with 593 emails offering pills to give him a 13 inch penis, and 264 emails offering a share of "an abandoned sum of$15million USD(Fifteen million US dollars)only" from "FOREIGN REMITTANCE DEPT. BANK OF AFRICA ( BOA) OUAGADOUGOU, BURKINA FASO". Why not leave the TechXclusives on the website until they've been turned into whatever 'corporate image thing' the new VP has decided on? Love you all loads, Syms.Article: 131138
On Apr 11, 2:32 pm, Fei Liu <fei....@gmail.com> wrote: > Hello > I am working on playing simple 11 kbytes/second 8bit WAV data through my > FPGA stereo jack. I used the following synthesis to play the sound data > delivered through the serial interface. I also used the mono_dac demo > module. > > My problem is I am getting a very high noise to signal ratio although I > can hear the speech. The sound file plays crystal clear on my host > computer. <.. snip ..> > > //PWM audio( > // .clk(clk), > // .PWM_in(rx_data), > // .PWM_out(aud_l) > //); > wire audio; > FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk)); > > mono_dac mono( > .signed_data(rx_data), > .volume(3'b100), > .audio(audio), > .clk(clk) > ); <.. snip ..> 8-bit WAV files use offset binary rather than signed values (i.e. 0 is the most negative, 128 is mid-scale 255 is full-scale) kevinArticle: 131139
Symon wrote: > Why not leave the TechXclusives on the website until they've been turned > into whatever 'corporate image thing' the new VP has decided on? > > Love you all loads, Syms. Or, a web stub called www.xilinx.com\TechXclusives, that the marketdroids don't need to know about - tell them it's museum archive stuff, for history students, and they'll never go there! -jgArticle: 131140
On Apr 11, 10:02 pm, kevin93 <ke...@whitedigs.com> wrote: > On Apr 11, 2:32 pm, Fei Liu <fei....@gmail.com> wrote: > > > Hello > > I am working on playing simple 11 kbytes/second 8bit WAV data through my > > FPGA stereo jack. I used the following synthesis to play the sound data > > delivered through the serial interface. I also used the mono_dac demo > > module. > > > My problem is I am getting a very high noise to signal ratio although I > > can hear the speech. The sound file plays crystal clear on my host > > computer. > <.. snip ..> > > > //PWM audio( > > // .clk(clk), > > // .PWM_in(rx_data), > > // .PWM_out(aud_l) > > //); > > wire audio; > > FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk)); > > > mono_dac mono( > > .signed_data(rx_data), > > .volume(3'b100), > > .audio(audio), > > .clk(clk) > > ); > > <.. snip ..> > > 8-bit WAV files use offset binary rather than signed values (i.e. 0 is > the most negative, 128 is mid-scale 255 is full-scale) > > kevin Ah, that's sweet to know. Where can I find similar information for 16bit and even 32bit WAV files? Thanks a lot! FeiArticle: 131141
On Apr 11, 7:02 pm, kevin93 <ke...@whitedigs.com> wrote: > On Apr 11, 2:32 pm, Fei Liu <fei....@gmail.com> wrote: > > > Hello > > I am working on playing simple 11 kbytes/second 8bit WAV data through my > > FPGA stereo jack. I used the following synthesis to play the sound data > > delivered through the serial interface. I also used the mono_dac demo > > module. > > > My problem is I am getting a very high noise to signal ratio although I > > can hear the speech. The sound file plays crystal clear on my host > > computer. > <.. snip ..> > > > //PWM audio( > > // .clk(clk), > > // .PWM_in(rx_data), > > // .PWM_out(aud_l) > > //); > > wire audio; > > FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk)); > > > mono_dac mono( > > .signed_data(rx_data), > > .volume(3'b100), > > .audio(audio), > > .clk(clk) > > ); > > <.. snip ..> > > 8-bit WAV files use offset binary rather than signed values (i.e. 0 is > the most negative, 128 is mid-scale 255 is full-scale) > > kevin And to convert signed to offset or to convert offset to signed you just have to invert the top bit (MSB). Since it is so easy, it might be worth it to just try it and see if it works. Alan NishiokaArticle: 131142
Hi, I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera. I use only a few components from the unisim lib so may not be a big effort to write a vhdl component for each one of them, providing I know the details what they do exactly. Can someone help me with the details of the following components: SRL16E MULT18x18 RAMB16_S18 RAMB16_S9 RAMB16_S4 RAMB16_S18_S18 Or maybe there is a clever way of doing this. Help is appreciated. Thanks. Luis C.Article: 131143
LC wrote: > I'm trying to port some code from Xilinx to Altera > and I'm in a bit of a problem by not having UNISIM lib > on Altera. > > I use only a few components from the unisim lib so may > not be a big effort to write a vhdl component for each > one of them, providing I know the details what they do > exactly. > > Can someone help me with the details of the following > components: > > SRL16E > MULT18x18 > RAMB16_S18 > RAMB16_S9 > RAMB16_S4 > RAMB16_S18_S18 This may be helpful: http://toolbox.xilinx.com/docsan/xilinx82/books/docs/lib/lib.pdfArticle: 131144
Hi I was recently very disappointed with the performance of Xilinx systemACE, but the problem was in my head, a thinking problem and too little homework - the issue is not related to systemACE or CF cards, but it is present by almost all flash cards - the "controller overhead" very short: any flash-card (except smartmedia or x-d) will only give some 1-2MB/s data rate when using single sector read commands. Ok it may differ a little, but by NO MEANS the advertised data rates can be achieved without multi-sector reads so there is NO WAY to optimize systemACE driver to get better performance as long the complete fat library is not optimized to read data from card in large junks that are sent to CF card as multi-sector reads PS, if there is some trick, or if some CF/SD card has VERY small controller overhead i would be interested to know Antti http://antti-lukats.blogspot.com/ From webmaster@nillakaes.de Sat Apr 12 05:49:45 2008 Path: flpi142.ffdc.sbc.com!flpi104.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!news.karotte.org!feeder06.uucp-net.de!news.uucp.at!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4800afe5$0$580$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: simple example with timing problems Newsgroups: comp.arch.fpga Date: Sat, 12 Apr 2008 14:49:45 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 16 Organization: CNNTP NNTP-Posting-Host: 16d2b12f.read.cnntp.org X-Trace: DXC=d]Se7]4_FRHhh8ai[0e3CKWoT\PAgXa?Af7hk0B9Y_hE1P5d:S1^>6CdlT:^LKmYjJCM_AgTRJ7gMl8iEgG6o>d@ X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143566 X-Received-Date: Mon, 21 Apr 2008 19:23:55 EDT (flpi142.ffdc.sbc.com) Hi, I wrote a simple stop watch for the Spartan 3 StarterKit. Unfortunately it seems to be unstable, i.e. sometimes when I release the button, the counter doesn't stop as it should. During synthesis I get a warning - about timing I think. Can you have a look at the program and advice me how to avoid this instability ?? http://tokisworld.org/spartan3/stopwatch.tbz Best regards Thorsten From webmaster@nillakaes.de Sat Apr 12 06:37:02 2008 Path: flpi142.ffdc.sbc.com!flpi104.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!newsfeed.velia.net!newsfeeder.dynfx.net!weretis.net!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4800baf9$0$580$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Re: simple example with timing problems Newsgroups: comp.arch.fpga Date: Sat, 12 Apr 2008 15:37:02 +0200 References: <4800afe5$0$580$6e1ede2f@read.cnntp.org> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 16 Organization: CNNTP NNTP-Posting-Host: 393b7a1b.read.cnntp.org X-Trace: DXC=bXS<Q5mY8RF?ZNgFG`EG\IWoT\PAgXa?Af7hk0B9Y_hE1P5d:S1^>6CdlT:^LKmYjJH>dRZ;jYR:DXWdc^NffR?D X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143567 X-Received-Date: Mon, 21 Apr 2008 19:24:38 EDT (flpi142.ffdc.sbc.com) Thorsten Kiefer wrote: > Hi, > I wrote a simple stop watch for the Spartan 3 StarterKit. > Unfortunately it seems to be unstable, i.e. sometimes > when I release the button, the counter doesn't stop as > it should. During synthesis I get a warning - about > timing I think. Can you have a look at the program > and advice me how to avoid this instability ?? > > http://tokisworld.org/spartan3/stopwatch.tbz > > Best regards > Thorsten OK, I found the bug......Article: 131145
On Apr 12, 12:59 pm, LC <cupidoREM...@mail.ua.pt> wrote:
>
> Can someone help me with the details of the following
> components:
>
> SRL16E
In Verilog-2001:
module SRL16E #(
parameter INIT=16'h0000
) (
output Q,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
reg [15:0] r;
assign Q = r[{A3, A2, A1, A0}];
initial
r = INIT;
always @(posedge CLK)
if (CE)
r <= {r[14:0], D};
endmodule
Article: 131146"Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message news:4800baf9$0$580$6e1ede2f@read.cnntp.org... > Thorsten Kiefer wrote: > >> Hi, >> I wrote a simple stop watch for the Spartan 3 StarterKit. >> Unfortunately it seems to be unstable, i.e. sometimes >> when I release the button, the counter doesn't stop as >> it should. During synthesis I get a warning - about >> timing I think. Can you have a look at the program >> and advice me how to avoid this instability ?? >> >> http://tokisworld.org/spartan3/stopwatch.tbz >> >> Best regards >> Thorsten > > OK, I found the bug...... Good that you found it on your own. In the future, if you do expect to get any help from any newsgroup you should put a bit more thought into your posting. Statements like "During synthesis I get a warning - about timing I think" are completely useless, I'm 100% confident that the synthesis tool did not report that text. Not posting any code doesn't give anyone anything to go on either. Basically, if you would like help, don't make it difficult on the potential helpers. KJ From webmaster@nillakaes.de Sat Apr 12 11:57:54 2008 Path: flpi142.ffdc.sbc.com!flpi104.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4801062d$0$580$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Re: simple example with timing problems Newsgroups: comp.arch.fpga Date: Sat, 12 Apr 2008 20:57:54 +0200 References: <4800afe5$0$580$6e1ede2f@read.cnntp.org> <4800baf9$0$580$6e1ede2f@read.cnntp.org> <h77Mj.1439$pS4.461@newssvr13.news.prodigy.net> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 39 Organization: CNNTP NNTP-Posting-Host: 7fd1c66e.read.cnntp.org X-Trace: DXC=`;oRWA<9B7O]ERPN0>`82KWoT\PAgXa?Af7hk0B9Y_hE1P5d:S1^>6CdlT:^LKmYjJHXbhg<K4>NDl8iEgG6o>d@ X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143570 X-Received-Date: Mon, 21 Apr 2008 19:24:37 EDT (flpi142.ffdc.sbc.com) KJ wrote: > > "Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message > news:4800baf9$0$580$6e1ede2f@read.cnntp.org... >> Thorsten Kiefer wrote: >> >>> Hi, >>> I wrote a simple stop watch for the Spartan 3 StarterKit. >>> Unfortunately it seems to be unstable, i.e. sometimes >>> when I release the button, the counter doesn't stop as >>> it should. During synthesis I get a warning - about >>> timing I think. Can you have a look at the program >>> and advice me how to avoid this instability ?? >>> >>> http://tokisworld.org/spartan3/stopwatch.tbz >>> >>> Best regards >>> Thorsten >> >> OK, I found the bug...... > > Good that you found it on your own. > > In the future, if you do expect to get any help from any newsgroup you > should put a bit more thought into your posting. Statements like "During > synthesis I get a warning - about timing I think" are completely useless, > I'm 100% confident that the synthesis tool did not report that text. Not > posting any code doesn't give anyone anything to go on either. > > Basically, if you would like help, don't make it difficult on the > potential helpers. > > KJ OK, I'll follow your advice ;) TKArticle: 131147
i got a problem with the Spartan 3E starter kit from Xilinx, no matter what Mode pins are set for, the DONE LED is always turned on when i power on the board. I cannot connect to the board via JTAG pin headers either. All the voltages are correct. What could be the problem ? any thing i can do to debug it ? i have another Spartan 3E board and it works fine.Article: 131148
On 12 Apr., 21:00, kislo <kisl...@student.sdu.dk> wrote: > i got a problem with the Spartan 3E starter kit from Xilinx, no matter > what Mode pins are set for, the DONE LED is always turned on when i > power on the board. I cannot connect to the board via JTAG pin headers > either. All the voltages are correct. What could be the problem ? any > thing i can do to debug it ? i have another Spartan 3E board and it > works fine. the LED is on even though i hold PROG_B lowArticle: 131149
On Apr 11, 7:11 pm, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > Hi, > my Windriver trial period has expired, and then > I found out that the license costs $900 ?!? > Is it possible to bypass windriver - e.g. > by using the xilinx usb-cable ? > > I'm currently using the Digilent parallel cable. > > Best Regards > Thorsten If you are using Linux, there is an open source driver (http:// rmdir.de/~michael/xilinx/).
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