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Messages from 13125

Article: 13125
Subject: Synthesizeablel fifo
From: James LaLone <lalone@worldnet.att.net>
Date: 17 Nov 1998 00:20:56 GMT
Links: << >>  << T >>  << A >>
Can someone shed light on building a fifo that can be synthesized?
The pointers, and ram, are no problem.  What I'm having problems with
are the flags.  Of course, the fifo that I want to build have
asynchronous read and write clocks.
I've looked over Xilinx applications XAPP051 and XAPP131, but they still
leave me with some implementation questions.

Thanks in advance,
-Jim
Article: 13126
Subject: Re: Board for FPGA ?
From: Jeff Vallier <jeffrey.vallier@smi.siemens.com>
Date: Mon, 16 Nov 1998 16:23:11 -0800
Links: << >>  << T >>  << A >>
If you wanna be cheap, make your own. Only YOU know what peripherals you
will need. I use a Jameco Breadboard (JE27) and a PLCC adapter. The power
supply and clock oscillator are trivial and the data sheet of yor target
FPGA will detail which pins are used for JTAG or serial ROM. The breadboard
will give you plenty of space to add your own I/O. I suggest starting with
a few LEDS and go from there...

Peff

p52mofej@uco.es wrote:

> Where could I find information to make an experimental board for FPGA?
> Thanks.
>
> --
> Jose Moreno
> p52mofej@uco.es
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



Article: 13127
Subject: Re: Big-Endian vs Little-Endian
From: Zoltan Kocsi <root@127.0.0.1>
Date: 17 Nov 1998 12:03:50 +1100
Links: << >>  << T >>  << A >>
shailbains007@my-dejanews.com writes:

> I'm not totally convinced. Why do Intel designers choose an Endianness that
> is, well, counter-intutive? Take a look at an x86 memory dump to know what I

There are arguments for little endian architectures. If you have a multi-byte 
object and you cast it to a smaller entity, your address remains the same.

That is:

	int  x;  /* Ints are at least 16 bits */
	char c;  /* Assume that chars are 8 bits */
	
	x = 10;
	c = *((char *) &x);

On little-endian c will be 10. On big-endian c will be 0.
I like big endian, however, because the dumps are easier to read :-)

Zoltan

-- 
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+
Article: 13128
Subject: Re: Example of clock circuit needed !
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Mon, 16 Nov 1998 20:25:31 -0500
Links: << >>  << T >>  << A >>
Your looking for direct digital synthesis.  Use an accumulator, to which
you add a fixed increment (for constant frequency).  The MSB of the
accumulator is your clock output.  It has the relation:

    f(out)= (N/2^m)*f(clk).  Where m is the size of the accumulator in
bits, N is the increment value and f(clk) is the frequency the
accumulator is clocked (ie how often the increment is added).  You will
have jitter of +/- 1 clock period (of the input clock) on the output, so
you'll need to select your clock frequency, and therefore the accumulator
size for acceptable jitter.  If you require something other than a
digital output, you can use the top k bits of the accumulator to address
a look-up table or to drive some function generator (the top bits form a
phase angle).

Le mer Michel wrote:

> ovilup wrote:
>
> > Hello !
> >
> > I am working on an I2C controller. Now, I am designing the
> > internal clock generator. I have an 1.5 MHz internal clock,
> > from which I have to generate the 100 KHz, 90 KHz, 44 KHz
> > 1.5 KHz SCL clocks.
> >
> > Any examples of such an clock generator would be appreciated !
> >
> > Thank you in advance.
> > OL
>
> Hello
>
> I do not know exactly what it is but I heard about the direct numeric
> synthesis. It is use in the signal generators to privide a wave of a
> specific frequency.
>
> Bye.
> Michel.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13129
Subject: Re: Example of clock circuit needed !
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Tue, 17 Nov 1998 01:30:28 GMT
Links: << >>  << T >>  << A >>
Also, there's the NCO, similar to the DDS.
Accumulator has a programmable "phase step" or the number you add to
the accumulator each 1.5 MHz clock.  Use the MSB bit as your derived
"clock", or the adder's COUT.  This output clock can be fairly finely
tuned to those frequencies you wanted.  Everything is synchronous to
that one 1.5 MHz clock.  Realize that this output is a bunch of pulses
that are not necessary regular; e.g. jitterry (but synchronous).  This
is also somewhat related to that old TTL trick of the "Rate
Multiplier"!  Don't know if you want that kind of output.  Simulate it
and see if its a waveform you can use.  I think I have an example on
my WWW page - look for NCO.  NCOs are a handy trick...

tom coonan
Scientific Atlanta
tcoonan@mindspring.com
www.mindspring.com/~tcoonan

>You are thinking of a phase adder in a technique called DDS or Direct
>Digital Synthesis.
>
>Simon
>=============================
>Le mer Michel <michel.lemer@ago.fr> wrote:
>
>>ovilup wrote:
>>
>>> Hello !
>>>
>>> I am working on an I2C controller. Now, I am designing the
>>> internal clock generator. I have an 1.5 MHz internal clock,
>>> from which I have to generate the 100 KHz, 90 KHz, 44 KHz
>>> 1.5 KHz SCL clocks.
>>>
>>> Any examples of such an clock generator would be appreciated !
>>>
>>> Thank you in advance.
>>> OL
>>
>>Hello
>>
>>I do not know exactly what it is but I heard about the direct numeric
>>synthesis. It is use in the signal generators to privide a wave of a
>>specific frequency.
>>
>>Bye.
>>Michel.
>>
>
>Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm

Article: 13130
Subject: Re: newbie question about timing
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Mon, 16 Nov 1998 20:33:38 -0500
Links: << >>  << T >>  << A >>
The answer is.... IT DEPENDS.  Depends on the required speed of your design,
whether or not you are using the IOB flip-flops, if you are using the
Tri-states on the IOBs and how you have those connected in your design and
so on.  If you are wiring a bus to the part, and are doing anything
resembling arithmetic (or counters) on the data from that bus, you'll want
to arrange the bus along the sides (not top or bottom) of the die with the
lsb's at the bottom to keep from killing the routing.  Take the time to
carefully block out your design and do some basic floorplanning before you
assign the pins and you'll save yourself a bunch of grief.  Also, whereever
possible use the IOB registers instead of routing an unregistered signal to
or from the core.  This decouples the IO timing from the route, and will
often save your bacon later.

jai wrote:

> Hi,
>
> I intend to implement some of my circuit functionality on a Xilinx
> Spartan FPGA. The signals are time critical but I know it can be
> implemented in this FPGA.
> My question is that does the actual pinout make a difference on the
> timing? (I want to do board layout first and then work on the FPGA
> configuration so I was wondering if I could arbitarily assign I/O pins).
>
> TIA,
> Jai.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13131
Subject: Re: Big-Endian vs Little-Endian
From: "Kalyan Gokhale" <kgokhale@execpc.com>
Date: Mon, 16 Nov 1998 20:36:43 -0600
Links: << >>  << T >>  << A >>

>
>I'm not totally convinced. Why do Intel designers choose an Endianness that
>is, well, counter-intutive? >
>--Shail Bains


The reasons are given in an IEEE-Micro Magazine (first issue of first year)
by Intel designers of 8008.


Article: 13132
Subject: Re: DES in VHDL
From: The Bearded Dave <dwp@po.cwru.edu>
Date: Mon, 16 Nov 1998 23:24:32 -0500
Links: << >>  << T >>  << A >>
>It is fully pipelined taking 4700 logic blocks on a Xilinx 4000 FPGA
4700 clbs is a bit big.

I looked at this for my senior project (BS) at school.
I implemented a fully pipelined DES encrypter in <2000 clbs (most of a
4062) and it should be able to run around 75MHZ in a -9. I achieved
around 60 MHz due to routing.(60MHz*64 bits/clock=3.8Gigabits/sec)

Some things to keep in mind if you decide to optimize:
1)No sbox equivalent should be >10 clbs.
2)There are 2 FFs/clb, signal preservation can munch clbs easily

Now, I've got this solution. Anyone have a problem for it? 8-)


   The Bearded Dave             Praise your lord
dwp@po.cwru.edu
"That's it! No more drugs for that man. You know, tar sticks to some
people?"
"Bury your head in the sand go around in circles bury your head in the
sand
 go around in circles"  Front 242

Article: 13133
Subject: Motorola MPA Latchup?
From: msj <msj@cloud9.net>
Date: Tue, 17 Nov 1998 00:44:07 -0500
Links: << >>  << T >>  << A >>
I was wondering if anyone had an experience with MPA being prone to
latchup and failure upon power up or it's some error in our design.
Trying to locate the problem. Thanks for clues.

Article: 13134
Subject: Xilinx Virtex and ZBT SRAM
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 16 Nov 1998 23:10:58 -0800
Links: << >>  << T >>  << A >>
The Virtex datasheet claims that these chips "Connect directly to
ZBTRAM" but fails to say what special feature comes into play here.

Any idea?

-Arrigo
-- 
Arrigo Benedetti          o         e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	 < >			phone: (626) 395-3695
Pasadena, CA 91125	 / \			fax:   (626) 795-8649
Article: 13135
Subject: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
From: nospam_ees1ht@ee.surrey.ac.uk (Hans)
Date: 17 Nov 1998 08:12:34 GMT
Links: << >>  << T >>  << A >>
In article <01be11a5$0b308dc0$8f6b5ecf@drt1>, dark4room@ix.netcom.com says...
>
>> I can't verify the details of offset and commands. But I can verify that
>> the process works.
>
>Does that work for NT?????
>
>Thanks,
>
>Austin
>
Yes but only if your harddisk format is FAT16 and not NTFS.

Article: 13136
Subject: Is there an alternative to Altera EPM5128 OTP?
From: chakanp@hotmail.com ("Håkan Pettersson")
Date: Tue, 17 Nov 1998 00:24:01 -0800
Links: << >>  << T >>  << A >>
Why don't you use the Altera EPM7128S instead ?1/3 - of the price, faster and also has the ISP-programming via JTAG pins.The only drawback is that it is not available in the 68pin PLCC, only 84PLCC
or 100 TQFP.Since you if you are to use a new part has to do a respin of the PCB you
could also trythe EPM7128A part, that is the 3.3V version.Best RegardsHåkan Pettersson



   -**** Posted from Supernews, Discussions Start Here(tm) ****-
http://www.supernews.com/ - Host to the the World's Discussions & Usenet
Article: 13137
Subject: Re: Xilinx 4k programming
From: z80@ds2.com (Peter)
Date: Tue, 17 Nov 1998 09:04:58 GMT
Links: << >>  << T >>  << A >>
In addition to Philip's reply, I found that the active edge of CCLK
needs to have a risetime faster than about 20ns (can't recall if there
is a spec), but if it is too fast you can get ground bounce and
consequent double clocking, etc. You need a very fast scope to check
this, 300MHz at least.

I don't know why Xilinx didn't use a schmitt trigger input on CCLK -
it would have saved many many problems where clock distribution is
naturally difficult, e.g. where you have 32 FPGAs on one board (the
sort of thing I have been doing).

--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 13138
Subject: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
From: z80@ds2.com (Peter)
Date: Tue, 17 Nov 1998 09:04:58 GMT
Links: << >>  << T >>  << A >>
NT will pick up the volume serial # from the HD directly, but one will
have to boot to DOS to hack it, I am sure.

>Does that work for NT?????


--
Peter.

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E-mail replies to zX80@digiYserve.com but
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Article: 13139
Subject: Re: DES in VHDL
From: z80@ds2.com (Peter)
Date: Tue, 17 Nov 1998 09:04:59 GMT
Links: << >>  << T >>  << A >>

Not even the Russian mafia could afford to buy a 4062 :)

So perhaps posting your design publicly might help to restore law and
order out there.

BTW - how did you do the S-boxes? The CLB tables are just a bit too
narrow to implement a S-box each. Last time I looked at this, just for
fun, I would have put the S-boxes in an external EPROM. Then you can
do it in a much smaller FPGA.

>Now, I've got this solution. Anyone have a problem for it? 8-)


--
Peter.

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E-mail replies to zX80@digiYserve.com but
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Article: 13140
Subject: Re: newbie question about timing
From: z80@ds2.com (Peter)
Date: Tue, 17 Nov 1998 09:04:59 GMT
Links: << >>  << T >>  << A >>

I recall, from one Xilinx seminar a few years ago, the X. rep
explaining that their P&R tools (APR/PPR in those days) worked from
left to right, so if one allocated the IOBs with inputs on the top and
outputs on the bottom (or vice versa) this could screw up the P&R.

Seems odd, because e.g. PCB autorouters don't seem to be sensitive to
this sort of thing.

I never came across this myself, having always drawn things left to
right.

>If you are wiring a bus to the part, and are doing anything
>resembling arithmetic (or counters) on the data from that bus, you'll want
>to arrange the bus along the sides (not top or bottom) of the die with the
>lsb's at the bottom to keep from killing the routing. 


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 13141
Subject: Re: Is there an alternative to Altera EPM5128 OTP?
From: "Arnold Beland" <acbel@worldnet.att.net>
Date: 17 Nov 1998 11:11:10 GMT
Links: << >>  << T >>  << A >>
Color me paranoid, but I prefer to make copying my work at this level
impossible.  I sell complete system designs and furnish detailed info on
everything except the fpga's and software.

Best Regards,

Arnold

"Håkan Pettersson" wrote in message ...
>Why don't you use the Altera EPM7128S instead ?
>1/3 - of the price, faster and also has the ISP-programming via JTAG pins.
>The only drawback is that it is not available in the 68pin PLCC, only
84PLCC
>or 100 TQFP.
>
>Since you if you are to use a new part has to do a respin of the PCB you
>could also try
>the EPM7128A part, that is the 3.3V version.
>
>Best Regards
>Håkan Pettersson
>
>
>
>   -**** Posted from Supernews, Discussions Start Here(tm) ****-
>http://www.supernews.com/ - Host to the the World's Discussions & Usenet


Article: 13142
Subject: Re: Big-Endian vs Little-Endian
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Tue, 17 Nov 1998 11:23:55 GMT
Links: << >>  << T >>  << A >>
On Mon, 16 Nov 1998 17:18:00 GMT, shailbains007@my-dejanews.com wrote:

>In article <364ff418.2246316251@firewall>,
>  yves@px.uk.com (Yves Tchapda) wrote:
>>
>> Hi Shail,
>> Technically speaking, there is no  advantage of Big-Endianness over
>> Little-Endianness. Intel processors are predominantly Little-Endian,
>> while Motorola processors are Big-Endian. Choosing one over the other
>> depends primarily on the overall system.
>
>I'm not totally convinced. Why do Intel designers choose an Endianness that
>is, well, counter-intutive? Take a look at an x86 memory dump to know what I
>mean...  Are you sure there's no difference in the gate counts required to
>make a system Small or Big Endian? Maybe one of them requires much fewer
>gates to implement...

Partly history - the x86is rooted in 8 bit designs.

It's certainly not counter-intuitive if you need to look at only the
least significant byte of a word, or if you need that byte first.
Because that byte is at the address given, not at an offset from that
address which depends on the size of the datatype being accessed...

Consider for example, adding two numbers, in assembly language, with an
1 byte wide accumulator. You have to add the LSByte first, to get the
"carry" for the next addition, and so on. That's a pain with a
big-endian format, and an even bigger pain with a mixture of 16-bit and
32-bit big-endian... (do you look at address n+1 first, or n+3???)

Byte order for a 64-bit (or greater) add would be: 

little-endian system: 

bytes 0,1,2,3,4,5,6,7 (...)

big-endian system: 
bytes 1,0,3,2,5,4,7,6 (if it's a 16-bit machine)
bytes 3,2,1,0,7,6,5,4 (if it's a 32-bit machine)

NOW which is cleaner??? ;)

and by the way, you have to write your own memory addressing routine...

Of course when you have 32 bit accumulators this is an irrelevant pain,
but let's not forget what people were up against. With those
constraints, IMO little endian was far cleaner, and nowadays any
overhead costs required to live with it, are arguably less than the
costs of scrapping the system and starting again...

- Brian.

p.s. hands up if you can read text from a big-endian binary dump!

Article: 13143
Subject: Re: DES in VHDL?
From: aph@cygnus.remove.co.uk (Andrew Haley)
Date: 17 Nov 1998 11:34:05 GMT
Links: << >>  << T >>  << A >>
Christof Paar (christof@ece.WPI.EDU) wrote:
: We studied and optimized DES for the Xilinx XC4000 series
: with -3 speed grade. Here are our main results:

: #pipeline stages  Mb/sec  CLBs used  device 

: 1                 99      262        4008
: 2                 184     433        4013
: 4                 403     741        4028

To clarify, this is 403 M *bits*/sec, about 50 Mbytes/sec.  Very nice.

: More info is in our SAC '98 paper and in Jens Kaps' thesis,
: both of which can be found on our web page at

: http://ece.wpi.edu/Research/crypt

There are plenty of other interesting crypto papers there too; worth a
look.

Andrew.






Article: 13144
Subject: Atmel AT17C010?
From: AT_farhad_abdolian@hotmail.com (Farhad Abdolian)
Date: Tue, 17 Nov 1998 13:11:19 GMT
Links: << >>  << T >>  << A >>
Hi,
I just received the programmer for AT17C010 Configuration FEPROM together with
some samples from their local repr. in Stockholm.

I must say that for 400$ it was a very strange programmer, it seems to be the
first or second prototype with lots of patches but the board is marked at REV 7!
But using flash instead of those damn OTPROM from xilinx is the only alternative
for us right now, so I had to try it!

Anyway, my problem is that I can not use AT17C010 instead of Xilinx 010 PROM!
and wonder if any of you have mannaged to use Atmel's proms without any
modification on the board level?

Appreciate your help,

Best regards,
Farhad A.

Article: 13145
Subject: Re: Synthesizeablel fifo
From: Rene Becker <rene.becker@exp2.physik.uni-giessen.de>
Date: Tue, 17 Nov 1998 13:42:27 +0000
Links: << >>  << T >>  << A >>
Hi!

Take a look at

                       http://www.vhdl-online.de/~vhdl/ .

Here you can find a collection of some synthezizable components.



James LaLone wrote:

> Can someone shed light on building a fifo that can be synthesized?
> The pointers, and ram, are no problem.  What I'm having problems with
> are the flags.  Of course, the fifo that I want to build have
> asynchronous read and write clocks.
> I've looked over Xilinx applications XAPP051 and XAPP131, but they still
> leave me with some implementation questions.
>
> Thanks in advance,
> -Jim

Article: 13146
Subject: Re: Is there an alternative to Altera EPM5128 OTP?
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Tue, 17 Nov 1998 14:31:01 GMT
Links: << >>  << T >>  << A >>

Arnold Beland wrote in message <72rlke$rj@bgtnsc01.worldnet.att.net>...
>Color me paranoid, but I prefer to make copying my work at this level
>impossible.  I sell complete system designs and furnish detailed info on
>everything except the fpga's and software.


The 7128 should be just as safe as the 5128.  Both have security fuses
to prevent reading.  Both can be programmed in a standalone programmer.
The 7128S(A) just have the option of programming in the board.  Reading
as previously mentioned can be disabled with a security fuse.


Steve



Article: 13147
Subject: Re: Low Cost FPGA Development Tools
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 17 Nov 1998 06:59:30 -0800
Links: << >>  << T >>  << A >>
The Programmable Logic Jump Station maintains links to various free or
low-cost development software for FPGAs and CPLDs.  Visit
http://www.optimagic.com/lowcost.html for the latest list.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


Hlebasko@t-online.de wrote in message <72ki6t$tfd$1@news00.btx.dtag.de>...
>I am looking for information for some low cost FPGA development tools for
>learning.  I am trying to improve my "skill set" on my own and I can't
>afford multiple thousand dollar tool sets.
>
>Thanks.
>
>Joseph Hlebasko
>
>


Article: 13148
Subject: Re: Looking for a good documentation on FPGA
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 17 Nov 1998 07:03:20 -0800
Links: << >>  << T >>  << A >>
Oops!  My apologies.  The correct link is
http://www.optimagic.com/tutorials.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


Utku Ozcan wrote in message <36504443.C86FABF7@netas.com.tr>...
>Steven K. Knapp wrote:
>>
>> You can find some tutorial information via The Programmable Logic Jump
>> Station at http://www.optimagic.com/tutorial.html.
>
>  this link doesn't work
>
>  utku
>
>>
>> Also, you may want to check out The Programmable Logic Bookstore at
>> http://www.optimagic.com/books.html#VHDL.
>>
>> -----------------------------------------------------------
>> Steven K. Knapp
>> OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
>> E-mail:  sknapp@optimagic.com
>>    Web:  http://www.optimagic.com
>> -----------------------------------------------------------
>>
>> ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>...
>> >Dear all,
>> >
>> >I am looking for a good documentation on programming FPGA's and
>> >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn
>> >more about FPGA's and ASIC's.
>> >
>> >Thank you.
>> >


Article: 13149
Subject: Re: Example of clock circuit needed !
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 17 Nov 1998 10:30:11 -0500
Links: << >>  << T >>  << A >>
Le mer Michel wrote:
> 
> ovilup wrote:
> 
> > Hello !
> >
> > I am working on an I2C controller. Now, I am designing the
> > internal clock generator. I have an 1.5 MHz internal clock,
> > from which I have to generate the 100 KHz, 90 KHz, 44 KHz
> > 1.5 KHz SCL clocks.
> >
> > Any examples of such an clock generator would be appreciated !
> >
> > Thank you in advance.
> > OL
> 
> Hello
> 
> I do not know exactly what it is but I heard about the direct numeric
> synthesis. It is use in the signal generators to privide a wave of a
> specific frequency.
> 
> Bye.
> Michel.

If I may add my two cents worth to the thread. NCO and DDS are the same
in this context. Both use an phase angle accumulator with a constant
phase step. The output of the phase accumulator can be used directly by
picking the top bit, or by using some number of top bits to generate a
sine wave via a translation table. This digital sine wave would be
converted to an analog signal via a DAC, filtered to remove the "jitter"
component, and run into a comparator to generate a symetrical square
wave, jitter free clock. This is a lot of work for what Ovilup is doing. 

Unfortunately, OL's frequencies are not exact multiples, so that you
can't just divide the 1.5 MHz down to get 90 kHz or 44 kHz exactly. So a
slightly different master frequency is needed or one of the above
methods need to be used, depending on the accuracy required. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.


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