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chrisdekoh@gmail.com wrote: > Hi, > I am wondering if anyone of you have experienced this before. Here > goes the reset problem I am facing now. asynchronous reset in FPGAs > are usually a big NO-NO. from the articles I am reading, the async > reset, normally results in more logic being used to stitch up LUTs > together. I prefer an asynch assert for simulation of the 'no clock running' case. I generate an asynch assert and sync de-assert reset strobe, something like this. http://home.comcast.net/~mike_treseler/reset.vhd http://home.comcast.net/~mike_treseler/reset.pdf It's just a two flop shifter, reset_out is preset with reset_in. A zero is clocked out to de-assert reset_out. > However, the design I am currently working on requires only one of > the blocks to run at 1/4 that of the original clock speed. I am using > a DCM to clock divide the master clock, and the output goes into this > block. I would clock all the flops at the original clock speed, reset everything the same way, and use clock enable strobes for the slower update rates. -- Mike TreselerArticle: 131351
Nico Coesel wrote: > Joerg <notthisjoergsch@removethispacbell.net> wrote: > >> Nico Coesel wrote: >>> Dave <dhschetz@gmail.com> wrote: >>> >>>> Does anybody out there have a good methodology for determining your >>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>> The brute force method is fairly maddening. I'd be curious to hear if >>>> anybody has any 'tricks of the trade' here. >>> I start thinking about how the PCB should be routed the minute I start >>> to draw a schematic. I always draw components with their actual >>> pin-outs. This helps to group pins together and it helps to >>> troubleshoot the circuit when the prototype is on your bench (no need >>> to lookup the pinouts because they are in your diagram). >>> >> For quad opamps like the LM324 as well? > > No. Those (and simple logic) have very few pins. > Ok, then you'd have to modify your statement "always" :-) Am I the nitpicker or what? -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131352
On Sat, 19 Apr 2008 14:17:44 -0700, Joerg <notthisjoergsch@removethispacbell.net> wrote: >Nico Coesel wrote: >> Dave <dhschetz@gmail.com> wrote: >> >>> Does anybody out there have a good methodology for determining your >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>> The brute force method is fairly maddening. I'd be curious to hear if >>> anybody has any 'tricks of the trade' here. >> >> I start thinking about how the PCB should be routed the minute I start >> to draw a schematic. I always draw components with their actual >> pin-outs. This helps to group pins together and it helps to >> troubleshoot the circuit when the prototype is on your bench (no need >> to lookup the pinouts because they are in your diagram). >> > >For quad opamps like the LM324 as well? That can make a schematic harder >to read and will also cause a nightmare if the layouter wants to swap >amp A with amp C and stuff like that. > >[...] A quad opamp doesn't have 1738 pins! JohnArticle: 131353
John Larkin wrote: > On Sat, 19 Apr 2008 14:17:44 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> Nico Coesel wrote: >>> Dave <dhschetz@gmail.com> wrote: >>> >>>> Does anybody out there have a good methodology for determining your >>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>> The brute force method is fairly maddening. I'd be curious to hear if >>>> anybody has any 'tricks of the trade' here. >>> I start thinking about how the PCB should be routed the minute I start >>> to draw a schematic. I always draw components with their actual >>> pin-outs. This helps to group pins together and it helps to >>> troubleshoot the circuit when the prototype is on your bench (no need >>> to lookup the pinouts because they are in your diagram). >>> >> For quad opamps like the LM324 as well? That can make a schematic harder >> to read and will also cause a nightmare if the layouter wants to swap >> amp A with amp C and stuff like that. >> >> [...] > > A quad opamp doesn't have 1738 pins! > Well, yes, I was just wondering about whether Nico really always draws the physical package. Looks like he doesn't for smaller stuff. With 1738 pins you can only hope that the FPGA has enough routing resources. That used to be a major pain in the early 90's. Don't know about nowadays since other guys design the parts with the big FPGAs. And I am glad I don't have to deal with BGA, at least not with large ones ... -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131354
Hi there - I am continuing to attempt to learn VHDL this weekend! Currently I'm trying to interface to the quadrature encoder on my Spartan 3E Starter Kit. It outputs normal quadrature signals. So, I tried to write a very simple bit of code for this purpose, which just checks which edge on which signal occurred and then checks the state of the other signal and infers if the count should be incremented or decremented from that. My code is at the bottom of my post. In theory this method of quadrature decoding should work perfectly, unless I'm forgetting something. But for some reason which I'm afraid I don't understand this is not synthesizable. I liked the idea of using this method for quadrature decoding as it didn't require me to deal with storing the previous state - the use of the falling_edge() and rising_edge() functions did that for me. Xilinx ISE help brought me to this page: http://www.xilinx.com/support/answers/14047.htm. However, I don't have any embedded 'event statements, or any 'event statements at all, for that matter (unless again I'm missing something). What exactly am I doing wrong, and is there a way to fix it? Thanks so much! -Michael library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity hello_world is port ( clk, enc_a, enc_b : in std_logic; switches : in std_logic_vector (3 downto 0); led : out std_logic_vector (7 downto 0) ); end hello_world; architecture rtl of hello_world is signal cnt : unsigned (30 downto 0); signal encval : unsigned (7 downto 0); signal enccnt : unsigned (7 downto 0); begin process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; encval <= "000000" & enc_b & enc_a; end if; end process; process (enc_a, enc_b) begin if (rising_edge(enc_a) and enc_b = '1') then enccnt <= enccnt - 1; elsif (rising_edge(enc_a) and enc_b = '0') then enccnt <= enccnt + 1; elsif (falling_edge(enc_a) and enc_b = '1') then enccnt <= enccnt + 1; elsif (falling_edge(enc_a) and enc_b = '0') then enccnt <= enccnt - 1; elsif (rising_edge(enc_b) and enc_a = '1') then enccnt <= enccnt + 1; elsif (rising_edge(enc_b) and enc_a = '0') then enccnt <= enccnt - 1; elsif (falling_edge(enc_b) and enc_a = '1') then enccnt <= enccnt - 1; elsif (falling_edge(enc_b) and enc_a = '0') then enccnt <= enccnt + 1; end if; end process; led <= std_logic_vector(cnt(30 downto 23)) when switches(0)='0' else std_logic_vector(encval); end rtl;Article: 131355
John Larkin wrote: > > A quad opamp doesn't have 1738 pins! That will only happen if Bloggs designs it. :( -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htmArticle: 131356
On Sun, 20 Apr 2008 14:13:21 -0700, Joerg <notthisjoergsch@removethispacbell.net> wrote: >John Larkin wrote: >> On Sat, 19 Apr 2008 14:17:44 -0700, Joerg >> <notthisjoergsch@removethispacbell.net> wrote: >> >>> Nico Coesel wrote: >>>> Dave <dhschetz@gmail.com> wrote: >>>> >>>>> Does anybody out there have a good methodology for determining your >>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>> anybody has any 'tricks of the trade' here. >>>> I start thinking about how the PCB should be routed the minute I start >>>> to draw a schematic. I always draw components with their actual >>>> pin-outs. This helps to group pins together and it helps to >>>> troubleshoot the circuit when the prototype is on your bench (no need >>>> to lookup the pinouts because they are in your diagram). >>>> >>> For quad opamps like the LM324 as well? That can make a schematic harder >>> to read and will also cause a nightmare if the layouter wants to swap >>> amp A with amp C and stuff like that. >>> >>> [...] >> >> A quad opamp doesn't have 1738 pins! >> > >Well, yes, I was just wondering about whether Nico really always draws >the physical package. Looks like he doesn't for smaller stuff. > >With 1738 pins you can only hope that the FPGA has enough routing >resources. That used to be a major pain in the early 90's. Don't know >about nowadays since other guys design the parts with the big FPGAs. And >I am glad I don't have to deal with BGA, at least not with large ones ... The biggest ones we use are Sparten 3's with 456 balls on 1 mm centers. We haven't had any routing problems so far, doing pretty complex stuff at 128 MHz clock rates. Our in-house BGA soldering yield, to date, is exactly 100%. BGAs seem to be a lot easier to solder reliably than fine-pitch leaded parts. Easier to inspect, too, since you can't inspect them at all. JohnArticle: 131357
On Sun, 20 Apr 2008 17:33:16 -0400, "Michael A. Terrell" <mike.terrell@earthlink.net> wrote: > >John Larkin wrote: >> >> A quad opamp doesn't have 1738 pins! > > > That will only happen if Bloggs designs it. :( Bloggs has several times stated that he doesn't design electronics. He hasn't stated what he actually does. JohnArticle: 131358
John Larkin wrote: > > On Sun, 20 Apr 2008 17:33:16 -0400, "Michael A. Terrell" > <mike.terrell@earthlink.net> wrote: > > > > >John Larkin wrote: > >> > >> A quad opamp doesn't have 1738 pins! > > > > > > That will only happen if Bloggs designs it. :( > > Bloggs has several times stated that he doesn't design electronics. He > hasn't stated what he actually does. He stated that he does absolutely nothing. It might be the only time he has ever told the truth. -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htmArticle: 131359
Michael wrote:
> What exactly am I doing wrong
1. Using inputs as clocks.
2. Using two clocks in a process.
and is there a way to fix it?
Declare as many registers as you need,
but put everything in your first process.
Have a look at my examples.
-- Mike Treseler
Article: 131360Michael wrote: > In theory this method of quadrature decoding should work perfectly, > unless I'm forgetting something. The quadrature encoder on the Spartan 3E Starter Kit is mechanical, you should implement some debouncing. Maybe some simple holdoff is sufficient, but if there are fast crosstalk glitches, a simple low pass filter (in VHDL) would be a good idea, too. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 131361
On Apr 20, 6:42 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > Michael wrote: > > What exactly am I doing wrong > > 1. Using inputs as clocks. > 2. Using two clocks in a process. So rising_edge() and falling_edge() can only be used with clocks? > and is there a way to fix it? > > Declare as many registers as you need, > but put everything in your first process. Why does everything have to be in one process? Is there a reason it's objectionable to have one process that is sensitive to only my clock and one process that's only sensitive to a couple inputs? And so you're suggesting I go with a state based approach? Or something else? What are these extra registers for? > Have a look at my examples. > > -- Mike Treseler What examples are you referring to? Thanks! -MichaelArticle: 131362
On Apr 20, 6:50=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Michael wrote: > > In theory this method of quadrature decoding should work perfectly, > > unless I'm forgetting something. > > The quadrature encoder on the Spartan 3E Starter Kit is mechanical, you > should implement some debouncing. Maybe some simple holdoff is sufficient,= > but if there are fast crosstalk glitches, a simple low pass filter (in > VHDL) would be a good idea, too. > > -- > Frank Buss Hi Frank - I thought about debouncing and - unless I'm being dumb - I think as long as only one input is changing at a time, bounce won't affect this approach in the steady state. I mean that if I turn it 4 counts, it might count something like 0 1 2 3 2 3 4 3 4. But the final value will be correct. -MichaelArticle: 131363
Michael, you might prefer my much simpler solution, as described in a recent blog on the Xilinx forums website. http://forums.xilinx.com/xlnx/blog/article?message.uid=3D9394 I designed this a few years ago, and we use it in our programmable frequency gererator, that I have mentioned here a few times. Ken Chapman then took the exact same shaft encoder for the Spartan eval board. The design is absolutely bounce-proof, no Mickey Mouse low-pass filters or other analog nonsense. I hope the explanation is sufficient. Viel Spa=DF Peter AlfkeArticle: 131364
In article <TlOOj.2407$I55.1437@newssvr22.news.prodigy.net>, notthisjoergsch@removethispacbell.net says... > John Larkin wrote: > > On Sat, 19 Apr 2008 14:17:44 -0700, Joerg > > <notthisjoergsch@removethispacbell.net> wrote: > > > >> Nico Coesel wrote: > >>> Dave <dhschetz@gmail.com> wrote: > >>> > >>>> Does anybody out there have a good methodology for determining your > >>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > >>>> The brute force method is fairly maddening. I'd be curious to hear if > >>>> anybody has any 'tricks of the trade' here. > >>> I start thinking about how the PCB should be routed the minute I start > >>> to draw a schematic. I always draw components with their actual > >>> pin-outs. This helps to group pins together and it helps to > >>> troubleshoot the circuit when the prototype is on your bench (no need > >>> to lookup the pinouts because they are in your diagram). > >>> > >> For quad opamps like the LM324 as well? That can make a schematic harder > >> to read and will also cause a nightmare if the layouter wants to swap > >> amp A with amp C and stuff like that. > >> > >> [...] > > > > A quad opamp doesn't have 1738 pins! > > > > Well, yes, I was just wondering about whether Nico really always draws > the physical package. Looks like he doesn't for smaller stuff. > > With 1738 pins you can only hope that the FPGA has enough routing > resources. That used to be a major pain in the early 90's. Don't know > about nowadays since other guys design the parts with the big FPGAs. And I had a *lot* of routing problems with the SpartanXL series. I had lotsa logic left but if it would route it would take days. I didn't have any problems, at the time, with Virtex or Vertex-E. Now the Virtex-2s and 4s route in a small number of minutes with no errors. > I am glad I don't have to deal with BGA, at least not with large ones ... I don't deal with them either. That's the layouter's job. ;-) Actually, right now I just work on what goes into them (though I had to completely redesign a badly screwed up board in December, which we *still* don't have back). -- KeithArticle: 131365
John Larkin wrote: > On Sun, 20 Apr 2008 14:13:21 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> John Larkin wrote: >>> On Sat, 19 Apr 2008 14:17:44 -0700, Joerg >>> <notthisjoergsch@removethispacbell.net> wrote: >>> >>>> Nico Coesel wrote: >>>>> Dave <dhschetz@gmail.com> wrote: >>>>> >>>>>> Does anybody out there have a good methodology for determining your >>>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>>> anybody has any 'tricks of the trade' here. >>>>> I start thinking about how the PCB should be routed the minute I start >>>>> to draw a schematic. I always draw components with their actual >>>>> pin-outs. This helps to group pins together and it helps to >>>>> troubleshoot the circuit when the prototype is on your bench (no need >>>>> to lookup the pinouts because they are in your diagram). >>>>> >>>> For quad opamps like the LM324 as well? That can make a schematic harder >>>> to read and will also cause a nightmare if the layouter wants to swap >>>> amp A with amp C and stuff like that. >>>> >>>> [...] >>> A quad opamp doesn't have 1738 pins! >>> >> Well, yes, I was just wondering about whether Nico really always draws >> the physical package. Looks like he doesn't for smaller stuff. >> >> With 1738 pins you can only hope that the FPGA has enough routing >> resources. That used to be a major pain in the early 90's. Don't know >> about nowadays since other guys design the parts with the big FPGAs. And >> I am glad I don't have to deal with BGA, at least not with large ones ... > > The biggest ones we use are Sparten 3's with 456 balls on 1 mm > centers. We haven't had any routing problems so far, doing pretty > complex stuff at 128 MHz clock rates. Our in-house BGA soldering > yield, to date, is exactly 100%. BGAs seem to be a lot easier to > solder reliably than fine-pitch leaded parts. Easier to inspect, too, > since you can't inspect them at all. > The latter is a concern in my field (medical). We need to be able to inspect. The other concern is involuntary board flexing. Most of my designs have to sustain under tortures such as freighter pilots ploughing through a storm in the Carribean in airplanes as old as a DC-3 or a trucker in Africa who is lead-footing it over a few hundred miles of washboard road. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131366
> Hi Frank - I thought about debouncing and - unless I'm being dumb - I > think as long as only one input is changing at a time, bounce won't > affect this approach in the steady state. I mean that if I turn it 4 > counts, it might count something like 0 1 2 3 2 3 4 3 4. But the final > value will be correct. There are different classes of Quad encoder. The Simplest feed one phase into a CLK and the other into DIRN, but that counts only once per whole cycle. The best designs can count on every edge, and can tolerate a chattering edge. You might also want to catch illegal state jumps (missed states), as that indicates something is amiss in your design. One easy to understand way to code this, is to create a internal 2 bit phase engine, and lock it to the external sampled edges. That design makes illegal state jumps easy to catch. You have a simple state engine, with 2 IP bits, 2 Present bits, [16 combinations] and output CE, DIRN, and ERR, as well as 2 bits for Next state. -jgArticle: 131367
Michael wrote: (snip on quadrature decoders) > Hi Frank - I thought about debouncing and - unless I'm being dumb - I > think as long as only one input is changing at a time, bounce won't > affect this approach in the steady state. I mean that if I turn it 4 > counts, it might count something like 0 1 2 3 2 3 4 3 4. But the final > value will be correct. As long as the bounce isn't faster than the counter can count, yes. I like the clocked design that Peter A. has in another post. I believe that one works as long as the clock is faster than the fastest possible real count. Bounces might be missed, but the count will be right. Also, I believe one should reset the counter on the first index pulse and not on subsequent ones. -- glenArticle: 131368
Frank Buss wrote: (snip) > You can't use IF outside of processes, a bit like that you can't use the C > IF outside of functions. You could write it like this: > led <= cnt(30 downto 23) when switches(0)=0 else enccnt; > A bit like the ?-operator in C. If you use verilog, the ?: operator is just like the C operator! -- glenArticle: 131369
On Apr 20, 5:12=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Michael wrote: > > (snip on quadrature decoders) > > > Hi Frank - I thought about debouncing and - unless I'm being dumb - I > > think as long as only one input is changing at a time, bounce won't > > affect this approach in the steady state. I mean that if I turn it 4 > > counts, it might count something like 0 1 2 3 2 3 4 3 4. But the final > > value will be correct. > > As long as the bounce isn't faster than the counter can count, yes. > > I like the clocked design that Peter A. has in another post. > I believe that one works as long as the clock is faster than > the fastest possible real count. =A0Bounces might be missed, but > the count will be right. > > Also, I believe one should reset the counter on the first index > pulse and not on =A0subsequent ones. > > -- glen Bounces should (or must) be missed.. That's the whole purpose of the circuit .:-) Peter..Article: 131370
Hi Mike,
> > However, the design I am currently working on requires only one of
> > the blocks to run at 1/4 that of the original clock speed. I am using
> > a DCM to clock divide the master clock, and the output goes into this
> > block.
>
> I would clock all the flops at the original clock speed,
> reset everything the same way, and use
> clock enable strobes for the slower update rates.
>
> -- Mike Treseler
thanks for your input. When you mean clock enable strobe, do you
mean... the following?
process (clk)
if clk=1 and clk'event then
if res = '1'
else
if clock_enable = '1'
end if;
end if;
end if;
--then clock_enable will be in my case asserted one in every 4 clocks
to achieve a f/4 MHz kind of data rate...
If my understanding is correct, then I have another question. The
maximum synthesizable frequency of a core used in the design cannot
run at clock speed and only at 1/4 clock speed. currently, I have thus
2 clock domains in this design
1) 1 clock runnning at f MHz
2) 1 clock running at f/4 frequency.
I have prevented potential clock domain crossing problems by piping
data already into an async FIFO (data entering the design written into
the FIFO at f MHz, data read out at f/4 MHz which goes into the core
also clocked at f/4 MHz).
Since you advised to use the strobe method as I understood above, then
how do i go about clocking the core that can run at only f/4 MHz max
and still not run into the reset problem stated above?
thanks again for your help.
Chris
Article: 131371On Apr 20, 6:30=A0pm, chrisde...@gmail.com wrote: > Hi Mike, > > > > =A0 However, the design I am currently working on requires only one of= > > > the blocks to run at 1/4 that of the original clock speed. I am using > > > a DCM to clock divide the master clock, and the output goes into this > > > block. > > > I would clock all the flops at the original clock speed, > > reset everything the same way, and use > > clock enable strobes for the slower update rates. > > > =A0 -- Mike Treseler > > =A0 =A0thanks for your input. When you mean clock enable strobe, do you > mean... the following? > > process (clk) > =A0 =A0if clk=3D1 and clk'event then > =A0 =A0 =A0if res =3D '1' > > =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0if clock_enable =3D '1' > > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0end if; > =A0 =A0end if; > > --then clock_enable will be in my case asserted one in every 4 clocks > to achieve a f/4 MHz kind of data rate... > > =A0 =A0 If my understanding is correct, then I have another question. The > maximum synthesizable frequency of a core used in the design cannot > run at clock speed and only at 1/4 clock speed. currently, I have thus > 2 clock domains in this design > > 1) 1 clock runnning at f MHz > 2) 1 clock running at f/4 frequency. > > I have prevented potential clock domain crossing problems by piping > data already into an async FIFO (data entering the design written into > the FIFO at f MHz, data read out at f/4 MHz which goes into the core > also clocked at f/4 MHz). > > Since you advised to use the strobe method as I understood above, then > how do i go about clocking the core that can run at only f/4 MHz max > and still not run into the reset problem stated above? > > thanks again for your help. > Chris If you use a global clock to distribute the fast clock, but us CE to disable each flip-flop for 3 out of 4 clock ticks, then that part of your design really runs at the quarter clock speed. The flip-flops see only every fourth clock tick, therefore your design will work as you expect. Peter AlfkeArticle: 131372
chrisdekoh@gmail.com wrote:
> Since you advised to use the strobe method as I understood above, then
> how do i go about clocking the core that can run at only f/4 MHz max
> and still not run into the reset problem stated above?
There is only one clock domain.
The reset circuit is separate.
See Peter's answer.
Post to comp.lang.vhd if you don't figure it out.
-- Mike Treseler
Article: 131373Hi Peter, I do not have this luxury. The core which is running at f/4 clock is a core originally written in Handel C and given to me as a ngc file and not in VHDL. The maximum synthesizable speed of this core is only at f/4 MHz. The core thus has to run at an f/4 clock. With this set of restrictions in mind, could there still be a solution to the reset problem? ChrisArticle: 131374
Michael wrote:
> So rising_edge() and falling_edge() can only be used with clocks?
For synchronous designs, yes.
> Why does everything have to be in one process?
It doesn't. Just a suggestion.
Peter has the problem solved for you.
Post a question to comp.lang.vhdl if you need more help.
-- Mike Treseler
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